1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \ 2; RUN: FileCheck %s -check-prefix=CHECK-LE 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \ 4; RUN: FileCheck %s -check-prefix=CHECK-BE 5 6; Possible LE ShuffleVector masks (Case 1): 7; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3) 8; ShuffleVector((vector int)a, vector(int)b, 7, 0, 1, 2) 9; ShuffleVector((vector int)a, vector(int)b, 6, 7, 0, 1) 10; ShuffleVector((vector int)a, vector(int)b, 5, 6, 7, 0) 11; which targets at: 12; xxsldwi a, b, 0 13; xxsldwi a, b, 1 14; xxsldwi a, b, 2 15; xxsldwi a, b, 3 16; Possible LE Swap ShuffleVector masks (Case 2): 17; ShuffleVector((vector int)a, vector(int)b, 4, 5, 6, 7) 18; ShuffleVector((vector int)a, vector(int)b, 3, 4, 5, 6) 19; ShuffleVector((vector int)a, vector(int)b, 2, 3, 4, 5) 20; ShuffleVector((vector int)a, vector(int)b, 1, 2, 3, 4) 21; which targets at: 22; xxsldwi b, a, 0 23; xxsldwi b, a, 1 24; xxsldwi b, a, 2 25; xxsldwi b, a, 3 26; Possible LE ShuffleVector masks when a == b, b is undef (Case 3): 27; ShuffleVector((vector int)a, vector(int)a, 0, 1, 2, 3) 28; ShuffleVector((vector int)a, vector(int)a, 3, 0, 1, 2) 29; ShuffleVector((vector int)a, vector(int)a, 2, 3, 0, 1) 30; ShuffleVector((vector int)a, vector(int)a, 1, 2, 3, 0) 31; which targets at: 32; xxsldwi a, a, 0 33; xxsldwi a, a, 1 34; xxsldwi a, a, 2 35; xxsldwi a, a, 3 36 37; Possible BE ShuffleVector masks (Case 4): 38; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3) 39; ShuffleVector((vector int)a, vector(int)b, 1, 2, 3, 4) 40; ShuffleVector((vector int)a, vector(int)b, 2, 3, 4, 5) 41; ShuffleVector((vector int)a, vector(int)b, 3, 4, 5, 6) 42; which targets at: 43; xxsldwi b, a, 0 44; xxsldwi b, a, 1 45; xxsldwi a, a, 2 46; xxsldwi a, a, 3 47; Possible BE Swap ShuffleVector masks (Case 5): 48; ShuffleVector((vector int)a, vector(int)b, 4, 5, 6, 7) 49; ShuffleVector((vector int)a, vector(int)b, 5, 6, 7, 0) 50; ShuffleVector((vector int)a, vector(int)b, 6, 7, 0, 1) 51; ShuffleVector((vector int)a, vector(int)b, 7, 0, 1, 2) 52; which targets at: 53; xxsldwi b, a, 0 54; xxsldwi b, a, 1 55; xxsldwi b, a, 2 56; xxsldwi b, a, 3 57; Possible BE ShuffleVector masks when a == b, b is undef (Case 6): 58; ShuffleVector((vector int)a, vector(int)b, 0, 1, 2, 3) 59; ShuffleVector((vector int)a, vector(int)a, 1, 2, 3, 0) 60; ShuffleVector((vector int)a, vector(int)a, 2, 3, 0, 1) 61; ShuffleVector((vector int)a, vector(int)a, 3, 0, 1, 2) 62; which targets at: 63; xxsldwi a, a, 0 64; xxsldwi a, a, 1 65; xxsldwi a, a, 2 66; xxsldwi a, a, 3 67 68define <4 x i32> @check_le_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) { 69entry: 70 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 71 ret <4 x i32> %0 72; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_0 73; CHECK-LE: blr 74} 75 76define <4 x i32> @check_le_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) { 77entry: 78 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 7, i32 0, i32 1, i32 2> 79 ret <4 x i32> %0 80; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_1 81; CHECK-LE: xxsldwi 34, 34, 35, 1 82; CHECK-LE: blr 83} 84 85define <4 x i32> @check_le_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) { 86entry: 87 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 6, i32 7, i32 0, i32 1> 88 ret <4 x i32> %0 89; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_2 90; CHECK-LE: xxsldwi 34, 34, 35, 2 91; CHECK-LE: blr 92} 93 94define <4 x i32> @check_le_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) { 95entry: 96 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 5, i32 6, i32 7, i32 0> 97 ret <4 x i32> %0 98; CHECK-LE-LABEL: @check_le_vec_sldwi_va_vb_3 99; CHECK-LE: xxsldwi 34, 34, 35, 3 100; CHECK-LE: blr 101} 102 103define <4 x i32> @check_le_swap_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) { 104entry: 105 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 106 ret <4 x i32> %0 107; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_0 108; CHECK-LE: vmr 2, 3 109; CHECK-LE: blr 110} 111 112define <4 x i32> @check_le_swap_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) { 113entry: 114 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 115 ret <4 x i32> %0 116; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_1 117; CHECK-LE: xxsldwi 34, 35, 34, 1 118; CHECK-LE: blr 119} 120 121define <4 x i32> @check_le_swap_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) { 122entry: 123 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 2, i32 3, i32 4, i32 5> 124 ret <4 x i32> %0 125; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_2 126; CHECK-LE: xxsldwi 34, 35, 34, 2 127; CHECK-LE: blr 128} 129 130define <4 x i32> @check_le_swap_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) { 131entry: 132 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 1, i32 2, i32 3, i32 4> 133 ret <4 x i32> %0 134; CHECK-LE-LABEL: @check_le_swap_vec_sldwi_va_vb_3 135; CHECK-LE: xxsldwi 34, 35, 34, 3 136; CHECK-LE: blr 137} 138 139define <4 x i32> @check_le_vec_sldwi_va_undef_0(<4 x i32> %VA) { 140entry: 141 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 142 ret <4 x i32> %0 143; CHECK-LE-LABEL: @check_le_vec_sldwi_va_undef_0 144; CHECK-LE: blr 145} 146 147define <4 x i32> @check_le_vec_sldwi_va_undef_1(<4 x i32> %VA) { 148entry: 149 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2> 150 ret <4 x i32> %0 151; CHECK-BE-LABEL: @check_le_vec_sldwi_va_undef_1 152; CHECK-LE: xxsldwi 34, 34, 34, 1 153; CHECK-LE: blr 154} 155 156define <4 x i32> @check_le_vec_sldwi_va_undef_2(<4 x i32> %VA) { 157entry: 158 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1> 159 ret <4 x i32> %0 160; CHECK-LE-LABEL: @check_le_vec_sldwi_va_undef_2 161; CHECK-LE: xxswapd 34, 34 162; CHECK-LE: blr 163} 164 165define <4 x i32> @check_le_vec_sldwi_va_undef_3(<4 x i32> %VA) { 166entry: 167 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> 168 ret <4 x i32> %0 169; CHECK-LE-LABEL: @check_le_vec_sldwi_va_undef_3 170; CHECK-LE: xxsldwi 34, 34, 34, 3 171; CHECK-LE: blr 172} 173 174define <4 x i32> @check_be_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) { 175entry: 176 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 177 ret <4 x i32> %0 178; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_0 179; CHECK-BE: blr 180} 181 182define <4 x i32> @check_be_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) { 183entry: 184 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 1, i32 2, i32 3, i32 4> 185 ret <4 x i32> %0 186; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_1 187; CHECK-BE: xxsldwi 34, 34, 35, 1 188; CHECK-BE: blr 189} 190 191define <4 x i32> @check_be_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) { 192entry: 193 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 2, i32 3, i32 4, i32 5> 194 ret <4 x i32> %0 195; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_2 196; CHECK-BE: xxsldwi 34, 34, 35, 2 197; CHECK-BE: blr 198} 199 200define <4 x i32> @check_be_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) { 201entry: 202 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 3, i32 4, i32 5, i32 6> 203 ret <4 x i32> %0 204; CHECK-BE-LABEL: @check_be_vec_sldwi_va_vb_3 205; CHECK-BE: xxsldwi 34, 34, 35, 3 206; CHECK-BE: blr 207} 208 209define <4 x i32> @check_be_swap_vec_sldwi_va_vb_0(<4 x i32> %VA, <4 x i32> %VB) { 210entry: 211 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 212 ret <4 x i32> %0 213; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_0 214; CHECK-LE: vmr 2, 3 215; CHECK-BE: blr 216} 217 218define <4 x i32> @check_be_swap_vec_sldwi_va_vb_1(<4 x i32> %VA, <4 x i32> %VB) { 219entry: 220 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 5, i32 6, i32 7, i32 0> 221 ret <4 x i32> %0 222; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_1 223; CHECK-BE: xxsldwi 34, 35, 34, 1 224; CHECK-BE: blr 225} 226 227define <4 x i32> @check_be_swap_vec_sldwi_va_vb_2(<4 x i32> %VA, <4 x i32> %VB) { 228entry: 229 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 6, i32 7, i32 0, i32 1> 230 ret <4 x i32> %0 231; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_2 232; CHECK-BE: xxsldwi 34, 35, 34, 2 233; CHECK-BE: blr 234} 235 236define <4 x i32> @check_be_swap_vec_sldwi_va_vb_3(<4 x i32> %VA, <4 x i32> %VB) { 237entry: 238 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB, <4 x i32> <i32 7, i32 0, i32 1, i32 2> 239 ret <4 x i32> %0 240; CHECK-BE-LABEL: @check_be_swap_vec_sldwi_va_vb_3 241; CHECK-BE: xxsldwi 34, 35, 34, 3 242; CHECK-BE: blr 243} 244 245define <4 x i32> @check_be_vec_sldwi_va_undef_0(<4 x i32> %VA) { 246entry: 247 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 248 ret <4 x i32> %0 249; CHECK-LE-LABEL: @check_be_vec_sldwi_va_undef_0 250; CHECK-BE: blr 251} 252 253define <4 x i32> @check_be_vec_sldwi_va_undef_1(<4 x i32> %VA) { 254entry: 255 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> 256 ret <4 x i32> %0 257; CHECK-BE-LABEL: @check_be_vec_sldwi_va_undef_1 258; CHECK-BE: xxsldwi 34, 34, 34, 1 259; CHECK-BE: blr 260} 261 262define <4 x i32> @check_be_vec_sldwi_va_undef_2(<4 x i32> %VA) { 263entry: 264 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 0, i32 1> 265 ret <4 x i32> %0 266; CHECK-BE-LABEL: @check_be_vec_sldwi_va_undef_2 267; CHECK-BE: xxswapd 34, 34 268; CHECK-BE: blr 269} 270 271define <4 x i32> @check_be_vec_sldwi_va_undef_3(<4 x i32> %VA) { 272entry: 273 %0 = shufflevector <4 x i32> %VA, <4 x i32> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2> 274 ret <4 x i32> %0 275; CHECK-BE-LABEL: @check_be_vec_sldwi_va_undef_3 276; CHECK-BE: xxsldwi 34, 34, 34, 3 277; CHECK-BE: blr 278} 279 280; More test cases to test different types of vector inputs 281define <16 x i8> @test_le_vec_sldwi_v16i8_v16i8(<16 x i8> %VA, <16 x i8> %VB) { 282 entry: 283 %0 = shufflevector <16 x i8> %VA, <16 x i8> %VB,<16 x i32> <i32 28, i32 29, i32 30, i32 31,i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> 284 ret <16 x i8> %0 285; CHECK-LE-LABEL: @test_le_vec_sldwi_v16i8_v16i8 286; CHECK-LE: xxsldwi 34, 34, 35, 1 287; CHECK-LE: blr 288} 289 290define <8 x i16> @test_le_vec_sldwi_v8i16_v8i16(<8 x i16> %VA, <8 x i16> %VB) { 291 entry: 292 %0 = shufflevector <8 x i16> %VA, <8 x i16> %VB,<8 x i32> <i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5> 293 ret <8 x i16> %0 294; CHECK-LE-LABEL: @test_le_vec_sldwi_v8i16_v8i16 295; CHECK-LE: xxsldwi 34, 34, 35, 1 296; CHECK-LE: blr 297} 298 299; Note here xxpermdi 34, 34, 35, 2 <=> xxsldwi 34, 34, 35, 2 300define <2 x i64> @test_be_vec_sldwi_v2i64_v2i64(<2 x i64> %VA, <2 x i64> %VB) { 301 entry: 302 %0 = shufflevector <2 x i64> %VA, <2 x i64> %VB,<2 x i32> <i32 3, i32 0> 303 ret <2 x i64> %0 304; CHECK-LE-LABEL: @test_be_vec_sldwi_v2i64_v2i64 305; CHECK-LE: xxpermdi 34, 34, 35, 2 306; CHECK-LE: blr 307} 308