xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec_revb.ll (revision 2d9890775f523a7a7ed2d7d064273bf7e28ebf20) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=pwr9 < %s | FileCheck %s
4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
5
6define <8 x i16> @testXXBRH(<8 x i16> %a) {
7; CHECK-LABEL: testXXBRH:
8; CHECK:       # %bb.0: # %entry
9; CHECK-NEXT:    xxbrh 34, 34
10; CHECK-NEXT:    blr
11
12entry:
13  %0 = bitcast <8 x i16> %a to <16 x i8>
14  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
15  %2 = bitcast <16 x i8> %1 to <8 x i16>
16  ret <8 x i16> %2
17}
18
19define <4 x i32> @testXXBRW(<4 x i32> %a) {
20; CHECK-LABEL: testXXBRW:
21; CHECK:       # %bb.0: # %entry
22; CHECK-NEXT:    xxbrw 34, 34
23; CHECK-NEXT:    blr
24
25entry:
26  %0 = bitcast <4 x i32> %a to <16 x i8>
27  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
28  %2 = bitcast <16 x i8> %1 to <4 x i32>
29  ret <4 x i32> %2
30}
31
32define <2 x double> @testXXBRD(<2 x double> %a) {
33; CHECK-LABEL: testXXBRD:
34; CHECK:       # %bb.0: # %entry
35; CHECK-NEXT:    xxbrd 34, 34
36; CHECK-NEXT:    blr
37
38entry:
39  %0 = bitcast <2 x double> %a to <16 x i8>
40  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
41  %2 = bitcast <16 x i8> %1 to <2 x double>
42  ret <2 x double> %2
43}
44
45define <1 x i128> @testXXBRQ(<1 x i128> %a) {
46; CHECK-LABEL: testXXBRQ:
47; CHECK:       # %bb.0: # %entry
48; CHECK-NEXT:    xxbrq 34, 34
49; CHECK-NEXT:    blr
50
51entry:
52  %0 = bitcast <1 x i128> %a to <16 x i8>
53  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
54  %2 = bitcast <16 x i8> %1 to <1 x i128>
55  ret <1 x i128> %2
56}
57
58define <4 x i32> @testXXBRD_With_LogicalOp(<4 x i32> %a, <4 x i32> %b) {
59; CHECK-LABEL: testXXBRD_With_LogicalOp:
60; CHECK:       # %bb.0: # %entry
61; CHECK-NEXT:    xxland 0, 34, 35
62; CHECK-NEXT:    xxbrw 34, 0
63; CHECK-NEXT:    blr
64entry:
65  %0 = bitcast <4 x i32> %a to <16 x i8>
66  %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
67  %2 = bitcast <16 x i8> %1 to <4 x i32>
68  %3 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %b)
69  %4 = and <4 x i32> %2, %3
70  ret <4 x i32> %4
71}
72declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
73