xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll (revision c1d0118459c814824b8a4c8f423b6b91d16af785) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-LE
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-gnu-linux -mcpu=pwr9 < %s | FileCheck %s -check-prefix=CHECK-BE
4
5define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
6; CHECK-LE-LABEL: test1:
7; CHECK-LE:       # %bb.0: # %entry
8; CHECK-LE-NEXT:    clrldi 3, 5, 32
9; CHECK-LE-NEXT:    vextubrx 3, 3, 2
10; CHECK-LE-NEXT:    clrldi 3, 3, 56
11; CHECK-LE-NEXT:    blr
12;
13; CHECK-BE-LABEL: test1:
14; CHECK-BE:       # %bb.0: # %entry
15; CHECK-BE-NEXT:    clrldi 3, 5, 32
16; CHECK-BE-NEXT:    vextublx 3, 3, 2
17; CHECK-BE-NEXT:    clrldi 3, 3, 56
18; CHECK-BE-NEXT:    blr
19
20entry:
21  %vecext = extractelement <16 x i8> %a, i32 %index
22  ret i8 %vecext
23}
24
25define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
26; CHECK-LE-LABEL: test2:
27; CHECK-LE:       # %bb.0: # %entry
28; CHECK-LE-NEXT:    clrldi 3, 5, 32
29; CHECK-LE-NEXT:    vextubrx 3, 3, 2
30; CHECK-LE-NEXT:    extsb 3, 3
31; CHECK-LE-NEXT:    blr
32;
33; CHECK-BE-LABEL: test2:
34; CHECK-BE:       # %bb.0: # %entry
35; CHECK-BE-NEXT:    clrldi 3, 5, 32
36; CHECK-BE-NEXT:    vextublx 3, 3, 2
37; CHECK-BE-NEXT:    extsb 3, 3
38; CHECK-BE-NEXT:    blr
39
40entry:
41  %vecext = extractelement <16 x i8> %a, i32 %index
42  ret i8 %vecext
43}
44
45define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
46; CHECK-LE-LABEL: test3:
47; CHECK-LE:       # %bb.0: # %entry
48; CHECK-LE-NEXT:    clrldi 3, 5, 32
49; CHECK-LE-NEXT:    rlwinm 3, 3, 1, 28, 30
50; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
51; CHECK-LE-NEXT:    clrldi 3, 3, 48
52; CHECK-LE-NEXT:    blr
53;
54; CHECK-BE-LABEL: test3:
55; CHECK-BE:       # %bb.0: # %entry
56; CHECK-BE-NEXT:    clrldi 3, 5, 32
57; CHECK-BE-NEXT:    rlwinm 3, 3, 1, 28, 30
58; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
59; CHECK-BE-NEXT:    clrldi 3, 3, 48
60; CHECK-BE-NEXT:    blr
61
62entry:
63  %vecext = extractelement <8 x i16> %a, i32 %index
64  ret i16 %vecext
65}
66
67define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
68; CHECK-LE-LABEL: test4:
69; CHECK-LE:       # %bb.0: # %entry
70; CHECK-LE-NEXT:    clrldi 3, 5, 32
71; CHECK-LE-NEXT:    rlwinm 3, 3, 1, 28, 30
72; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
73; CHECK-LE-NEXT:    extsh 3, 3
74; CHECK-LE-NEXT:    blr
75;
76; CHECK-BE-LABEL: test4:
77; CHECK-BE:       # %bb.0: # %entry
78; CHECK-BE-NEXT:    clrldi 3, 5, 32
79; CHECK-BE-NEXT:    rlwinm 3, 3, 1, 28, 30
80; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
81; CHECK-BE-NEXT:    extsh 3, 3
82; CHECK-BE-NEXT:    blr
83
84entry:
85  %vecext = extractelement <8 x i16> %a, i32 %index
86  ret i16 %vecext
87}
88
89define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
90; CHECK-LE-LABEL: test5:
91; CHECK-LE:       # %bb.0: # %entry
92; CHECK-LE-NEXT:    clrldi 3, 5, 32
93; CHECK-LE-NEXT:    rlwinm 3, 3, 2, 28, 29
94; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
95; CHECK-LE-NEXT:    blr
96;
97; CHECK-BE-LABEL: test5:
98; CHECK-BE:       # %bb.0: # %entry
99; CHECK-BE-NEXT:    clrldi 3, 5, 32
100; CHECK-BE-NEXT:    rlwinm 3, 3, 2, 28, 29
101; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
102; CHECK-BE-NEXT:    blr
103
104entry:
105  %vecext = extractelement <4 x i32> %a, i32 %index
106  ret i32 %vecext
107}
108
109define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
110; CHECK-LE-LABEL: test6:
111; CHECK-LE:       # %bb.0: # %entry
112; CHECK-LE-NEXT:    clrldi 3, 5, 32
113; CHECK-LE-NEXT:    rlwinm 3, 3, 2, 28, 29
114; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
115; CHECK-LE-NEXT:    extsw 3, 3
116; CHECK-LE-NEXT:    blr
117;
118; CHECK-BE-LABEL: test6:
119; CHECK-BE:       # %bb.0: # %entry
120; CHECK-BE-NEXT:    clrldi 3, 5, 32
121; CHECK-BE-NEXT:    rlwinm 3, 3, 2, 28, 29
122; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
123; CHECK-BE-NEXT:    extsw 3, 3
124; CHECK-BE-NEXT:    blr
125
126entry:
127  %vecext = extractelement <4 x i32> %a, i32 %index
128  ret i32 %vecext
129}
130
131; Test with immediate index
132define zeroext i8 @test7(<16 x i8> %a) {
133; CHECK-LE-LABEL: test7:
134; CHECK-LE:       # %bb.0: # %entry
135; CHECK-LE-NEXT:    li 3, 1
136; CHECK-LE-NEXT:    vextubrx 3, 3, 2
137; CHECK-LE-NEXT:    clrldi 3, 3, 56
138; CHECK-LE-NEXT:    blr
139;
140; CHECK-BE-LABEL: test7:
141; CHECK-BE:       # %bb.0: # %entry
142; CHECK-BE-NEXT:    li 3, 1
143; CHECK-BE-NEXT:    vextublx 3, 3, 2
144; CHECK-BE-NEXT:    clrldi 3, 3, 56
145; CHECK-BE-NEXT:    blr
146
147entry:
148  %vecext = extractelement <16 x i8> %a, i32 1
149  ret i8 %vecext
150}
151
152define zeroext i16 @test8(<8 x i16> %a) {
153; CHECK-LE-LABEL: test8:
154; CHECK-LE:       # %bb.0: # %entry
155; CHECK-LE-NEXT:    li 3, 2
156; CHECK-LE-NEXT:    vextuhrx 3, 3, 2
157; CHECK-LE-NEXT:    clrldi 3, 3, 48
158; CHECK-LE-NEXT:    blr
159;
160; CHECK-BE-LABEL: test8:
161; CHECK-BE:       # %bb.0: # %entry
162; CHECK-BE-NEXT:    li 3, 2
163; CHECK-BE-NEXT:    vextuhlx 3, 3, 2
164; CHECK-BE-NEXT:    clrldi 3, 3, 48
165; CHECK-BE-NEXT:    blr
166
167entry:
168  %vecext = extractelement <8 x i16> %a, i32 1
169  ret i16 %vecext
170}
171
172define zeroext i32 @test9(<4 x i32> %a) {
173; CHECK-LE-LABEL: test9:
174; CHECK-LE:       # %bb.0: # %entry
175; CHECK-LE-NEXT:    li 3, 12
176; CHECK-LE-NEXT:    vextuwrx 3, 3, 2
177; CHECK-LE-NEXT:    blr
178;
179; CHECK-BE-LABEL: test9:
180; CHECK-BE:       # %bb.0: # %entry
181; CHECK-BE-NEXT:    li 3, 12
182; CHECK-BE-NEXT:    vextuwlx 3, 3, 2
183; CHECK-BE-NEXT:    blr
184
185entry:
186  %vecext = extractelement <4 x i32> %a, i32 3
187  ret i32 %vecext
188}
189
190define double @test10(<4 x i32> %a, <4 x i32> %b) {
191; CHECK-LE-LABEL: test10:
192; CHECK-LE:       # %bb.0: # %entry
193; CHECK-LE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
194; CHECK-LE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
195; CHECK-LE-NEXT:    lxv 0, 0(3)
196; CHECK-LE-NEXT:    xxperm 35, 34, 0
197; CHECK-LE-NEXT:    vspltisw 2, 1
198; CHECK-LE-NEXT:    xvcvsxwdp 1, 34
199; CHECK-LE-NEXT:    xxswapd 0, 35
200; CHECK-LE-NEXT:    xsadddp 1, 0, 1
201; CHECK-LE-NEXT:    blr
202;
203; CHECK-BE-LABEL: test10:
204; CHECK-BE:       # %bb.0: # %entry
205; CHECK-BE-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
206; CHECK-BE-NEXT:    addi 3, 3, .LCPI9_0@toc@l
207; CHECK-BE-NEXT:    lxv 0, 0(3)
208; CHECK-BE-NEXT:    xxperm 34, 35, 0
209; CHECK-BE-NEXT:    vspltisw 3, 1
210; CHECK-BE-NEXT:    xvcvsxwdp 0, 35
211; CHECK-BE-NEXT:    xsadddp 1, 34, 0
212; CHECK-BE-NEXT:    blr
213entry:
214  %shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 2, i32 3, i32 7>
215  %cast = bitcast <4 x i32> %shuffle to <2 x double>
216  %extract = extractelement <2 x double> %cast, i32 0
217  %add = fadd double %extract, 1.0000
218  ret double %add
219}
220