1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s --check-prefix=CHECK-P8 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 6; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 7; RUN: FileCheck %s --check-prefix=CHECK-P9 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 9; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 10; RUN: FileCheck %s --check-prefix=CHECK-BE 11 12define i64 @test2elt(<2 x i64> %a) local_unnamed_addr #0 { 13; CHECK-P8-LABEL: test2elt: 14; CHECK-P8: # %bb.0: # %entry 15; CHECK-P8-NEXT: xxswapd vs0, v2 16; CHECK-P8-NEXT: xscvuxdsp f1, v2 17; CHECK-P8-NEXT: xscvuxdsp f0, f0 18; CHECK-P8-NEXT: xscvdpspn vs1, f1 19; CHECK-P8-NEXT: xscvdpspn vs0, f0 20; CHECK-P8-NEXT: xxmrghw vs0, vs1, vs0 21; CHECK-P8-NEXT: xxswapd vs0, vs0 22; CHECK-P8-NEXT: mffprd r3, f0 23; CHECK-P8-NEXT: blr 24; 25; CHECK-P9-LABEL: test2elt: 26; CHECK-P9: # %bb.0: # %entry 27; CHECK-P9-NEXT: xxswapd vs0, v2 28; CHECK-P9-NEXT: xscvuxdsp f1, v2 29; CHECK-P9-NEXT: xscvuxdsp f0, f0 30; CHECK-P9-NEXT: xscvdpspn vs1, f1 31; CHECK-P9-NEXT: xscvdpspn vs0, f0 32; CHECK-P9-NEXT: xxmrghw vs0, vs1, vs0 33; CHECK-P9-NEXT: mfvsrld r3, vs0 34; CHECK-P9-NEXT: blr 35; 36; CHECK-BE-LABEL: test2elt: 37; CHECK-BE: # %bb.0: # %entry 38; CHECK-BE-NEXT: xxswapd vs0, v2 39; CHECK-BE-NEXT: xscvuxdsp f1, v2 40; CHECK-BE-NEXT: xscvuxdsp f0, f0 41; CHECK-BE-NEXT: xscvdpspn v2, f1 42; CHECK-BE-NEXT: xscvdpspn v3, f0 43; CHECK-BE-NEXT: vmrgow v2, v2, v3 44; CHECK-BE-NEXT: mfvsrd r3, v2 45; CHECK-BE-NEXT: blr 46entry: 47 %0 = uitofp <2 x i64> %a to <2 x float> 48 %1 = bitcast <2 x float> %0 to i64 49 ret i64 %1 50} 51 52define <4 x float> @test4elt(ptr nocapture readonly) local_unnamed_addr #1 { 53; CHECK-P8-LABEL: test4elt: 54; CHECK-P8: # %bb.0: # %entry 55; CHECK-P8-NEXT: li r4, 16 56; CHECK-P8-NEXT: lxvd2x vs0, r3, r4 57; CHECK-P8-NEXT: xxswapd v2, vs0 58; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 59; CHECK-P8-NEXT: xxswapd v3, vs0 60; CHECK-P8-NEXT: xvcvuxdsp vs0, v2 61; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 62; CHECK-P8-NEXT: xvcvuxdsp vs0, v3 63; CHECK-P8-NEXT: xxsldwi v3, vs0, vs0, 3 64; CHECK-P8-NEXT: vpkudum v2, v2, v3 65; CHECK-P8-NEXT: blr 66; 67; CHECK-P9-LABEL: test4elt: 68; CHECK-P9: # %bb.0: # %entry 69; CHECK-P9-NEXT: lxv v3, 0(r3) 70; CHECK-P9-NEXT: lxv v2, 16(r3) 71; CHECK-P9-NEXT: xvcvuxdsp vs0, v3 72; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 73; CHECK-P9-NEXT: xvcvuxdsp vs0, v2 74; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 75; CHECK-P9-NEXT: vpkudum v2, v2, v3 76; CHECK-P9-NEXT: blr 77; 78; CHECK-BE-LABEL: test4elt: 79; CHECK-BE: # %bb.0: # %entry 80; CHECK-BE-NEXT: lxv v3, 16(r3) 81; CHECK-BE-NEXT: lxv v2, 0(r3) 82; CHECK-BE-NEXT: xvcvuxdsp vs0, v3 83; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3 84; CHECK-BE-NEXT: xvcvuxdsp vs0, v2 85; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 86; CHECK-BE-NEXT: vpkudum v2, v2, v3 87; CHECK-BE-NEXT: blr 88entry: 89 %a = load <4 x i64>, ptr %0, align 32 90 %1 = uitofp <4 x i64> %a to <4 x float> 91 ret <4 x float> %1 92} 93 94define void @test8elt(ptr noalias nocapture sret(<8 x float>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 { 95; CHECK-P8-LABEL: test8elt: 96; CHECK-P8: # %bb.0: # %entry 97; CHECK-P8-NEXT: li r6, 48 98; CHECK-P8-NEXT: li r5, 16 99; CHECK-P8-NEXT: lxvd2x vs0, r4, r6 100; CHECK-P8-NEXT: li r6, 32 101; CHECK-P8-NEXT: lxvd2x vs1, r4, r6 102; CHECK-P8-NEXT: xxswapd v2, vs0 103; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 104; CHECK-P8-NEXT: xxswapd v3, vs1 105; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 106; CHECK-P8-NEXT: xxswapd v4, vs0 107; CHECK-P8-NEXT: xvcvuxdsp vs0, v3 108; CHECK-P8-NEXT: xxswapd v5, vs1 109; CHECK-P8-NEXT: xvcvuxdsp vs1, v2 110; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 111; CHECK-P8-NEXT: xvcvuxdsp vs0, v4 112; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 113; CHECK-P8-NEXT: vpkudum v2, v3, v2 114; CHECK-P8-NEXT: xxsldwi v4, vs0, vs0, 3 115; CHECK-P8-NEXT: xvcvuxdsp vs0, v5 116; CHECK-P8-NEXT: xxsldwi v5, vs0, vs0, 3 117; CHECK-P8-NEXT: xxswapd vs0, v2 118; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 119; CHECK-P8-NEXT: vpkudum v3, v4, v5 120; CHECK-P8-NEXT: xxswapd vs1, v3 121; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 122; CHECK-P8-NEXT: blr 123; 124; CHECK-P9-LABEL: test8elt: 125; CHECK-P9: # %bb.0: # %entry 126; CHECK-P9-NEXT: lxv v5, 0(r4) 127; CHECK-P9-NEXT: lxv v4, 16(r4) 128; CHECK-P9-NEXT: lxv v3, 32(r4) 129; CHECK-P9-NEXT: lxv v2, 48(r4) 130; CHECK-P9-NEXT: xvcvuxdsp vs0, v5 131; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3 132; CHECK-P9-NEXT: xvcvuxdsp vs0, v4 133; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 134; CHECK-P9-NEXT: xvcvuxdsp vs0, v3 135; CHECK-P9-NEXT: vpkudum v3, v4, v5 136; CHECK-P9-NEXT: stxv v3, 0(r3) 137; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 138; CHECK-P9-NEXT: xvcvuxdsp vs0, v2 139; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 140; CHECK-P9-NEXT: vpkudum v2, v2, v4 141; CHECK-P9-NEXT: stxv v2, 16(r3) 142; CHECK-P9-NEXT: blr 143; 144; CHECK-BE-LABEL: test8elt: 145; CHECK-BE: # %bb.0: # %entry 146; CHECK-BE-NEXT: lxv v5, 16(r4) 147; CHECK-BE-NEXT: lxv v4, 0(r4) 148; CHECK-BE-NEXT: lxv v3, 48(r4) 149; CHECK-BE-NEXT: lxv v2, 32(r4) 150; CHECK-BE-NEXT: xvcvuxdsp vs0, v5 151; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3 152; CHECK-BE-NEXT: xvcvuxdsp vs0, v4 153; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 154; CHECK-BE-NEXT: xvcvuxdsp vs0, v3 155; CHECK-BE-NEXT: vpkudum v3, v4, v5 156; CHECK-BE-NEXT: stxv v3, 0(r3) 157; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 158; CHECK-BE-NEXT: xvcvuxdsp vs0, v2 159; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 160; CHECK-BE-NEXT: vpkudum v2, v2, v4 161; CHECK-BE-NEXT: stxv v2, 16(r3) 162; CHECK-BE-NEXT: blr 163entry: 164 %a = load <8 x i64>, ptr %0, align 64 165 %1 = uitofp <8 x i64> %a to <8 x float> 166 store <8 x float> %1, ptr %agg.result, align 32 167 ret void 168} 169 170define void @test16elt(ptr noalias nocapture sret(<16 x float>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 { 171; CHECK-P8-LABEL: test16elt: 172; CHECK-P8: # %bb.0: # %entry 173; CHECK-P8-NEXT: li r7, 96 174; CHECK-P8-NEXT: li r6, 112 175; CHECK-P8-NEXT: li r5, 16 176; CHECK-P8-NEXT: lxvd2x vs1, r4, r7 177; CHECK-P8-NEXT: li r7, 64 178; CHECK-P8-NEXT: lxvd2x vs0, r4, r6 179; CHECK-P8-NEXT: li r6, 80 180; CHECK-P8-NEXT: lxvd2x vs3, r4, r7 181; CHECK-P8-NEXT: li r7, 32 182; CHECK-P8-NEXT: lxvd2x vs2, r4, r6 183; CHECK-P8-NEXT: li r6, 48 184; CHECK-P8-NEXT: lxvd2x vs5, r4, r7 185; CHECK-P8-NEXT: lxvd2x vs4, r4, r6 186; CHECK-P8-NEXT: xxswapd v4, vs0 187; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 188; CHECK-P8-NEXT: xxswapd v5, vs1 189; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 190; CHECK-P8-NEXT: xxswapd v0, vs2 191; CHECK-P8-NEXT: xxswapd v1, vs3 192; CHECK-P8-NEXT: xvcvuxdsp vs2, v1 193; CHECK-P8-NEXT: xvcvuxdsp vs3, v0 194; CHECK-P8-NEXT: xxswapd v3, vs5 195; CHECK-P8-NEXT: xxswapd v2, vs4 196; CHECK-P8-NEXT: xvcvuxdsp vs4, v5 197; CHECK-P8-NEXT: xvcvuxdsp vs5, v4 198; CHECK-P8-NEXT: xxswapd v6, vs0 199; CHECK-P8-NEXT: xxswapd v7, vs1 200; CHECK-P8-NEXT: xvcvuxdsp vs0, v3 201; CHECK-P8-NEXT: xvcvuxdsp vs1, v2 202; CHECK-P8-NEXT: xxsldwi v4, vs2, vs2, 3 203; CHECK-P8-NEXT: xxsldwi v5, vs3, vs3, 3 204; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3 205; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3 206; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 207; CHECK-P8-NEXT: xvcvuxdsp vs0, v6 208; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 209; CHECK-P8-NEXT: vpkudum v2, v3, v2 210; CHECK-P8-NEXT: vpkudum v3, v5, v4 211; CHECK-P8-NEXT: vpkudum v4, v1, v0 212; CHECK-P8-NEXT: xxswapd vs1, v3 213; CHECK-P8-NEXT: xxswapd vs2, v2 214; CHECK-P8-NEXT: stxvd2x vs1, r3, r7 215; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 216; CHECK-P8-NEXT: xxsldwi v6, vs0, vs0, 3 217; CHECK-P8-NEXT: xvcvuxdsp vs0, v7 218; CHECK-P8-NEXT: xxsldwi v7, vs0, vs0, 3 219; CHECK-P8-NEXT: xxswapd vs0, v4 220; CHECK-P8-NEXT: stxvd2x vs0, r3, r6 221; CHECK-P8-NEXT: vpkudum v5, v6, v7 222; CHECK-P8-NEXT: xxswapd vs3, v5 223; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 224; CHECK-P8-NEXT: blr 225; 226; CHECK-P9-LABEL: test16elt: 227; CHECK-P9: # %bb.0: # %entry 228; CHECK-P9-NEXT: lxv v7, 0(r4) 229; CHECK-P9-NEXT: lxv v6, 16(r4) 230; CHECK-P9-NEXT: lxv v1, 32(r4) 231; CHECK-P9-NEXT: lxv v0, 48(r4) 232; CHECK-P9-NEXT: xvcvuxdsp vs0, v7 233; CHECK-P9-NEXT: lxv v5, 64(r4) 234; CHECK-P9-NEXT: lxv v4, 80(r4) 235; CHECK-P9-NEXT: lxv v3, 96(r4) 236; CHECK-P9-NEXT: lxv v2, 112(r4) 237; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3 238; CHECK-P9-NEXT: xvcvuxdsp vs0, v6 239; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3 240; CHECK-P9-NEXT: xvcvuxdsp vs0, v1 241; CHECK-P9-NEXT: vpkudum v1, v6, v7 242; CHECK-P9-NEXT: stxv v1, 0(r3) 243; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3 244; CHECK-P9-NEXT: xvcvuxdsp vs0, v0 245; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3 246; CHECK-P9-NEXT: xvcvuxdsp vs0, v5 247; CHECK-P9-NEXT: vpkudum v0, v0, v6 248; CHECK-P9-NEXT: stxv v0, 16(r3) 249; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3 250; CHECK-P9-NEXT: xvcvuxdsp vs0, v4 251; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 252; CHECK-P9-NEXT: xvcvuxdsp vs0, v3 253; CHECK-P9-NEXT: vpkudum v4, v4, v5 254; CHECK-P9-NEXT: stxv v4, 32(r3) 255; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 256; CHECK-P9-NEXT: xvcvuxdsp vs0, v2 257; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 258; CHECK-P9-NEXT: vpkudum v2, v2, v3 259; CHECK-P9-NEXT: stxv v2, 48(r3) 260; CHECK-P9-NEXT: blr 261; 262; CHECK-BE-LABEL: test16elt: 263; CHECK-BE: # %bb.0: # %entry 264; CHECK-BE-NEXT: lxv v7, 16(r4) 265; CHECK-BE-NEXT: lxv v6, 0(r4) 266; CHECK-BE-NEXT: lxv v1, 48(r4) 267; CHECK-BE-NEXT: lxv v0, 32(r4) 268; CHECK-BE-NEXT: xvcvuxdsp vs0, v7 269; CHECK-BE-NEXT: lxv v5, 80(r4) 270; CHECK-BE-NEXT: lxv v4, 64(r4) 271; CHECK-BE-NEXT: lxv v3, 112(r4) 272; CHECK-BE-NEXT: lxv v2, 96(r4) 273; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3 274; CHECK-BE-NEXT: xvcvuxdsp vs0, v6 275; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3 276; CHECK-BE-NEXT: xvcvuxdsp vs0, v1 277; CHECK-BE-NEXT: vpkudum v1, v6, v7 278; CHECK-BE-NEXT: stxv v1, 0(r3) 279; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3 280; CHECK-BE-NEXT: xvcvuxdsp vs0, v0 281; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3 282; CHECK-BE-NEXT: xvcvuxdsp vs0, v5 283; CHECK-BE-NEXT: vpkudum v0, v0, v6 284; CHECK-BE-NEXT: stxv v0, 16(r3) 285; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3 286; CHECK-BE-NEXT: xvcvuxdsp vs0, v4 287; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 288; CHECK-BE-NEXT: xvcvuxdsp vs0, v3 289; CHECK-BE-NEXT: vpkudum v4, v4, v5 290; CHECK-BE-NEXT: stxv v4, 32(r3) 291; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3 292; CHECK-BE-NEXT: xvcvuxdsp vs0, v2 293; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 294; CHECK-BE-NEXT: vpkudum v2, v2, v3 295; CHECK-BE-NEXT: stxv v2, 48(r3) 296; CHECK-BE-NEXT: blr 297entry: 298 %a = load <16 x i64>, ptr %0, align 128 299 %1 = uitofp <16 x i64> %a to <16 x float> 300 store <16 x float> %1, ptr %agg.result, align 64 301 ret void 302} 303 304define i64 @test2elt_signed(<2 x i64> %a) local_unnamed_addr #0 { 305; CHECK-P8-LABEL: test2elt_signed: 306; CHECK-P8: # %bb.0: # %entry 307; CHECK-P8-NEXT: xxswapd vs0, v2 308; CHECK-P8-NEXT: xscvsxdsp f1, v2 309; CHECK-P8-NEXT: xscvsxdsp f0, f0 310; CHECK-P8-NEXT: xscvdpspn vs1, f1 311; CHECK-P8-NEXT: xscvdpspn vs0, f0 312; CHECK-P8-NEXT: xxmrghw vs0, vs1, vs0 313; CHECK-P8-NEXT: xxswapd vs0, vs0 314; CHECK-P8-NEXT: mffprd r3, f0 315; CHECK-P8-NEXT: blr 316; 317; CHECK-P9-LABEL: test2elt_signed: 318; CHECK-P9: # %bb.0: # %entry 319; CHECK-P9-NEXT: xxswapd vs0, v2 320; CHECK-P9-NEXT: xscvsxdsp f1, v2 321; CHECK-P9-NEXT: xscvsxdsp f0, f0 322; CHECK-P9-NEXT: xscvdpspn vs1, f1 323; CHECK-P9-NEXT: xscvdpspn vs0, f0 324; CHECK-P9-NEXT: xxmrghw vs0, vs1, vs0 325; CHECK-P9-NEXT: mfvsrld r3, vs0 326; CHECK-P9-NEXT: blr 327; 328; CHECK-BE-LABEL: test2elt_signed: 329; CHECK-BE: # %bb.0: # %entry 330; CHECK-BE-NEXT: xxswapd vs0, v2 331; CHECK-BE-NEXT: xscvsxdsp f1, v2 332; CHECK-BE-NEXT: xscvsxdsp f0, f0 333; CHECK-BE-NEXT: xscvdpspn v2, f1 334; CHECK-BE-NEXT: xscvdpspn v3, f0 335; CHECK-BE-NEXT: vmrgow v2, v2, v3 336; CHECK-BE-NEXT: mfvsrd r3, v2 337; CHECK-BE-NEXT: blr 338entry: 339 %0 = sitofp <2 x i64> %a to <2 x float> 340 %1 = bitcast <2 x float> %0 to i64 341 ret i64 %1 342} 343 344define <4 x float> @test4elt_signed(ptr nocapture readonly) local_unnamed_addr #1 { 345; CHECK-P8-LABEL: test4elt_signed: 346; CHECK-P8: # %bb.0: # %entry 347; CHECK-P8-NEXT: li r4, 16 348; CHECK-P8-NEXT: lxvd2x vs0, r3, r4 349; CHECK-P8-NEXT: xxswapd v2, vs0 350; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 351; CHECK-P8-NEXT: xxswapd v3, vs0 352; CHECK-P8-NEXT: xvcvsxdsp vs0, v2 353; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 354; CHECK-P8-NEXT: xvcvsxdsp vs0, v3 355; CHECK-P8-NEXT: xxsldwi v3, vs0, vs0, 3 356; CHECK-P8-NEXT: vpkudum v2, v2, v3 357; CHECK-P8-NEXT: blr 358; 359; CHECK-P9-LABEL: test4elt_signed: 360; CHECK-P9: # %bb.0: # %entry 361; CHECK-P9-NEXT: lxv v3, 0(r3) 362; CHECK-P9-NEXT: lxv v2, 16(r3) 363; CHECK-P9-NEXT: xvcvsxdsp vs0, v3 364; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 365; CHECK-P9-NEXT: xvcvsxdsp vs0, v2 366; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 367; CHECK-P9-NEXT: vpkudum v2, v2, v3 368; CHECK-P9-NEXT: blr 369; 370; CHECK-BE-LABEL: test4elt_signed: 371; CHECK-BE: # %bb.0: # %entry 372; CHECK-BE-NEXT: lxv v3, 16(r3) 373; CHECK-BE-NEXT: lxv v2, 0(r3) 374; CHECK-BE-NEXT: xvcvsxdsp vs0, v3 375; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3 376; CHECK-BE-NEXT: xvcvsxdsp vs0, v2 377; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 378; CHECK-BE-NEXT: vpkudum v2, v2, v3 379; CHECK-BE-NEXT: blr 380entry: 381 %a = load <4 x i64>, ptr %0, align 32 382 %1 = sitofp <4 x i64> %a to <4 x float> 383 ret <4 x float> %1 384} 385 386define void @test8elt_signed(ptr noalias nocapture sret(<8 x float>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 { 387; CHECK-P8-LABEL: test8elt_signed: 388; CHECK-P8: # %bb.0: # %entry 389; CHECK-P8-NEXT: li r6, 48 390; CHECK-P8-NEXT: li r5, 16 391; CHECK-P8-NEXT: lxvd2x vs0, r4, r6 392; CHECK-P8-NEXT: li r6, 32 393; CHECK-P8-NEXT: lxvd2x vs1, r4, r6 394; CHECK-P8-NEXT: xxswapd v2, vs0 395; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 396; CHECK-P8-NEXT: xxswapd v3, vs1 397; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 398; CHECK-P8-NEXT: xxswapd v4, vs0 399; CHECK-P8-NEXT: xvcvsxdsp vs0, v3 400; CHECK-P8-NEXT: xxswapd v5, vs1 401; CHECK-P8-NEXT: xvcvsxdsp vs1, v2 402; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 403; CHECK-P8-NEXT: xvcvsxdsp vs0, v4 404; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 405; CHECK-P8-NEXT: vpkudum v2, v3, v2 406; CHECK-P8-NEXT: xxsldwi v4, vs0, vs0, 3 407; CHECK-P8-NEXT: xvcvsxdsp vs0, v5 408; CHECK-P8-NEXT: xxsldwi v5, vs0, vs0, 3 409; CHECK-P8-NEXT: xxswapd vs0, v2 410; CHECK-P8-NEXT: stxvd2x vs0, r3, r5 411; CHECK-P8-NEXT: vpkudum v3, v4, v5 412; CHECK-P8-NEXT: xxswapd vs1, v3 413; CHECK-P8-NEXT: stxvd2x vs1, 0, r3 414; CHECK-P8-NEXT: blr 415; 416; CHECK-P9-LABEL: test8elt_signed: 417; CHECK-P9: # %bb.0: # %entry 418; CHECK-P9-NEXT: lxv v5, 0(r4) 419; CHECK-P9-NEXT: lxv v4, 16(r4) 420; CHECK-P9-NEXT: lxv v3, 32(r4) 421; CHECK-P9-NEXT: lxv v2, 48(r4) 422; CHECK-P9-NEXT: xvcvsxdsp vs0, v5 423; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3 424; CHECK-P9-NEXT: xvcvsxdsp vs0, v4 425; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 426; CHECK-P9-NEXT: xvcvsxdsp vs0, v3 427; CHECK-P9-NEXT: vpkudum v3, v4, v5 428; CHECK-P9-NEXT: stxv v3, 0(r3) 429; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 430; CHECK-P9-NEXT: xvcvsxdsp vs0, v2 431; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 432; CHECK-P9-NEXT: vpkudum v2, v2, v4 433; CHECK-P9-NEXT: stxv v2, 16(r3) 434; CHECK-P9-NEXT: blr 435; 436; CHECK-BE-LABEL: test8elt_signed: 437; CHECK-BE: # %bb.0: # %entry 438; CHECK-BE-NEXT: lxv v5, 16(r4) 439; CHECK-BE-NEXT: lxv v4, 0(r4) 440; CHECK-BE-NEXT: lxv v3, 48(r4) 441; CHECK-BE-NEXT: lxv v2, 32(r4) 442; CHECK-BE-NEXT: xvcvsxdsp vs0, v5 443; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3 444; CHECK-BE-NEXT: xvcvsxdsp vs0, v4 445; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 446; CHECK-BE-NEXT: xvcvsxdsp vs0, v3 447; CHECK-BE-NEXT: vpkudum v3, v4, v5 448; CHECK-BE-NEXT: stxv v3, 0(r3) 449; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 450; CHECK-BE-NEXT: xvcvsxdsp vs0, v2 451; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 452; CHECK-BE-NEXT: vpkudum v2, v2, v4 453; CHECK-BE-NEXT: stxv v2, 16(r3) 454; CHECK-BE-NEXT: blr 455entry: 456 %a = load <8 x i64>, ptr %0, align 64 457 %1 = sitofp <8 x i64> %a to <8 x float> 458 store <8 x float> %1, ptr %agg.result, align 32 459 ret void 460} 461 462define void @test16elt_signed(ptr noalias nocapture sret(<16 x float>) %agg.result, ptr nocapture readonly) local_unnamed_addr #2 { 463; CHECK-P8-LABEL: test16elt_signed: 464; CHECK-P8: # %bb.0: # %entry 465; CHECK-P8-NEXT: li r7, 96 466; CHECK-P8-NEXT: li r6, 112 467; CHECK-P8-NEXT: li r5, 16 468; CHECK-P8-NEXT: lxvd2x vs1, r4, r7 469; CHECK-P8-NEXT: li r7, 64 470; CHECK-P8-NEXT: lxvd2x vs0, r4, r6 471; CHECK-P8-NEXT: li r6, 80 472; CHECK-P8-NEXT: lxvd2x vs3, r4, r7 473; CHECK-P8-NEXT: li r7, 32 474; CHECK-P8-NEXT: lxvd2x vs2, r4, r6 475; CHECK-P8-NEXT: li r6, 48 476; CHECK-P8-NEXT: lxvd2x vs5, r4, r7 477; CHECK-P8-NEXT: lxvd2x vs4, r4, r6 478; CHECK-P8-NEXT: xxswapd v4, vs0 479; CHECK-P8-NEXT: lxvd2x vs0, r4, r5 480; CHECK-P8-NEXT: xxswapd v5, vs1 481; CHECK-P8-NEXT: lxvd2x vs1, 0, r4 482; CHECK-P8-NEXT: xxswapd v0, vs2 483; CHECK-P8-NEXT: xxswapd v1, vs3 484; CHECK-P8-NEXT: xvcvsxdsp vs2, v1 485; CHECK-P8-NEXT: xvcvsxdsp vs3, v0 486; CHECK-P8-NEXT: xxswapd v3, vs5 487; CHECK-P8-NEXT: xxswapd v2, vs4 488; CHECK-P8-NEXT: xvcvsxdsp vs4, v5 489; CHECK-P8-NEXT: xvcvsxdsp vs5, v4 490; CHECK-P8-NEXT: xxswapd v6, vs0 491; CHECK-P8-NEXT: xxswapd v7, vs1 492; CHECK-P8-NEXT: xvcvsxdsp vs0, v3 493; CHECK-P8-NEXT: xvcvsxdsp vs1, v2 494; CHECK-P8-NEXT: xxsldwi v4, vs2, vs2, 3 495; CHECK-P8-NEXT: xxsldwi v5, vs3, vs3, 3 496; CHECK-P8-NEXT: xxsldwi v0, vs4, vs4, 3 497; CHECK-P8-NEXT: xxsldwi v1, vs5, vs5, 3 498; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 3 499; CHECK-P8-NEXT: xvcvsxdsp vs0, v6 500; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 3 501; CHECK-P8-NEXT: vpkudum v2, v3, v2 502; CHECK-P8-NEXT: vpkudum v3, v5, v4 503; CHECK-P8-NEXT: vpkudum v4, v1, v0 504; CHECK-P8-NEXT: xxswapd vs1, v3 505; CHECK-P8-NEXT: xxswapd vs2, v2 506; CHECK-P8-NEXT: stxvd2x vs1, r3, r7 507; CHECK-P8-NEXT: stxvd2x vs2, r3, r5 508; CHECK-P8-NEXT: xxsldwi v6, vs0, vs0, 3 509; CHECK-P8-NEXT: xvcvsxdsp vs0, v7 510; CHECK-P8-NEXT: xxsldwi v7, vs0, vs0, 3 511; CHECK-P8-NEXT: xxswapd vs0, v4 512; CHECK-P8-NEXT: stxvd2x vs0, r3, r6 513; CHECK-P8-NEXT: vpkudum v5, v6, v7 514; CHECK-P8-NEXT: xxswapd vs3, v5 515; CHECK-P8-NEXT: stxvd2x vs3, 0, r3 516; CHECK-P8-NEXT: blr 517; 518; CHECK-P9-LABEL: test16elt_signed: 519; CHECK-P9: # %bb.0: # %entry 520; CHECK-P9-NEXT: lxv v7, 0(r4) 521; CHECK-P9-NEXT: lxv v6, 16(r4) 522; CHECK-P9-NEXT: lxv v1, 32(r4) 523; CHECK-P9-NEXT: lxv v0, 48(r4) 524; CHECK-P9-NEXT: xvcvsxdsp vs0, v7 525; CHECK-P9-NEXT: lxv v5, 64(r4) 526; CHECK-P9-NEXT: lxv v4, 80(r4) 527; CHECK-P9-NEXT: lxv v3, 96(r4) 528; CHECK-P9-NEXT: lxv v2, 112(r4) 529; CHECK-P9-NEXT: xxsldwi v7, vs0, vs0, 3 530; CHECK-P9-NEXT: xvcvsxdsp vs0, v6 531; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3 532; CHECK-P9-NEXT: xvcvsxdsp vs0, v1 533; CHECK-P9-NEXT: vpkudum v1, v6, v7 534; CHECK-P9-NEXT: stxv v1, 0(r3) 535; CHECK-P9-NEXT: xxsldwi v6, vs0, vs0, 3 536; CHECK-P9-NEXT: xvcvsxdsp vs0, v0 537; CHECK-P9-NEXT: xxsldwi v0, vs0, vs0, 3 538; CHECK-P9-NEXT: xvcvsxdsp vs0, v5 539; CHECK-P9-NEXT: vpkudum v0, v0, v6 540; CHECK-P9-NEXT: stxv v0, 16(r3) 541; CHECK-P9-NEXT: xxsldwi v5, vs0, vs0, 3 542; CHECK-P9-NEXT: xvcvsxdsp vs0, v4 543; CHECK-P9-NEXT: xxsldwi v4, vs0, vs0, 3 544; CHECK-P9-NEXT: xvcvsxdsp vs0, v3 545; CHECK-P9-NEXT: vpkudum v4, v4, v5 546; CHECK-P9-NEXT: stxv v4, 32(r3) 547; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 3 548; CHECK-P9-NEXT: xvcvsxdsp vs0, v2 549; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 3 550; CHECK-P9-NEXT: vpkudum v2, v2, v3 551; CHECK-P9-NEXT: stxv v2, 48(r3) 552; CHECK-P9-NEXT: blr 553; 554; CHECK-BE-LABEL: test16elt_signed: 555; CHECK-BE: # %bb.0: # %entry 556; CHECK-BE-NEXT: lxv v7, 16(r4) 557; CHECK-BE-NEXT: lxv v6, 0(r4) 558; CHECK-BE-NEXT: lxv v1, 48(r4) 559; CHECK-BE-NEXT: lxv v0, 32(r4) 560; CHECK-BE-NEXT: xvcvsxdsp vs0, v7 561; CHECK-BE-NEXT: lxv v5, 80(r4) 562; CHECK-BE-NEXT: lxv v4, 64(r4) 563; CHECK-BE-NEXT: lxv v3, 112(r4) 564; CHECK-BE-NEXT: lxv v2, 96(r4) 565; CHECK-BE-NEXT: xxsldwi v7, vs0, vs0, 3 566; CHECK-BE-NEXT: xvcvsxdsp vs0, v6 567; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3 568; CHECK-BE-NEXT: xvcvsxdsp vs0, v1 569; CHECK-BE-NEXT: vpkudum v1, v6, v7 570; CHECK-BE-NEXT: stxv v1, 0(r3) 571; CHECK-BE-NEXT: xxsldwi v6, vs0, vs0, 3 572; CHECK-BE-NEXT: xvcvsxdsp vs0, v0 573; CHECK-BE-NEXT: xxsldwi v0, vs0, vs0, 3 574; CHECK-BE-NEXT: xvcvsxdsp vs0, v5 575; CHECK-BE-NEXT: vpkudum v0, v0, v6 576; CHECK-BE-NEXT: stxv v0, 16(r3) 577; CHECK-BE-NEXT: xxsldwi v5, vs0, vs0, 3 578; CHECK-BE-NEXT: xvcvsxdsp vs0, v4 579; CHECK-BE-NEXT: xxsldwi v4, vs0, vs0, 3 580; CHECK-BE-NEXT: xvcvsxdsp vs0, v3 581; CHECK-BE-NEXT: vpkudum v4, v4, v5 582; CHECK-BE-NEXT: stxv v4, 32(r3) 583; CHECK-BE-NEXT: xxsldwi v3, vs0, vs0, 3 584; CHECK-BE-NEXT: xvcvsxdsp vs0, v2 585; CHECK-BE-NEXT: xxsldwi v2, vs0, vs0, 3 586; CHECK-BE-NEXT: vpkudum v2, v2, v3 587; CHECK-BE-NEXT: stxv v2, 48(r3) 588; CHECK-BE-NEXT: blr 589entry: 590 %a = load <16 x i64>, ptr %0, align 128 591 %1 = sitofp <16 x i64> %a to <16 x float> 592 store <16 x float> %1, ptr %agg.result, align 64 593 ret void 594} 595