1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,BE 3; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -vec-extabi < %s | FileCheck %s --check-prefixes=CHECK,BE 4; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,LE 5 6define void @test1(ptr %P1, ptr %P2, ptr %P3) nounwind { 7; BE-LABEL: test1: 8; BE: # %bb.0: 9; BE-NEXT: lxvw4x 0, 0, 3 10; BE-NEXT: vspltisb 2, -1 11; BE-NEXT: vslw 2, 2, 2 12; BE-NEXT: xxland 0, 0, 34 13; BE-NEXT: stxvw4x 0, 0, 3 14; BE-NEXT: lxvw4x 0, 0, 4 15; BE-NEXT: xxlandc 0, 0, 34 16; BE-NEXT: stxvw4x 0, 0, 4 17; BE-NEXT: lxvw4x 0, 0, 5 18; BE-NEXT: xvabssp 0, 0 19; BE-NEXT: stxvw4x 0, 0, 5 20; BE-NEXT: blr 21; 22; LE-LABEL: test1: 23; LE: # %bb.0: 24; LE-NEXT: lxvd2x 0, 0, 3 25; LE-NEXT: xxswapd 34, 0 26; LE-NEXT: vspltisb 3, -1 27; LE-NEXT: vslw 3, 3, 3 28; LE-NEXT: xxland 0, 34, 35 29; LE-NEXT: xxswapd 0, 0 30; LE-NEXT: stxvd2x 0, 0, 3 31; LE-NEXT: lxvd2x 0, 0, 4 32; LE-NEXT: xxswapd 34, 0 33; LE-NEXT: xxlandc 0, 34, 35 34; LE-NEXT: xxswapd 0, 0 35; LE-NEXT: stxvd2x 0, 0, 4 36; LE-NEXT: lxvd2x 0, 0, 5 37; LE-NEXT: xxswapd 34, 0 38; LE-NEXT: xvabssp 0, 34 39; LE-NEXT: xxswapd 0, 0 40; LE-NEXT: stxvd2x 0, 0, 5 41; LE-NEXT: blr 42 %tmp = load <4 x i32>, ptr %P1 ; <<4 x i32>> [#uses=1] 43 %tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 > ; <<4 x i32>> [#uses=1] 44 store <4 x i32> %tmp4, ptr %P1 45 %tmp7 = load <4 x i32>, ptr %P2 ; <<4 x i32>> [#uses=1] 46 %tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] 47 store <4 x i32> %tmp9, ptr %P2 48 %tmp.upgrd.1 = load <4 x float>, ptr %P3 ; <<4 x float>> [#uses=1] 49 %tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32> ; <<4 x i32>> [#uses=1] 50 %tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 > ; <<4 x i32>> [#uses=1] 51 %tmp13 = bitcast <4 x i32> %tmp12 to <4 x float> ; <<4 x float>> [#uses=1] 52 store <4 x float> %tmp13, ptr %P3 53 ret void 54 55} 56 57define <4 x i32> @test_30() nounwind { 58; CHECK-LABEL: test_30: 59; CHECK: # %bb.0: 60; CHECK-NEXT: vspltisw 2, 15 61; CHECK-NEXT: vadduwm 2, 2, 2 62; CHECK-NEXT: blr 63 ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 > 64} 65 66define <4 x i32> @test_29() nounwind { 67; CHECK-LABEL: test_29: 68; CHECK: # %bb.0: 69; CHECK-NEXT: vspltisw 3, -16 70; CHECK-NEXT: vspltisw 2, 13 71; CHECK-NEXT: vsubuwm 2, 2, 3 72; CHECK-NEXT: blr 73 ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 > 74} 75 76define <8 x i16> @test_n30() nounwind { 77; CHECK-LABEL: test_n30: 78; CHECK: # %bb.0: 79; CHECK-NEXT: vspltish 2, -15 80; CHECK-NEXT: vadduhm 2, 2, 2 81; CHECK-NEXT: blr 82 ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 > 83} 84 85define <16 x i8> @test_n104() nounwind { 86; CHECK-LABEL: test_n104: 87; CHECK: # %bb.0: 88; CHECK-NEXT: vspltisb 2, -13 89; CHECK-NEXT: vslb 2, 2, 2 90; CHECK-NEXT: blr 91 ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 > 92} 93 94define <4 x i32> @test_vsldoi() nounwind { 95; CHECK-LABEL: test_vsldoi: 96; CHECK: # %bb.0: 97; CHECK-NEXT: vspltisw 2, 2 98; CHECK-NEXT: vsldoi 2, 2, 2, 1 99; CHECK-NEXT: blr 100 ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 > 101} 102 103define <8 x i16> @test_vsldoi_65023() nounwind { 104; CHECK-LABEL: test_vsldoi_65023: 105; CHECK: # %bb.0: 106; CHECK-NEXT: vspltish 2, -3 107; CHECK-NEXT: vsldoi 2, 2, 2, 1 108; CHECK-NEXT: blr 109 ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 > 110} 111 112define <4 x i32> @test_vsldoi_x16() nounwind { 113; CHECK-LABEL: test_vsldoi_x16: 114; CHECK: # %bb.0: 115; CHECK-NEXT: vspltisw 2, -3 116; CHECK-NEXT: vsldoi 2, 2, 2, 2 117; CHECK-NEXT: blr 118 ret <4 x i32> <i32 -131073, i32 -131073, i32 -131073, i32 -131073> 119} 120 121define <4 x i32> @test_vsldoi_x24() nounwind { 122; CHECK-LABEL: test_vsldoi_x24: 123; CHECK: # %bb.0: 124; CHECK-NEXT: vspltisw 2, -3 125; CHECK-NEXT: vsldoi 2, 2, 2, 3 126; CHECK-NEXT: blr 127 ret <4 x i32> <i32 -33554433, i32 -33554433, i32 -33554433, i32 -33554433> 128} 129 130define <4 x i32> @test_rol() nounwind { 131; CHECK-LABEL: test_rol: 132; CHECK: # %bb.0: 133; CHECK-NEXT: vspltisw 2, -12 134; CHECK-NEXT: vrlw 2, 2, 2 135; CHECK-NEXT: blr 136 ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 > 137} 138