xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec_cmpq.ll (revision 2e7117f847708d2fd1ff2d2961c3439470532b80) 
1; Test the quadword comparison instructions that were added in POWER10.
2;
3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
4; RUN:     -mcpu=pwr10 < %s | FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:     -mcpu=pwr10 -mattr=-vsx < %s | FileCheck %s
7; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
8; RUN:     -mcpu=pwr10 < %s | FileCheck %s
9define <1 x i128> @v1si128_cmp(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
10       %cmp = icmp eq <1 x i128> %x, %y
11       %result = sext <1 x i1> %cmp to <1 x i128>
12       ret <1 x i128> %result
13; CHECK-LABEL: v1si128_cmp:
14; CHECK: vcmpequq 2, 2, 3
15}
16
17define <2 x i128> @v2si128_cmp(<2 x i128> %x, <2 x i128> %y) nounwind readnone {
18       %cmp = icmp eq <2 x i128> %x, %y
19       %result = sext <2 x i1> %cmp to <2 x i128>
20       ret <2 x i128> %result
21; CHECK-LABEL: v2si128_cmp
22; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
23; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
24; CHECK: blr
25}
26
27define <4 x i128> @v4si128_cmp(<4 x i128> %x, <4 x i128> %y) nounwind readnone {
28       %cmp = icmp eq <4 x i128> %x, %y
29       %result = sext <4 x i1> %cmp to <4 x i128>
30       ret <4 x i128> %result
31; CHECK-LABEL: v4si128_cmp
32; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
33; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
34; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
35; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
36; CHECK: blr
37}
38
39define <8 x i128> @v8si128_cmp(<8 x i128> %x, <8 x i128> %y) nounwind readnone {
40       %cmp = icmp eq <8 x i128> %x, %y
41       %result = sext <8 x i1> %cmp to <8 x i128>
42       ret <8 x i128> %result
43; CHECK-LABEL: v8si128_cmp
44; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
45; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
46; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
47; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
48; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
49; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
50; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
51; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
52; CHECK: blr
53}
54
55define <16 x i128> @v16si128_cmp(<16 x i128> %x, <16 x i128> %y) nounwind readnone {
56       %cmp = icmp eq <16 x i128> %x, %y
57       %result = sext <16 x i1> %cmp to <16 x i128>
58       ret <16 x i128> %result
59; CHECK-LABEL: v16si128_cmp
60; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
61; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
62; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
63; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
64; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
65; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
66; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
67; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
68; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
69; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
70; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
71; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
72; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
73; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
74; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
75; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
76; CHECK: blr
77}
78
79; Greater than signed
80define <1 x i128> @v1si128_cmp_gt(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
81       %cmp = icmp sgt <1 x i128> %x, %y
82       %result = sext <1 x i1> %cmp to <1 x i128>
83       ret <1 x i128> %result
84; CHECK-LABEL: v1si128_cmp_gt
85; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
86; CHECK: blr
87}
88
89define <2 x i128> @v2si128_cmp_gt(<2 x i128> %x, <2 x i128> %y) nounwind readnone {
90       %cmp = icmp sgt <2 x i128> %x, %y
91       %result = sext <2 x i1> %cmp to <2 x i128>
92       ret <2 x i128> %result
93; CHECK-LABEL: v2si128_cmp_gt
94; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
95; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
96; CHECK: blr
97}
98
99define <4 x i128> @v4si128_cmp_gt(<4 x i128> %x, <4 x i128> %y) nounwind readnone {
100       %cmp = icmp sgt <4 x i128> %x, %y
101       %result = sext <4 x i1> %cmp to <4 x i128>
102       ret <4 x i128> %result
103; CHECK-LABEL: v4si128_cmp_gt
104; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
105; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
106; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
107; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
108; CHECK: blr
109}
110
111define <8 x i128> @v8si128_cmp_gt(<8 x i128> %x, <8 x i128> %y) nounwind readnone {
112       %cmp = icmp sgt <8 x i128> %x, %y
113       %result = sext <8 x i1> %cmp to <8 x i128>
114       ret <8 x i128> %result
115; CHECK-LABEL: v8si128_cmp_gt
116; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
117; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
118; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
119; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
120; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
121; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
122; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
123; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
124; CHECK: blr
125}
126
127define <16 x i128> @v16si128_cmp_gt(<16 x i128> %x, <16 x i128> %y) nounwind readnone {
128       %cmp = icmp sgt <16 x i128> %x, %y
129       %result = sext <16 x i1> %cmp to <16 x i128>
130       ret <16 x i128> %result
131; CHECK-LABEL: v16si128_cmp_gt
132; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
133; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
134; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
135; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
136; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
137; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
138; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
139; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
140; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
141; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
142; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
143; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
144; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
145; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
146; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
147; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
148; CHECK: blr
149}
150
151; Greater than unsigned
152define <1 x i128> @v1ui128_cmp_gt(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
153       %cmp = icmp ugt <1 x i128> %x, %y
154       %result = sext <1 x i1> %cmp to <1 x i128>
155       ret <1 x i128> %result
156; CHECK-LABEL: v1ui128_cmp_gt
157; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
158; CHECK: blr
159}
160
161define <2 x i128> @v2ui128_cmp_gt(<2 x i128> %x, <2 x i128> %y) nounwind readnone {
162       %cmp = icmp ugt <2 x i128> %x, %y
163       %result = sext <2 x i1> %cmp to <2 x i128>
164       ret <2 x i128> %result
165; CHECK-LABEL: v2ui128_cmp_gt
166; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
167; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
168; CHECK: blr
169}
170
171define <4 x i128> @v4ui128_cmp_gt(<4 x i128> %x, <4 x i128> %y) nounwind readnone {
172       %cmp = icmp ugt <4 x i128> %x, %y
173       %result = sext <4 x i1> %cmp to <4 x i128>
174       ret <4 x i128> %result
175; CHECK-LABEL: v4ui128_cmp_gt
176; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
177; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
178; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
179; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
180; CHECK: blr
181}
182
183define <8 x i128> @v8ui128_cmp_gt(<8 x i128> %x, <8 x i128> %y) nounwind readnone {
184       %cmp = icmp ugt <8 x i128> %x, %y
185       %result = sext <8 x i1> %cmp to <8 x i128>
186       ret <8 x i128> %result
187; CHECK-LABEL: v8ui128_cmp_gt
188; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
189; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
190; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
191; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
192; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
193; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
194; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
195; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
196; CHECK: blr
197}
198
199define <16 x i128> @v16ui128_cmp_gt(<16 x i128> %x, <16 x i128> %y) nounwind readnone {
200       %cmp = icmp ugt <16 x i128> %x, %y
201       %result = sext <16 x i1> %cmp to <16 x i128>
202       ret <16 x i128> %result
203; CHECK-LABEL: v16ui128_cmp_gt
204; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
205; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
206; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
207; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
208; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
209; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
210; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
211; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
212; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
213; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
214; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
215; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
216; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
217; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
218; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
219; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
220; CHECK: blr
221}
222
223; Check the intrinsics also
224declare <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>, <1 x i128>) nounwind readnone
225declare <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>, <1 x i128>) nounwind readnone
226declare <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128>, <1 x i128>) nounwind readnone
227
228define <1 x i128> @test_vcmpequq(<1 x i128> %x, <1 x i128> %y) {
229       %tmp = tail call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128> %x, <1 x i128> %y)
230       ret <1 x i128> %tmp
231; CHECK-LABEL: test_vcmpequq:
232; CHECK: vcmpequq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
233; CHECK: blr
234}
235
236define <1 x i128> @test_vcmpgtsq(<1 x i128> %x, <1 x i128> %y) {
237       %tmp = tail call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128> %x, <1 x i128> %y)
238       ret <1 x i128> %tmp
239; CHECK-LABEL: test_vcmpgtsq
240; CHECK: vcmpgtsq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
241; CHECK: blr
242}
243
244define <1 x i128> @test_vcmpgtuq(<1 x i128> %x, <1 x i128> %y) {
245       %tmp = tail call <1 x i128> @llvm.ppc.altivec.vcmpgtuq(<1 x i128> %x, <1 x i128> %y)
246       ret <1 x i128> %tmp
247; CHECK-LABEL: test_vcmpgtuq
248; CHECK: vcmpgtuq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
249; CHECK: blr
250}
251
252declare i32 @llvm.ppc.altivec.vcmpequq.p(i32, <1 x i128>, <1 x i128>) nounwind readnone
253declare i32 @llvm.ppc.altivec.vcmpgtsq.p(i32, <1 x i128>, <1 x i128>) nounwind readnone
254declare i32 @llvm.ppc.altivec.vcmpgtuq.p(i32, <1 x i128>, <1 x i128>) nounwind readnone
255
256define i32 @test_vcmpequq_p(<1 x i128> %x, <1 x i128> %y) {
257      %tmp = tail call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %x, <1 x i128> %y)
258      ret i32 %tmp
259; CHECK-LABEL: test_vcmpequq_p:
260; CHECK: vcmpequq. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
261; CHECK: blr
262}
263
264define i32 @test_vcmpgtsq_p(<1 x i128> %x, <1 x i128> %y) {
265      %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %x, <1 x i128> %y)
266      ret i32 %tmp
267; CHECK-LABEL: test_vcmpgtsq_p
268; CHECK: vcmpgtsq. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
269; CHECK: blr
270}
271
272define i32 @test_vcmpgtuq_p(<1 x i128> %x, <1 x i128> %y) {
273      %tmp = tail call i32 @llvm.ppc.altivec.vcmpgtuq.p(i32 2, <1 x i128> %x, <1 x i128> %y)
274      ret i32 %tmp
275; CHECK-LABEL: test_vcmpgtuq_p
276; CHECK: vcmpgtuq. {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
277; CHECK: blr
278}
279