xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec-trunc2.ll (revision a51712751c184ebe056718c938d2526693a31564) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN: FileCheck %s
5; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7; RUN: FileCheck %s --check-prefix=CHECK-BE
8
9define dso_local <8 x i8> @test8x32(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
10; CHECK-LABEL: test8x32:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    rldimi r3, r4, 32, 0
13; CHECK-NEXT:    rldimi r5, r6, 32, 0
14; CHECK-NEXT:    mtfprd f0, r3
15; CHECK-NEXT:    mtfprd f1, r5
16; CHECK-NEXT:    rldimi r7, r8, 32, 0
17; CHECK-NEXT:    rldimi r9, r10, 32, 0
18; CHECK-NEXT:    mtfprd f2, r7
19; CHECK-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
20; CHECK-NEXT:    addi r3, r3, .LCPI0_0@toc@l
21; CHECK-NEXT:    xxmrghd v2, vs1, vs0
22; CHECK-NEXT:    mtfprd f0, r9
23; CHECK-NEXT:    xxmrghd v3, vs0, vs2
24; CHECK-NEXT:    lxvd2x vs0, 0, r3
25; CHECK-NEXT:    xxswapd v4, vs0
26; CHECK-NEXT:    vperm v2, v3, v2, v4
27; CHECK-NEXT:    blr
28;
29; CHECK-BE-LABEL: test8x32:
30; CHECK-BE:       # %bb.0:
31; CHECK-BE-NEXT:    sldi r10, r10, 32
32; CHECK-BE-NEXT:    sldi r9, r9, 32
33; CHECK-BE-NEXT:    sldi r8, r8, 32
34; CHECK-BE-NEXT:    sldi r7, r7, 32
35; CHECK-BE-NEXT:    sldi r6, r6, 32
36; CHECK-BE-NEXT:    sldi r5, r5, 32
37; CHECK-BE-NEXT:    sldi r4, r4, 32
38; CHECK-BE-NEXT:    sldi r3, r3, 32
39; CHECK-BE-NEXT:    addi r11, r1, -80
40; CHECK-BE-NEXT:    std r10, -80(r1)
41; CHECK-BE-NEXT:    std r10, -72(r1)
42; CHECK-BE-NEXT:    std r9, -96(r1)
43; CHECK-BE-NEXT:    std r9, -88(r1)
44; CHECK-BE-NEXT:    std r8, -112(r1)
45; CHECK-BE-NEXT:    std r8, -104(r1)
46; CHECK-BE-NEXT:    std r7, -128(r1)
47; CHECK-BE-NEXT:    std r7, -120(r1)
48; CHECK-BE-NEXT:    std r6, -16(r1)
49; CHECK-BE-NEXT:    std r6, -8(r1)
50; CHECK-BE-NEXT:    std r5, -32(r1)
51; CHECK-BE-NEXT:    std r5, -24(r1)
52; CHECK-BE-NEXT:    std r4, -48(r1)
53; CHECK-BE-NEXT:    std r4, -40(r1)
54; CHECK-BE-NEXT:    std r3, -64(r1)
55; CHECK-BE-NEXT:    std r3, -56(r1)
56; CHECK-BE-NEXT:    addi r3, r1, -96
57; CHECK-BE-NEXT:    lxvw4x vs1, 0, r3
58; CHECK-BE-NEXT:    addi r3, r1, -112
59; CHECK-BE-NEXT:    lxvw4x vs2, 0, r3
60; CHECK-BE-NEXT:    addi r3, r1, -128
61; CHECK-BE-NEXT:    lxvw4x vs3, 0, r3
62; CHECK-BE-NEXT:    addi r3, r1, -16
63; CHECK-BE-NEXT:    lxvw4x vs4, 0, r3
64; CHECK-BE-NEXT:    addi r3, r1, -32
65; CHECK-BE-NEXT:    lxvw4x vs5, 0, r3
66; CHECK-BE-NEXT:    addi r3, r1, -48
67; CHECK-BE-NEXT:    lxvw4x vs6, 0, r3
68; CHECK-BE-NEXT:    addi r3, r1, -64
69; CHECK-BE-NEXT:    lxvw4x vs0, 0, r11
70; CHECK-BE-NEXT:    lxvw4x vs7, 0, r3
71; CHECK-BE-NEXT:    addis r3, r2, .LCPI0_0@toc@ha
72; CHECK-BE-NEXT:    addi r3, r3, .LCPI0_0@toc@l
73; CHECK-BE-NEXT:    xxmrghw vs0, vs1, vs0
74; CHECK-BE-NEXT:    xxmrghw vs1, vs3, vs2
75; CHECK-BE-NEXT:    xxmrghw vs2, vs5, vs4
76; CHECK-BE-NEXT:    lxvw4x v2, 0, r3
77; CHECK-BE-NEXT:    xxmrghw vs3, vs7, vs6
78; CHECK-BE-NEXT:    xxmrghd v3, vs1, vs0
79; CHECK-BE-NEXT:    xxmrghd v4, vs3, vs2
80; CHECK-BE-NEXT:    vperm v2, v4, v3, v2
81; CHECK-BE-NEXT:    blr
82%v10 = insertelement <8 x i32> undef, i32 %i1, i32 0
83%v11 = insertelement <8 x i32> %v10, i32 %i2, i32 1
84%v12 = insertelement <8 x i32> %v11, i32 %i3, i32 2
85%v13 = insertelement <8 x i32> %v12, i32 %i4, i32 3
86%v14 = insertelement <8 x i32> %v13, i32 %i5, i32 4
87%v15 = insertelement <8 x i32> %v14, i32 %i6, i32 5
88%v16 = insertelement <8 x i32> %v15, i32 %i7, i32 6
89%v17 = insertelement <8 x i32> %v16, i32 %i8, i32 7
90%v2 = trunc <8 x i32> %v17 to <8 x i8>
91ret <8 x i8> %v2
92}
93
94define dso_local <4 x i16> @test4x64(i64 %i1, i64 %i2, i64 %i3, i64 %i4) {
95; CHECK-LABEL: test4x64:
96; CHECK:       # %bb.0:
97; CHECK-NEXT:    mtfprd f0, r5
98; CHECK-NEXT:    mtfprd f1, r6
99; CHECK-NEXT:    xxmrghd v2, vs1, vs0
100; CHECK-NEXT:    mtfprd f0, r3
101; CHECK-NEXT:    mtfprd f1, r4
102; CHECK-NEXT:    addis r3, r2, .LCPI1_0@toc@ha
103; CHECK-NEXT:    addi r3, r3, .LCPI1_0@toc@l
104; CHECK-NEXT:    xxmrghd v3, vs1, vs0
105; CHECK-NEXT:    lxvd2x vs0, 0, r3
106; CHECK-NEXT:    xxswapd v4, vs0
107; CHECK-NEXT:    vperm v2, v2, v3, v4
108; CHECK-NEXT:    blr
109;
110; CHECK-BE-LABEL: test4x64:
111; CHECK-BE:       # %bb.0:
112; CHECK-BE-NEXT:    std r6, -8(r1)
113; CHECK-BE-NEXT:    std r5, -16(r1)
114; CHECK-BE-NEXT:    std r4, -24(r1)
115; CHECK-BE-NEXT:    std r3, -32(r1)
116; CHECK-BE-NEXT:    addi r3, r1, -32
117; CHECK-BE-NEXT:    addis r4, r2, .LCPI1_0@toc@ha
118; CHECK-BE-NEXT:    addi r7, r1, -16
119; CHECK-BE-NEXT:    lxvd2x v3, 0, r3
120; CHECK-BE-NEXT:    addi r3, r4, .LCPI1_0@toc@l
121; CHECK-BE-NEXT:    lxvd2x v2, 0, r7
122; CHECK-BE-NEXT:    lxvw4x v4, 0, r3
123; CHECK-BE-NEXT:    vperm v2, v3, v2, v4
124; CHECK-BE-NEXT:    blr
125%v10 = insertelement <4 x i64> undef, i64 %i1, i32 0
126%v11 = insertelement <4 x i64> %v10, i64 %i2, i32 1
127%v12 = insertelement <4 x i64> %v11, i64 %i3, i32 2
128%v13 = insertelement <4 x i64> %v12, i64 %i4, i32 3
129%v2 = trunc <4 x i64> %v13 to <4 x i16>
130ret <4 x i16> %v2
131}
132
133define dso_local <8 x i16> @test8x24(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8) {
134; CHECK-LABEL: test8x24:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    mtvsrd v2, r3
137; CHECK-NEXT:    mtvsrd v3, r4
138; CHECK-NEXT:    mtvsrd v4, r5
139; CHECK-NEXT:    mtvsrd v5, r6
140; CHECK-NEXT:    mtvsrd v0, r7
141; CHECK-NEXT:    vmrghh v2, v3, v2
142; CHECK-NEXT:    mtvsrd v3, r8
143; CHECK-NEXT:    vmrghh v4, v5, v4
144; CHECK-NEXT:    mtvsrd v5, r9
145; CHECK-NEXT:    xxmrglw vs0, v4, v2
146; CHECK-NEXT:    vmrghh v3, v3, v0
147; CHECK-NEXT:    mtvsrd v0, r10
148; CHECK-NEXT:    vmrghh v5, v0, v5
149; CHECK-NEXT:    xxmrglw vs1, v5, v3
150; CHECK-NEXT:    xxmrgld v2, vs1, vs0
151; CHECK-NEXT:    blr
152;
153; CHECK-BE-LABEL: test8x24:
154; CHECK-BE:       # %bb.0:
155; CHECK-BE-NEXT:    sldi r10, r10, 48
156; CHECK-BE-NEXT:    sldi r9, r9, 48
157; CHECK-BE-NEXT:    sldi r8, r8, 48
158; CHECK-BE-NEXT:    sldi r7, r7, 48
159; CHECK-BE-NEXT:    sldi r6, r6, 48
160; CHECK-BE-NEXT:    sldi r5, r5, 48
161; CHECK-BE-NEXT:    sldi r4, r4, 48
162; CHECK-BE-NEXT:    sldi r3, r3, 48
163; CHECK-BE-NEXT:    addi r11, r1, -16
164; CHECK-BE-NEXT:    std r10, -16(r1)
165; CHECK-BE-NEXT:    std r10, -8(r1)
166; CHECK-BE-NEXT:    std r9, -32(r1)
167; CHECK-BE-NEXT:    std r9, -24(r1)
168; CHECK-BE-NEXT:    std r8, -48(r1)
169; CHECK-BE-NEXT:    std r8, -40(r1)
170; CHECK-BE-NEXT:    std r7, -64(r1)
171; CHECK-BE-NEXT:    std r7, -56(r1)
172; CHECK-BE-NEXT:    std r6, -80(r1)
173; CHECK-BE-NEXT:    std r6, -72(r1)
174; CHECK-BE-NEXT:    std r5, -96(r1)
175; CHECK-BE-NEXT:    std r5, -88(r1)
176; CHECK-BE-NEXT:    std r4, -112(r1)
177; CHECK-BE-NEXT:    std r4, -104(r1)
178; CHECK-BE-NEXT:    std r3, -128(r1)
179; CHECK-BE-NEXT:    std r3, -120(r1)
180; CHECK-BE-NEXT:    addi r3, r1, -32
181; CHECK-BE-NEXT:    lxvw4x v3, 0, r3
182; CHECK-BE-NEXT:    addi r3, r1, -48
183; CHECK-BE-NEXT:    lxvw4x v4, 0, r3
184; CHECK-BE-NEXT:    addi r3, r1, -64
185; CHECK-BE-NEXT:    lxvw4x v5, 0, r3
186; CHECK-BE-NEXT:    addi r3, r1, -80
187; CHECK-BE-NEXT:    lxvw4x v0, 0, r3
188; CHECK-BE-NEXT:    addi r3, r1, -96
189; CHECK-BE-NEXT:    lxvw4x v1, 0, r3
190; CHECK-BE-NEXT:    addi r3, r1, -112
191; CHECK-BE-NEXT:    lxvw4x v6, 0, r3
192; CHECK-BE-NEXT:    addi r3, r1, -128
193; CHECK-BE-NEXT:    lxvw4x v2, 0, r11
194; CHECK-BE-NEXT:    lxvw4x v7, 0, r3
195; CHECK-BE-NEXT:    vmrghh v2, v3, v2
196; CHECK-BE-NEXT:    vmrghh v3, v5, v4
197; CHECK-BE-NEXT:    vmrghh v4, v1, v0
198; CHECK-BE-NEXT:    xxmrghw vs0, v3, v2
199; CHECK-BE-NEXT:    vmrghh v5, v7, v6
200; CHECK-BE-NEXT:    xxmrghw vs1, v5, v4
201; CHECK-BE-NEXT:    xxmrghd v2, vs1, vs0
202; CHECK-BE-NEXT:    blr
203%i11 = trunc i32 %i1 to i24
204%i21 = trunc i32 %i2 to i24
205%i31 = trunc i32 %i3 to i24
206%i41 = trunc i32 %i4 to i24
207%i51 = trunc i32 %i5 to i24
208%i61 = trunc i32 %i6 to i24
209%i71 = trunc i32 %i7 to i24
210%i81 = trunc i32 %i8 to i24
211%v10 = insertelement <8 x i24> undef, i24 %i11, i32 0
212%v11 = insertelement <8 x i24> %v10, i24 %i21, i32 1
213%v12 = insertelement <8 x i24> %v11, i24 %i31, i32 2
214%v13 = insertelement <8 x i24> %v12, i24 %i41, i32 3
215%v14 = insertelement <8 x i24> %v13, i24 %i51, i32 4
216%v15 = insertelement <8 x i24> %v14, i24 %i61, i32 5
217%v16 = insertelement <8 x i24> %v15, i24 %i71, i32 6
218%v17 = insertelement <8 x i24> %v16, i24 %i81, i32 7
219%v2 = trunc <8 x i24> %v17 to <8 x i16>
220ret <8 x i16> %v2
221}
222