xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec-trunc.ll (revision b922a3621116b404d868af8b74cab25ab78555be) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
4; RUN: FileCheck %s
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6; RUN:     -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7; RUN: FileCheck %s --check-prefix=CHECK-BE
8
9define void @test8i8(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {
10; CHECK-LABEL: test8i8:
11; CHECK:       # %bb.0: # %entry
12; CHECK-NEXT:    lxvd2x vs0, 0, r4
13; CHECK-NEXT:    xxswapd v2, vs0
14; CHECK-NEXT:    vpkuhum v2, v2, v2
15; CHECK-NEXT:    xxswapd vs0, v2
16; CHECK-NEXT:    stfdx f0, 0, r3
17; CHECK-NEXT:    blr
18;
19; CHECK-BE-LABEL: test8i8:
20; CHECK-BE:       # %bb.0: # %entry
21; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
22; CHECK-BE-NEXT:    addi r5, r1, -16
23; CHECK-BE-NEXT:    vpkuhum v2, v2, v2
24; CHECK-BE-NEXT:    stxvd2x v2, 0, r5
25; CHECK-BE-NEXT:    ld r4, -16(r1)
26; CHECK-BE-NEXT:    std r4, 0(r3)
27; CHECK-BE-NEXT:    blr
28entry:
29  %0 = load <8 x i16>, ptr %SrcPtr, align 16
30  %1 = trunc <8 x i16> %0 to <8 x i8>
31  store <8 x i8> %1, ptr %Sink, align 16
32  ret void
33}
34
35define void @test4i8(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {
36; CHECK-LABEL: test4i8:
37; CHECK:       # %bb.0: # %entry
38; CHECK-NEXT:    lxvd2x vs0, 0, r4
39; CHECK-NEXT:    xxswapd v2, vs0
40; CHECK-NEXT:    vpkuhum v2, v2, v2
41; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
42; CHECK-NEXT:    stfiwx f0, 0, r3
43; CHECK-NEXT:    blr
44;
45; CHECK-BE-LABEL: test4i8:
46; CHECK-BE:       # %bb.0: # %entry
47; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
48; CHECK-BE-NEXT:    addi r5, r1, -16
49; CHECK-BE-NEXT:    vpkuhum v2, v2, v2
50; CHECK-BE-NEXT:    stxvw4x v2, 0, r5
51; CHECK-BE-NEXT:    lwz r4, -16(r1)
52; CHECK-BE-NEXT:    stw r4, 0(r3)
53; CHECK-BE-NEXT:    blr
54entry:
55  %0 = load <4 x i16>, ptr %SrcPtr, align 16
56  %1 = trunc <4 x i16> %0 to <4 x i8>
57  store <4 x i8> %1, ptr %Sink, align 16
58  ret void
59}
60
61define void @test4i8w(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {
62; CHECK-LABEL: test4i8w:
63; CHECK:       # %bb.0: # %entry
64; CHECK-NEXT:    lxvd2x vs0, 0, r4
65; CHECK-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
66; CHECK-NEXT:    addi r4, r4, .LCPI2_0@toc@l
67; CHECK-NEXT:    xxswapd v2, vs0
68; CHECK-NEXT:    lxvd2x vs0, 0, r4
69; CHECK-NEXT:    xxswapd v3, vs0
70; CHECK-NEXT:    vperm v2, v2, v2, v3
71; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
72; CHECK-NEXT:    stfiwx f0, 0, r3
73; CHECK-NEXT:    blr
74;
75; CHECK-BE-LABEL: test4i8w:
76; CHECK-BE:       # %bb.0: # %entry
77; CHECK-BE-NEXT:    addis r5, r2, .LCPI2_0@toc@ha
78; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
79; CHECK-BE-NEXT:    addi r4, r5, .LCPI2_0@toc@l
80; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
81; CHECK-BE-NEXT:    addi r4, r1, -16
82; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
83; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
84; CHECK-BE-NEXT:    lwz r4, -16(r1)
85; CHECK-BE-NEXT:    stw r4, 0(r3)
86; CHECK-BE-NEXT:    blr
87entry:
88  %0 = load <4 x i32>, ptr %SrcPtr, align 16
89  %1 = trunc <4 x i32> %0 to <4 x i8>
90  store <4 x i8> %1, ptr %Sink, align 16
91  ret void
92}
93
94define void @test2i8(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {
95; CHECK-LABEL: test2i8:
96; CHECK:       # %bb.0: # %entry
97; CHECK-NEXT:    lxvd2x vs0, 0, r4
98; CHECK-NEXT:    xxswapd v2, vs0
99; CHECK-NEXT:    vpkuhum v2, v2, v2
100; CHECK-NEXT:    xxswapd vs0, v2
101; CHECK-NEXT:    mffprd r4, f0
102; CHECK-NEXT:    clrldi r4, r4, 48
103; CHECK-NEXT:    sth r4, 0(r3)
104; CHECK-NEXT:    blr
105;
106; CHECK-BE-LABEL: test2i8:
107; CHECK-BE:       # %bb.0: # %entry
108; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
109; CHECK-BE-NEXT:    addi r5, r1, -16
110; CHECK-BE-NEXT:    vpkuhum v2, v2, v2
111; CHECK-BE-NEXT:    stxvw4x v2, 0, r5
112; CHECK-BE-NEXT:    lhz r4, -16(r1)
113; CHECK-BE-NEXT:    sth r4, 0(r3)
114; CHECK-BE-NEXT:    blr
115entry:
116  %0 = load <2 x i16>, ptr %SrcPtr, align 16
117  %1 = trunc <2 x i16> %0 to <2 x i8>
118  store <2 x i8> %1, ptr %Sink, align 16
119  ret void
120}
121
122define void @test4i16(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {
123; CHECK-LABEL: test4i16:
124; CHECK:       # %bb.0: # %entry
125; CHECK-NEXT:    lxvd2x vs0, 0, r4
126; CHECK-NEXT:    xxswapd v2, vs0
127; CHECK-NEXT:    vpkuwum v2, v2, v2
128; CHECK-NEXT:    xxswapd vs0, v2
129; CHECK-NEXT:    stfdx f0, 0, r3
130; CHECK-NEXT:    blr
131;
132; CHECK-BE-LABEL: test4i16:
133; CHECK-BE:       # %bb.0: # %entry
134; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
135; CHECK-BE-NEXT:    addi r5, r1, -16
136; CHECK-BE-NEXT:    vpkuwum v2, v2, v2
137; CHECK-BE-NEXT:    stxvd2x v2, 0, r5
138; CHECK-BE-NEXT:    ld r4, -16(r1)
139; CHECK-BE-NEXT:    std r4, 0(r3)
140; CHECK-BE-NEXT:    blr
141entry:
142  %0 = load <4 x i32>, ptr %SrcPtr, align 16
143  %1 = trunc <4 x i32> %0 to <4 x i16>
144  store <4 x i16> %1, ptr %Sink, align 16
145  ret void
146}
147
148define void @test2i16(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {
149; CHECK-LABEL: test2i16:
150; CHECK:       # %bb.0: # %entry
151; CHECK-NEXT:    lxvd2x vs0, 0, r4
152; CHECK-NEXT:    xxswapd v2, vs0
153; CHECK-NEXT:    vpkuwum v2, v2, v2
154; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
155; CHECK-NEXT:    stfiwx f0, 0, r3
156; CHECK-NEXT:    blr
157;
158; CHECK-BE-LABEL: test2i16:
159; CHECK-BE:       # %bb.0: # %entry
160; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
161; CHECK-BE-NEXT:    addi r5, r1, -16
162; CHECK-BE-NEXT:    vpkuwum v2, v2, v2
163; CHECK-BE-NEXT:    stxvw4x v2, 0, r5
164; CHECK-BE-NEXT:    lwz r4, -16(r1)
165; CHECK-BE-NEXT:    stw r4, 0(r3)
166; CHECK-BE-NEXT:    blr
167entry:
168  %0 = load <2 x i32>, ptr %SrcPtr, align 16
169  %1 = trunc <2 x i32> %0 to <2 x i16>
170  store <2 x i16> %1, ptr %Sink, align 16
171  ret void
172}
173
174define void @test2i16d(ptr nocapture %Sink, ptr nocapture readonly %SrcPtr) {
175; CHECK-LABEL: test2i16d:
176; CHECK:       # %bb.0: # %entry
177; CHECK-NEXT:    lxvd2x vs0, 0, r4
178; CHECK-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
179; CHECK-NEXT:    addi r4, r4, .LCPI6_0@toc@l
180; CHECK-NEXT:    xxswapd v2, vs0
181; CHECK-NEXT:    lxvd2x vs0, 0, r4
182; CHECK-NEXT:    xxswapd v3, vs0
183; CHECK-NEXT:    vperm v2, v2, v2, v3
184; CHECK-NEXT:    xxsldwi vs0, v2, v2, 2
185; CHECK-NEXT:    stfiwx f0, 0, r3
186; CHECK-NEXT:    blr
187;
188; CHECK-BE-LABEL: test2i16d:
189; CHECK-BE:       # %bb.0: # %entry
190; CHECK-BE-NEXT:    addis r5, r2, .LCPI6_0@toc@ha
191; CHECK-BE-NEXT:    lxvw4x v2, 0, r4
192; CHECK-BE-NEXT:    addi r4, r5, .LCPI6_0@toc@l
193; CHECK-BE-NEXT:    lxvw4x v3, 0, r4
194; CHECK-BE-NEXT:    addi r4, r1, -16
195; CHECK-BE-NEXT:    vperm v2, v2, v2, v3
196; CHECK-BE-NEXT:    stxvw4x v2, 0, r4
197; CHECK-BE-NEXT:    lwz r4, -16(r1)
198; CHECK-BE-NEXT:    stw r4, 0(r3)
199; CHECK-BE-NEXT:    blr
200entry:
201  %0 = load <2 x i64>, ptr %SrcPtr, align 16
202  %1 = trunc <2 x i64> %0 to <2 x i16>
203  store <2 x i16> %1, ptr %Sink, align 16
204  ret void
205}
206