xref: /llvm-project/llvm/test/CodeGen/PowerPC/vec-min-max.ll (revision 55890968ac2d297803fa538c2eff66988dbb221f) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,PWR8
3; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr7 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,PWR7
4
5define <16 x i8> @getsmaxi8(<16 x i8> %a, <16 x i8> %b) {
6; CHECK-LABEL: getsmaxi8:
7; CHECK:       # %bb.0: # %entry
8; CHECK-NEXT:    vmaxsb 2, 2, 3
9; CHECK-NEXT:    blr
10entry:
11  %0 = icmp sgt <16 x i8> %a, %b
12  %1 = select <16 x i1> %0, <16 x i8> %a, <16 x i8> %b
13  ret <16 x i8> %1
14}
15
16define <8 x i16> @getsmaxi16(<8 x i16> %a, <8 x i16> %b) {
17; CHECK-LABEL: getsmaxi16:
18; CHECK:       # %bb.0: # %entry
19; CHECK-NEXT:    vmaxsh 2, 2, 3
20; CHECK-NEXT:    blr
21entry:
22  %0 = icmp sgt <8 x i16> %a, %b
23  %1 = select <8 x i1> %0, <8 x i16> %a, <8 x i16> %b
24  ret <8 x i16> %1
25}
26
27define <4 x i32> @getsmaxi32(<4 x i32> %a, <4 x i32> %b) {
28; CHECK-LABEL: getsmaxi32:
29; CHECK:       # %bb.0: # %entry
30; CHECK-NEXT:    vmaxsw 2, 2, 3
31; CHECK-NEXT:    blr
32entry:
33  %0 = icmp sgt <4 x i32> %a, %b
34  %1 = select <4 x i1> %0, <4 x i32> %a, <4 x i32> %b
35  ret <4 x i32> %1
36}
37
38define <2 x i64> @getsmaxi64(<2 x i64> %a, <2 x i64> %b) {
39; PWR8-LABEL: getsmaxi64:
40; PWR8:       # %bb.0: # %entry
41; PWR8-NEXT:    vmaxsd 2, 2, 3
42; PWR8-NEXT:    blr
43;
44; PWR7-LABEL: getsmaxi64:
45; PWR7:       # %bb.0: # %entry
46; PWR7-NEXT:    xxswapd 0, 35
47; PWR7-NEXT:    addi 3, 1, -32
48; PWR7-NEXT:    xxswapd 1, 34
49; PWR7-NEXT:    stxvd2x 0, 0, 3
50; PWR7-NEXT:    addi 3, 1, -48
51; PWR7-NEXT:    stxvd2x 1, 0, 3
52; PWR7-NEXT:    ld 3, -24(1)
53; PWR7-NEXT:    ld 4, -40(1)
54; PWR7-NEXT:    ld 6, -48(1)
55; PWR7-NEXT:    cmpd 4, 3
56; PWR7-NEXT:    li 3, 0
57; PWR7-NEXT:    li 4, -1
58; PWR7-NEXT:    iselgt 5, 4, 3
59; PWR7-NEXT:    std 5, -8(1)
60; PWR7-NEXT:    ld 5, -32(1)
61; PWR7-NEXT:    cmpd 6, 5
62; PWR7-NEXT:    iselgt 3, 4, 3
63; PWR7-NEXT:    std 3, -16(1)
64; PWR7-NEXT:    addi 3, 1, -16
65; PWR7-NEXT:    lxvd2x 0, 0, 3
66; PWR7-NEXT:    xxswapd 36, 0
67; PWR7-NEXT:    xxsel 34, 35, 34, 36
68; PWR7-NEXT:    blr
69entry:
70  %0 = icmp sgt <2 x i64> %a, %b
71  %1 = select <2 x i1> %0, <2 x i64> %a, <2 x i64> %b
72  ret <2 x i64> %1
73}
74
75define <4 x float> @getsmaxf32(<4 x float> %a, <4 x float> %b) {
76; CHECK-LABEL: getsmaxf32:
77; CHECK:       # %bb.0: # %entry
78; CHECK-NEXT:    xvmaxsp 34, 34, 35
79; CHECK-NEXT:    blr
80entry:
81  %0 = fcmp nnan nsz oge <4 x float> %a, %b
82  %1 = select <4 x i1> %0, <4 x float> %a, <4 x float> %b
83  ret <4 x float> %1
84}
85
86define <2 x double> @getsmaxf64(<2 x double> %a, <2 x double> %b) {
87; CHECK-LABEL: getsmaxf64:
88; CHECK:       # %bb.0: # %entry
89; CHECK-NEXT:    xvmaxdp 34, 34, 35
90; CHECK-NEXT:    blr
91entry:
92  %0 = fcmp nnan nsz oge <2 x double> %a, %b
93  %1 = select <2 x i1> %0, <2 x double> %a, <2 x double> %b
94  ret <2 x double> %1
95}
96
97define <16 x i8> @getsmini8(<16 x i8> %a, <16 x i8> %b) {
98; CHECK-LABEL: getsmini8:
99; CHECK:       # %bb.0: # %entry
100; CHECK-NEXT:    vminsb 2, 2, 3
101; CHECK-NEXT:    blr
102entry:
103  %0 = icmp slt <16 x i8> %a, %b
104  %1 = select <16 x i1> %0, <16 x i8> %a, <16 x i8> %b
105  ret <16 x i8> %1
106}
107
108define <8 x i16> @getsmini16(<8 x i16> %a, <8 x i16> %b) {
109; CHECK-LABEL: getsmini16:
110; CHECK:       # %bb.0: # %entry
111; CHECK-NEXT:    vminsh 2, 2, 3
112; CHECK-NEXT:    blr
113entry:
114  %0 = icmp slt <8 x i16> %a, %b
115  %1 = select <8 x i1> %0, <8 x i16> %a, <8 x i16> %b
116  ret <8 x i16> %1
117}
118
119define <4 x i32> @getsmini32(<4 x i32> %a, <4 x i32> %b) {
120; CHECK-LABEL: getsmini32:
121; CHECK:       # %bb.0: # %entry
122; CHECK-NEXT:    vminsw 2, 2, 3
123; CHECK-NEXT:    blr
124entry:
125  %0 = icmp slt <4 x i32> %a, %b
126  %1 = select <4 x i1> %0, <4 x i32> %a, <4 x i32> %b
127  ret <4 x i32> %1
128}
129
130define <2 x i64> @getsmini64(<2 x i64> %a, <2 x i64> %b) {
131; PWR8-LABEL: getsmini64:
132; PWR8:       # %bb.0: # %entry
133; PWR8-NEXT:    vminsd 2, 2, 3
134; PWR8-NEXT:    blr
135;
136; PWR7-LABEL: getsmini64:
137; PWR7:       # %bb.0: # %entry
138; PWR7-NEXT:    xxswapd 0, 35
139; PWR7-NEXT:    addi 3, 1, -32
140; PWR7-NEXT:    xxswapd 1, 34
141; PWR7-NEXT:    stxvd2x 0, 0, 3
142; PWR7-NEXT:    addi 3, 1, -48
143; PWR7-NEXT:    stxvd2x 1, 0, 3
144; PWR7-NEXT:    ld 3, -24(1)
145; PWR7-NEXT:    ld 4, -40(1)
146; PWR7-NEXT:    ld 6, -48(1)
147; PWR7-NEXT:    cmpd 4, 3
148; PWR7-NEXT:    li 3, 0
149; PWR7-NEXT:    li 4, -1
150; PWR7-NEXT:    isellt 5, 4, 3
151; PWR7-NEXT:    std 5, -8(1)
152; PWR7-NEXT:    ld 5, -32(1)
153; PWR7-NEXT:    cmpd 6, 5
154; PWR7-NEXT:    isellt 3, 4, 3
155; PWR7-NEXT:    std 3, -16(1)
156; PWR7-NEXT:    addi 3, 1, -16
157; PWR7-NEXT:    lxvd2x 0, 0, 3
158; PWR7-NEXT:    xxswapd 36, 0
159; PWR7-NEXT:    xxsel 34, 35, 34, 36
160; PWR7-NEXT:    blr
161entry:
162  %0 = icmp slt <2 x i64> %a, %b
163  %1 = select <2 x i1> %0, <2 x i64> %a, <2 x i64> %b
164  ret <2 x i64> %1
165}
166
167define <4 x float> @getsminf32(<4 x float> %a, <4 x float> %b) {
168; CHECK-LABEL: getsminf32:
169; CHECK:       # %bb.0: # %entry
170; CHECK-NEXT:    xvminsp 34, 34, 35
171; CHECK-NEXT:    blr
172entry:
173  %0 = fcmp nnan nsz ole <4 x float> %a, %b
174  %1 = select <4 x i1> %0, <4 x float> %a, <4 x float> %b
175  ret <4 x float> %1
176}
177
178define <2 x double> @getsminf64(<2 x double> %a, <2 x double> %b) {
179; CHECK-LABEL: getsminf64:
180; CHECK:       # %bb.0: # %entry
181; CHECK-NEXT:    xvmindp 34, 34, 35
182; CHECK-NEXT:    blr
183entry:
184  %0 = fcmp nnan nsz ole <2 x double> %a, %b
185  %1 = select <2 x i1> %0, <2 x double> %a, <2 x double> %b
186  ret <2 x double> %1
187}
188
189define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
190; PWR8-LABEL: invalidv1i128:
191; PWR8:       # %bb.0:
192; PWR8-NEXT:    mfvsrd 3, 36
193; PWR8-NEXT:    mfvsrd 4, 34
194; PWR8-NEXT:    cmpld 4, 3
195; PWR8-NEXT:    xxswapd 0, 36
196; PWR8-NEXT:    xxswapd 1, 34
197; PWR8-NEXT:    cmpd 1, 4, 3
198; PWR8-NEXT:    mffprd 3, 0
199; PWR8-NEXT:    mffprd 4, 1
200; PWR8-NEXT:    crandc 20, 4, 2
201; PWR8-NEXT:    cmpld 1, 4, 3
202; PWR8-NEXT:    bc 12, 20, .LBB12_3
203; PWR8-NEXT:  # %bb.1:
204; PWR8-NEXT:    crand 20, 2, 4
205; PWR8-NEXT:    bc 12, 20, .LBB12_3
206; PWR8-NEXT:  # %bb.2:
207; PWR8-NEXT:    vmr 2, 4
208; PWR8-NEXT:  .LBB12_3:
209; PWR8-NEXT:    xxswapd 0, 34
210; PWR8-NEXT:    mfvsrd 4, 34
211; PWR8-NEXT:    mffprd 3, 0
212; PWR8-NEXT:    blr
213;
214; PWR7-LABEL: invalidv1i128:
215; PWR7:       # %bb.0:
216; PWR7-NEXT:    cmpld 4, 8
217; PWR7-NEXT:    cmpd 1, 4, 8
218; PWR7-NEXT:    crandc 20, 4, 2
219; PWR7-NEXT:    cmpld 1, 3, 7
220; PWR7-NEXT:    crand 21, 2, 4
221; PWR7-NEXT:    cror 20, 21, 20
222; PWR7-NEXT:    isel 3, 3, 7, 20
223; PWR7-NEXT:    isel 4, 4, 8, 20
224; PWR7-NEXT:    std 3, -32(1)
225; PWR7-NEXT:    addi 3, 1, -32
226; PWR7-NEXT:    std 4, -24(1)
227; PWR7-NEXT:    lxvd2x 0, 0, 3
228; PWR7-NEXT:    addi 3, 1, -16
229; PWR7-NEXT:    stxvd2x 0, 0, 3
230; PWR7-NEXT:    ld 3, -16(1)
231; PWR7-NEXT:    ld 4, -8(1)
232; PWR7-NEXT:    blr
233%1 = icmp slt <2 x i128> %v1, %v2
234%2 = select <2 x i1> %1, <2 x i128> %v1, <2 x i128> %v2
235%3 = extractelement <2 x i128> %2, i32 0
236ret i128 %3
237}
238