1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-convert-rr-to-ri=false -ppc-asm-full-reg-names < %s | FileCheck %s 3 4; ISEL matches address mode xaddr. 5define i8 @test_xaddr(ptr %p) { 6; CHECK-LABEL: test_xaddr: 7; CHECK: # %bb.0: # %entry 8; CHECK-NEXT: li r4, 0 9; CHECK-NEXT: std r3, -8(r1) 10; CHECK-NEXT: ori r4, r4, 40000 11; CHECK-NEXT: lbzx r3, r3, r4 12; CHECK-NEXT: blr 13entry: 14 %p.addr = alloca ptr, align 8 15 store ptr %p, ptr %p.addr, align 8 16 %0 = load ptr, ptr %p.addr, align 8 17 %add.ptr = getelementptr inbounds i8, ptr %0, i64 40000 18 %1 = load i8, ptr %add.ptr, align 1 19 ret i8 %1 20} 21 22; ISEL matches address mode xaddrX4. 23define i64 @test_xaddrX4(ptr %p) { 24; CHECK-LABEL: test_xaddrX4: 25; CHECK: # %bb.0: # %entry 26; CHECK-NEXT: li r4, 3 27; CHECK-NEXT: std r3, -8(r1) 28; CHECK-NEXT: ldx r3, r3, r4 29; CHECK-NEXT: blr 30entry: 31 %p.addr = alloca ptr, align 8 32 store ptr %p, ptr %p.addr, align 8 33 %0 = load ptr, ptr %p.addr, align 8 34 %add.ptr = getelementptr inbounds i8, ptr %0, i64 3 35 %1 = load i64, ptr %add.ptr, align 8 36 ret i64 %1 37} 38 39; ISEL matches address mode xaddrX16. 40define <2 x double> @test_xaddrX16(ptr %arr) { 41; CHECK-LABEL: test_xaddrX16: 42; CHECK: # %bb.0: # %entry 43; CHECK-NEXT: li r4, 40 44; CHECK-NEXT: lxvx vs34, r3, r4 45; CHECK-NEXT: blr 46entry: 47 %arrayidx1 = getelementptr inbounds double, ptr %arr, i64 5 48 %0 = load <2 x double>, ptr %arrayidx1, align 16 49 ret <2 x double> %0 50} 51 52; ISEL matches address mode xoaddr. 53define void @test_xoaddr(ptr %arr, ptr %arrTo) { 54; CHECK-LABEL: test_xoaddr: 55; CHECK: # %bb.0: # %entry 56; CHECK-NEXT: li r5, 8 57; CHECK-NEXT: lxvx vs0, r3, r5 58; CHECK-NEXT: li r3, 4 59; CHECK-NEXT: stxvx vs0, r4, r3 60; CHECK-NEXT: blr 61entry: 62 %arrayidx = getelementptr inbounds i32, ptr %arrTo, i64 1 63 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 2 64 %0 = load <4 x i32>, ptr %arrayidx1, align 8 65 store <4 x i32> %0, ptr %arrayidx, align 8 66 ret void 67} 68 69; ISEL matches address mode xaddrX4 and generates LI which can be moved outside of 70; loop. 71define i64 @test_xaddrX4_loop(ptr %p) { 72; CHECK-LABEL: test_xaddrX4_loop: 73; CHECK: # %bb.0: # %entry 74; CHECK-NEXT: addi r4, r3, -8 75; CHECK-NEXT: li r3, 8 76; CHECK-NEXT: li r5, 3 77; CHECK-NEXT: mtctr r3 78; CHECK-NEXT: li r3, 0 79; CHECK-NEXT: .p2align 4 80; CHECK-NEXT: .LBB4_1: # %for.body 81; CHECK-NEXT: # 82; CHECK-NEXT: ldu r6, 8(r4) 83; CHECK-NEXT: ldx r7, r4, r5 84; CHECK-NEXT: maddld r3, r7, r6, r3 85; CHECK-NEXT: bdnz .LBB4_1 86; CHECK-NEXT: # %bb.2: # %for.end 87; CHECK-NEXT: blr 88; loop instruction number is changed from 5 to 4, so its align is changed from 5 to 4. 89entry: 90 br label %for.body 91 92for.body: ; preds = %for.body, %entry 93 %i.015 = phi i64 [ 0, %entry ], [ %inc, %for.body ] 94 %res.014 = phi i64 [ 0, %entry ], [ %add, %for.body ] 95 %mul = shl i64 %i.015, 3 96 %add.ptr = getelementptr inbounds i8, ptr %p, i64 %mul 97 %0 = load i64, ptr %add.ptr, align 8 98 %add.ptr3 = getelementptr inbounds i8, ptr %add.ptr, i64 3 99 %1 = load i64, ptr %add.ptr3, align 8 100 %mul4 = mul i64 %1, %0 101 %add = add i64 %mul4, %res.014 102 %inc = add nuw nsw i64 %i.015, 1 103 %exitcond = icmp eq i64 %inc, 8 104 br i1 %exitcond, label %for.end, label %for.body 105 106for.end: ; preds = %for.body 107 ret i64 %add 108 109} 110