xref: /llvm-project/llvm/test/CodeGen/PowerPC/testComparesilesll.ll (revision b922a3621116b404d868af8b74cab25ab78555be) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
3; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
4; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
6; RUN:   -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
7; RUN:  --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
8@glob = dso_local local_unnamed_addr global i64 0, align 8
9
10define dso_local signext i32 @test_ilesll(i64 %a, i64 %b) {
11; CHECK-LABEL: test_ilesll:
12; CHECK:       # %bb.0: # %entry
13; CHECK-NEXT:    sradi r5, r4, 63
14; CHECK-NEXT:    rldicl r6, r3, 1, 63
15; CHECK-NEXT:    subfc r3, r3, r4
16; CHECK-NEXT:    adde r3, r5, r6
17; CHECK-NEXT:    blr
18; CHECK-BE-LABEL: test_ilesll:
19; CHECK-BE:       # %bb.0: # %entry
20; CHECK-BE-NEXT:    rldicl r5, r3, 1, 63
21; CHECK-BE-NEXT:    sradi r6, r4, 63
22; CHECK-BE-NEXT:    subc r3, r4, r3
23; CHECK-BE-NEXT:    adde r3, r6, r5
24; CHECK-BE-NEXT:    blr
25;
26; CHECK-LE-LABEL: test_ilesll:
27; CHECK-LE:       # %bb.0: # %entry
28; CHECK-LE-NEXT:    rldicl r5, r3, 1, 63
29; CHECK-LE-NEXT:    sradi r6, r4, 63
30; CHECK-LE-NEXT:    subc r3, r4, r3
31; CHECK-LE-NEXT:    adde r3, r6, r5
32; CHECK-LE-NEXT:    blr
33entry:
34  %cmp = icmp sle i64 %a, %b
35  %conv = zext i1 %cmp to i32
36  ret i32 %conv
37}
38
39define dso_local signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
40; CHECK-LABEL: test_ilesll_sext:
41; CHECK:       # %bb.0: # %entry
42; CHECK-NEXT:    sradi r5, r4, 63
43; CHECK-NEXT:    rldicl r6, r3, 1, 63
44; CHECK-NEXT:    subfc r3, r3, r4
45; CHECK-NEXT:    adde r3, r5, r6
46; CHECK-NEXT:    neg r3, r3
47; CHECK-NEXT:    blr
48; CHECK-BE-LABEL: test_ilesll_sext:
49; CHECK-BE:       # %bb.0: # %entry
50; CHECK-BE-NEXT:    rldicl r5, r3, 1, 63
51; CHECK-BE-NEXT:    sradi r6, r4, 63
52; CHECK-BE-NEXT:    subc r3, r4, r3
53; CHECK-BE-NEXT:    adde r3, r6, r5
54; CHECK-BE-NEXT:    neg r3, r3
55; CHECK-BE-NEXT:    blr
56;
57; CHECK-LE-LABEL: test_ilesll_sext:
58; CHECK-LE:       # %bb.0: # %entry
59; CHECK-LE-NEXT:    rldicl r5, r3, 1, 63
60; CHECK-LE-NEXT:    sradi r6, r4, 63
61; CHECK-LE-NEXT:    subc r3, r4, r3
62; CHECK-LE-NEXT:    adde r3, r6, r5
63; CHECK-LE-NEXT:    neg r3, r3
64; CHECK-LE-NEXT:    blr
65entry:
66  %cmp = icmp sle i64 %a, %b
67  %sub = sext i1 %cmp to i32
68  ret i32 %sub
69}
70
71define dso_local signext i32 @test_ilesll_z(i64 %a) {
72; CHECK-LABEL: test_ilesll_z:
73; CHECK:       # %bb.0: # %entry
74; CHECK-NEXT:    addi r4, r3, -1
75; CHECK-NEXT:    or r3, r4, r3
76; CHECK-NEXT:    rldicl r3, r3, 1, 63
77; CHECK-NEXT:    blr
78; CHECK-BE-LABEL: test_ilesll_z:
79; CHECK-BE:       # %bb.0: # %entry
80; CHECK-BE-NEXT:    addi r4, r3, -1
81; CHECK-BE-NEXT:    or r3, r4, r3
82; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
83; CHECK-BE-NEXT:    blr
84;
85; CHECK-LE-LABEL: test_ilesll_z:
86; CHECK-LE:       # %bb.0: # %entry
87; CHECK-LE-NEXT:    addi r4, r3, -1
88; CHECK-LE-NEXT:    or r3, r4, r3
89; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
90; CHECK-LE-NEXT:    blr
91entry:
92  %cmp = icmp slt i64 %a, 1
93  %conv = zext i1 %cmp to i32
94  ret i32 %conv
95}
96
97define dso_local signext i32 @test_ilesll_sext_z(i64 %a) {
98; CHECK-LABEL: test_ilesll_sext_z:
99; CHECK:       # %bb.0: # %entry
100; CHECK-NEXT:    addi r4, r3, -1
101; CHECK-NEXT:    or r3, r4, r3
102; CHECK-NEXT:    sradi r3, r3, 63
103; CHECK-NEXT:    blr
104; CHECK-BE-LABEL: test_ilesll_sext_z:
105; CHECK-BE:       # %bb.0: # %entry
106; CHECK-BE-NEXT:    addi r4, r3, -1
107; CHECK-BE-NEXT:    or r3, r4, r3
108; CHECK-BE-NEXT:    sradi r3, r3, 63
109; CHECK-BE-NEXT:    blr
110;
111; CHECK-LE-LABEL: test_ilesll_sext_z:
112; CHECK-LE:       # %bb.0: # %entry
113; CHECK-LE-NEXT:    addi r4, r3, -1
114; CHECK-LE-NEXT:    or r3, r4, r3
115; CHECK-LE-NEXT:    sradi r3, r3, 63
116; CHECK-LE-NEXT:    blr
117entry:
118  %cmp = icmp slt i64 %a, 1
119  %sub = sext i1 %cmp to i32
120  ret i32 %sub
121}
122
123define dso_local void @test_ilesll_store(i64 %a, i64 %b) {
124; CHECK-LABEL: test_ilesll_store:
125; CHECK:       # %bb.0: # %entry
126; CHECK-NEXT:    sradi r6, r4, 63
127; CHECK-NEXT:    addis r5, r2, glob@toc@ha
128; CHECK-NEXT:    subfc r4, r3, r4
129; CHECK-NEXT:    rldicl r3, r3, 1, 63
130; CHECK-NEXT:    adde r3, r6, r3
131; CHECK-NEXT:    std r3, glob@toc@l(r5)
132; CHECK-NEXT:    blr
133; CHECK-BE-LABEL: test_ilesll_store:
134; CHECK-BE:       # %bb.0: # %entry
135; CHECK-BE-NEXT:    rldicl r5, r3, 1, 63
136; CHECK-BE-NEXT:    sradi r6, r4, 63
137; CHECK-BE-NEXT:    subc r3, r4, r3
138; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
139; CHECK-BE-NEXT:    adde r3, r6, r5
140; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
141; CHECK-BE-NEXT:    blr
142;
143; CHECK-LE-LABEL: test_ilesll_store:
144; CHECK-LE:       # %bb.0: # %entry
145; CHECK-LE-NEXT:    rldicl r5, r3, 1, 63
146; CHECK-LE-NEXT:    sradi r6, r4, 63
147; CHECK-LE-NEXT:    subc r3, r4, r3
148; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
149; CHECK-LE-NEXT:    adde r3, r6, r5
150; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
151; CHECK-LE-NEXT:    blr
152entry:
153  %cmp = icmp sle i64 %a, %b
154  %conv1 = zext i1 %cmp to i64
155  store i64 %conv1, ptr @glob, align 8
156  ret void
157}
158
159define dso_local void @test_ilesll_sext_store(i64 %a, i64 %b) {
160; CHECK-LABEL: test_ilesll_sext_store:
161; CHECK:       # %bb.0: # %entry
162; CHECK-NEXT:    sradi r6, r4, 63
163; CHECK-NEXT:    addis r5, r2, glob@toc@ha
164; CHECK-NEXT:    subfc r4, r3, r4
165; CHECK-NEXT:    rldicl r3, r3, 1, 63
166; CHECK-NEXT:    adde r3, r6, r3
167; CHECK-NEXT:    neg r3, r3
168; CHECK-NEXT:    std r3, glob@toc@l(r5)
169; CHECK-NEXT:    blr
170; CHECK-BE-LABEL: test_ilesll_sext_store:
171; CHECK-BE:       # %bb.0: # %entry
172; CHECK-BE-NEXT:    rldicl r5, r3, 1, 63
173; CHECK-BE-NEXT:    sradi r6, r4, 63
174; CHECK-BE-NEXT:    subc r3, r4, r3
175; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
176; CHECK-BE-NEXT:    adde r3, r6, r5
177; CHECK-BE-NEXT:    neg r3, r3
178; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
179; CHECK-BE-NEXT:    blr
180;
181; CHECK-LE-LABEL: test_ilesll_sext_store:
182; CHECK-LE:       # %bb.0: # %entry
183; CHECK-LE-NEXT:    rldicl r5, r3, 1, 63
184; CHECK-LE-NEXT:    sradi r6, r4, 63
185; CHECK-LE-NEXT:    subc r3, r4, r3
186; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
187; CHECK-LE-NEXT:    adde r3, r6, r5
188; CHECK-LE-NEXT:    neg r3, r3
189; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
190; CHECK-LE-NEXT:    blr
191entry:
192  %cmp = icmp sle i64 %a, %b
193  %conv1 = sext i1 %cmp to i64
194  store i64 %conv1, ptr @glob, align 8
195  ret void
196}
197
198define dso_local void @test_ilesll_z_store(i64 %a) {
199; CHECK-LABEL: test_ilesll_z_store:
200; CHECK:       # %bb.0: # %entry
201; CHECK-NEXT:    addi r5, r3, -1
202; CHECK-NEXT:    addis r4, r2, glob@toc@ha
203; CHECK-NEXT:    or r3, r5, r3
204; CHECK-NEXT:    rldicl r3, r3, 1, 63
205; CHECK-NEXT:    std r3, glob@toc@l(r4)
206; CHECK-NEXT:    blr
207; CHECK-BE-LABEL: test_ilesll_z_store:
208; CHECK-BE:       # %bb.0: # %entry
209; CHECK-BE-NEXT:    addi r4, r3, -1
210; CHECK-BE-NEXT:    or r3, r4, r3
211; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
212; CHECK-BE-NEXT:    rldicl r3, r3, 1, 63
213; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
214; CHECK-BE-NEXT:    blr
215;
216; CHECK-LE-LABEL: test_ilesll_z_store:
217; CHECK-LE:       # %bb.0: # %entry
218; CHECK-LE-NEXT:    addi r4, r3, -1
219; CHECK-LE-NEXT:    or r3, r4, r3
220; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
221; CHECK-LE-NEXT:    rldicl r3, r3, 1, 63
222; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
223; CHECK-LE-NEXT:    blr
224entry:
225  %cmp = icmp slt i64 %a, 1
226  %conv1 = zext i1 %cmp to i64
227  store i64 %conv1, ptr @glob, align 8
228  ret void
229}
230
231define dso_local void @test_ilesll_sext_z_store(i64 %a) {
232; CHECK-LABEL: test_ilesll_sext_z_store:
233; CHECK:       # %bb.0: # %entry
234; CHECK-NEXT:    addi r5, r3, -1
235; CHECK-NEXT:    addis r4, r2, glob@toc@ha
236; CHECK-NEXT:    or r3, r5, r3
237; CHECK-NEXT:    sradi r3, r3, 63
238; CHECK-NEXT:    std r3, glob@toc@l(r4)
239; CHECK-NEXT:    blr
240; CHECK-BE-LABEL: test_ilesll_sext_z_store:
241; CHECK-BE:       # %bb.0: # %entry
242; CHECK-BE-NEXT:    addi r4, r3, -1
243; CHECK-BE-NEXT:    or r3, r4, r3
244; CHECK-BE-NEXT:    addis r4, r2, glob@toc@ha
245; CHECK-BE-NEXT:    sradi r3, r3, 63
246; CHECK-BE-NEXT:    std r3, glob@toc@l(r4)
247; CHECK-BE-NEXT:    blr
248;
249; CHECK-LE-LABEL: test_ilesll_sext_z_store:
250; CHECK-LE:       # %bb.0: # %entry
251; CHECK-LE-NEXT:    addi r4, r3, -1
252; CHECK-LE-NEXT:    or r3, r4, r3
253; CHECK-LE-NEXT:    addis r4, r2, glob@toc@ha
254; CHECK-LE-NEXT:    sradi r3, r3, 63
255; CHECK-LE-NEXT:    std r3, glob@toc@l(r4)
256; CHECK-LE-NEXT:    blr
257entry:
258  %cmp = icmp slt i64 %a, 1
259  %conv1 = sext i1 %cmp to i64
260  store i64 %conv1, ptr @glob, align 8
261  ret void
262}
263