1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 4; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-LE-P7 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 6; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 7; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE-P8 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 9; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 10; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-LE-P9 11; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 12; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 13; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE-P7 14; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 15; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 16; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE-P8 17; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 18; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 19; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-BE-P9 20; xscvdpsxws and xscvdpsxws is only available on Power7 and above 21; Codgen is different for Power7, Power8, and Power9. 22 23define dso_local <4 x i32> @test(<4 x i32> %a, double %b) { 24; CHECK-LE-P7-LABEL: test: 25; CHECK-LE-P7: # %bb.0: # %entry 26; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1 27; CHECK-LE-P7-NEXT: addi r3, r1, -4 28; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI0_0@toc@ha 29; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI0_0@toc@l 30; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3 31; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4 32; CHECK-LE-P7-NEXT: xxswapd v3, vs0 33; CHECK-LE-P7-NEXT: lfiwzx f0, 0, r3 34; CHECK-LE-P7-NEXT: xxspltw v4, vs0, 1 35; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3 36; CHECK-LE-P7-NEXT: blr 37; 38; CHECK-LE-P8-LABEL: test: 39; CHECK-LE-P8: # %bb.0: # %entry 40; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha 41; CHECK-LE-P8-NEXT: xscvdpsxws v4, f1 42; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l 43; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3 44; CHECK-LE-P8-NEXT: xxswapd v3, vs0 45; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3 46; CHECK-LE-P8-NEXT: blr 47; 48; CHECK-LE-P9-LABEL: test: 49; CHECK-LE-P9: # %bb.0: # %entry 50; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1 51; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0 52; CHECK-LE-P9-NEXT: blr 53; 54; CHECK-BE-P7-LABEL: test: 55; CHECK-BE-P7: # %bb.0: # %entry 56; CHECK-BE-P7-NEXT: xscvdpsxws f0, f1 57; CHECK-BE-P7-NEXT: addi r3, r1, -4 58; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3 59; CHECK-BE-P7-NEXT: lfiwzx f0, 0, r3 60; CHECK-BE-P7-NEXT: addis r3, r2, .LCPI0_0@toc@ha 61; CHECK-BE-P7-NEXT: addi r3, r3, .LCPI0_0@toc@l 62; CHECK-BE-P7-NEXT: lxvw4x v4, 0, r3 63; CHECK-BE-P7-NEXT: xxspltw v3, vs0, 1 64; CHECK-BE-P7-NEXT: vperm v2, v2, v3, v4 65; CHECK-BE-P7-NEXT: blr 66; 67; CHECK-BE-P8-LABEL: test: 68; CHECK-BE-P8: # %bb.0: # %entry 69; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha 70; CHECK-BE-P8-NEXT: xscvdpsxws v4, f1 71; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l 72; CHECK-BE-P8-NEXT: lxvw4x v3, 0, r3 73; CHECK-BE-P8-NEXT: vperm v2, v2, v4, v3 74; CHECK-BE-P8-NEXT: blr 75; 76; CHECK-BE-P9-LABEL: test: 77; CHECK-BE-P9: # %bb.0: # %entry 78; CHECK-BE-P9-NEXT: xscvdpsxws f0, f1 79; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12 80; CHECK-BE-P9-NEXT: blr 81entry: 82 %conv = fptosi double %b to i32 83 %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3 84 ret <4 x i32> %vecins 85} 86 87define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) { 88; CHECK-LE-P7-LABEL: test2: 89; CHECK-LE-P7: # %bb.0: # %entry 90; CHECK-LE-P7-NEXT: xscvdpsxws f0, f1 91; CHECK-LE-P7-NEXT: addi r3, r1, -4 92; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI1_0@toc@ha 93; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI1_0@toc@l 94; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3 95; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4 96; CHECK-LE-P7-NEXT: xxswapd v3, vs0 97; CHECK-LE-P7-NEXT: lfiwzx f0, 0, r3 98; CHECK-LE-P7-NEXT: xxspltw v4, vs0, 1 99; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3 100; CHECK-LE-P7-NEXT: blr 101; 102; CHECK-LE-P8-LABEL: test2: 103; CHECK-LE-P8: # %bb.0: # %entry 104; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha 105; CHECK-LE-P8-NEXT: xscvdpsxws v4, f1 106; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l 107; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3 108; CHECK-LE-P8-NEXT: xxswapd v3, vs0 109; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3 110; CHECK-LE-P8-NEXT: blr 111; 112; CHECK-LE-P9-LABEL: test2: 113; CHECK-LE-P9: # %bb.0: # %entry 114; CHECK-LE-P9-NEXT: xscvdpsxws f0, f1 115; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0 116; CHECK-LE-P9-NEXT: blr 117; 118; CHECK-BE-P7-LABEL: test2: 119; CHECK-BE-P7: # %bb.0: # %entry 120; CHECK-BE-P7-NEXT: xscvdpsxws f0, f1 121; CHECK-BE-P7-NEXT: addi r3, r1, -4 122; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3 123; CHECK-BE-P7-NEXT: lfiwzx f0, 0, r3 124; CHECK-BE-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha 125; CHECK-BE-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l 126; CHECK-BE-P7-NEXT: lxvw4x v4, 0, r3 127; CHECK-BE-P7-NEXT: xxspltw v3, vs0, 1 128; CHECK-BE-P7-NEXT: vperm v2, v2, v3, v4 129; CHECK-BE-P7-NEXT: blr 130; 131; CHECK-BE-P8-LABEL: test2: 132; CHECK-BE-P8: # %bb.0: # %entry 133; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha 134; CHECK-BE-P8-NEXT: xscvdpsxws v4, f1 135; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l 136; CHECK-BE-P8-NEXT: lxvw4x v3, 0, r3 137; CHECK-BE-P8-NEXT: vperm v2, v2, v4, v3 138; CHECK-BE-P8-NEXT: blr 139; 140; CHECK-BE-P9-LABEL: test2: 141; CHECK-BE-P9: # %bb.0: # %entry 142; CHECK-BE-P9-NEXT: xscvdpsxws f0, f1 143; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12 144; CHECK-BE-P9-NEXT: blr 145entry: 146 %conv = fptosi float %b to i32 147 %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3 148 ret <4 x i32> %vecins 149} 150 151define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) { 152; CHECK-LE-P7-LABEL: test3: 153; CHECK-LE-P7: # %bb.0: # %entry 154; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1 155; CHECK-LE-P7-NEXT: addi r3, r1, -4 156; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI2_0@toc@ha 157; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI2_0@toc@l 158; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3 159; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4 160; CHECK-LE-P7-NEXT: xxswapd v3, vs0 161; CHECK-LE-P7-NEXT: lfiwzx f0, 0, r3 162; CHECK-LE-P7-NEXT: xxspltw v4, vs0, 1 163; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3 164; CHECK-LE-P7-NEXT: blr 165; 166; CHECK-LE-P8-LABEL: test3: 167; CHECK-LE-P8: # %bb.0: # %entry 168; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha 169; CHECK-LE-P8-NEXT: xscvdpuxws v4, f1 170; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l 171; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3 172; CHECK-LE-P8-NEXT: xxswapd v3, vs0 173; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3 174; CHECK-LE-P8-NEXT: blr 175; 176; CHECK-LE-P9-LABEL: test3: 177; CHECK-LE-P9: # %bb.0: # %entry 178; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1 179; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0 180; CHECK-LE-P9-NEXT: blr 181; 182; CHECK-BE-P7-LABEL: test3: 183; CHECK-BE-P7: # %bb.0: # %entry 184; CHECK-BE-P7-NEXT: xscvdpuxws f0, f1 185; CHECK-BE-P7-NEXT: addi r3, r1, -4 186; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3 187; CHECK-BE-P7-NEXT: lfiwzx f0, 0, r3 188; CHECK-BE-P7-NEXT: addis r3, r2, .LCPI2_0@toc@ha 189; CHECK-BE-P7-NEXT: addi r3, r3, .LCPI2_0@toc@l 190; CHECK-BE-P7-NEXT: lxvw4x v4, 0, r3 191; CHECK-BE-P7-NEXT: xxspltw v3, vs0, 1 192; CHECK-BE-P7-NEXT: vperm v2, v2, v3, v4 193; CHECK-BE-P7-NEXT: blr 194; 195; CHECK-BE-P8-LABEL: test3: 196; CHECK-BE-P8: # %bb.0: # %entry 197; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha 198; CHECK-BE-P8-NEXT: xscvdpuxws v4, f1 199; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l 200; CHECK-BE-P8-NEXT: lxvw4x v3, 0, r3 201; CHECK-BE-P8-NEXT: vperm v2, v2, v4, v3 202; CHECK-BE-P8-NEXT: blr 203; 204; CHECK-BE-P9-LABEL: test3: 205; CHECK-BE-P9: # %bb.0: # %entry 206; CHECK-BE-P9-NEXT: xscvdpuxws f0, f1 207; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12 208; CHECK-BE-P9-NEXT: blr 209entry: 210 %conv = fptoui double %b to i32 211 %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3 212 ret <4 x i32> %vecins 213} 214 215define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) { 216; CHECK-LE-P7-LABEL: test4: 217; CHECK-LE-P7: # %bb.0: # %entry 218; CHECK-LE-P7-NEXT: xscvdpuxws f0, f1 219; CHECK-LE-P7-NEXT: addi r3, r1, -4 220; CHECK-LE-P7-NEXT: addis r4, r2, .LCPI3_0@toc@ha 221; CHECK-LE-P7-NEXT: addi r4, r4, .LCPI3_0@toc@l 222; CHECK-LE-P7-NEXT: stfiwx f0, 0, r3 223; CHECK-LE-P7-NEXT: lxvd2x vs0, 0, r4 224; CHECK-LE-P7-NEXT: xxswapd v3, vs0 225; CHECK-LE-P7-NEXT: lfiwzx f0, 0, r3 226; CHECK-LE-P7-NEXT: xxspltw v4, vs0, 1 227; CHECK-LE-P7-NEXT: vperm v2, v4, v2, v3 228; CHECK-LE-P7-NEXT: blr 229; 230; CHECK-LE-P8-LABEL: test4: 231; CHECK-LE-P8: # %bb.0: # %entry 232; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha 233; CHECK-LE-P8-NEXT: xscvdpuxws v4, f1 234; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l 235; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3 236; CHECK-LE-P8-NEXT: xxswapd v3, vs0 237; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3 238; CHECK-LE-P8-NEXT: blr 239; 240; CHECK-LE-P9-LABEL: test4: 241; CHECK-LE-P9: # %bb.0: # %entry 242; CHECK-LE-P9-NEXT: xscvdpuxws f0, f1 243; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 0 244; CHECK-LE-P9-NEXT: blr 245; 246; CHECK-BE-P7-LABEL: test4: 247; CHECK-BE-P7: # %bb.0: # %entry 248; CHECK-BE-P7-NEXT: xscvdpuxws f0, f1 249; CHECK-BE-P7-NEXT: addi r3, r1, -4 250; CHECK-BE-P7-NEXT: stfiwx f0, 0, r3 251; CHECK-BE-P7-NEXT: lfiwzx f0, 0, r3 252; CHECK-BE-P7-NEXT: addis r3, r2, .LCPI3_0@toc@ha 253; CHECK-BE-P7-NEXT: addi r3, r3, .LCPI3_0@toc@l 254; CHECK-BE-P7-NEXT: lxvw4x v4, 0, r3 255; CHECK-BE-P7-NEXT: xxspltw v3, vs0, 1 256; CHECK-BE-P7-NEXT: vperm v2, v2, v3, v4 257; CHECK-BE-P7-NEXT: blr 258; 259; CHECK-BE-P8-LABEL: test4: 260; CHECK-BE-P8: # %bb.0: # %entry 261; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI3_0@toc@ha 262; CHECK-BE-P8-NEXT: xscvdpuxws v4, f1 263; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI3_0@toc@l 264; CHECK-BE-P8-NEXT: lxvw4x v3, 0, r3 265; CHECK-BE-P8-NEXT: vperm v2, v2, v4, v3 266; CHECK-BE-P8-NEXT: blr 267; 268; CHECK-BE-P9-LABEL: test4: 269; CHECK-BE-P9: # %bb.0: # %entry 270; CHECK-BE-P9-NEXT: xscvdpuxws f0, f1 271; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 12 272; CHECK-BE-P9-NEXT: blr 273entry: 274 %conv = fptoui float %b to i32 275 %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3 276 ret <4 x i32> %vecins 277} 278