xref: /llvm-project/llvm/test/CodeGen/PowerPC/swap-reduction.ll (revision b922a3621116b404d868af8b74cab25ab78555be) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le < %s | FileCheck %s
3
4define i64 @test1(ptr %a, ptr %b) {
5; CHECK-LABEL: test1:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    ld 5, 0(3)
8; CHECK-NEXT:    ld 6, 0(4)
9; CHECK-NEXT:    mtvsrd 34, 5
10; CHECK-NEXT:    mtvsrd 35, 6
11; CHECK-NEXT:    add 4, 5, 6
12; CHECK-NEXT:    vavgsb 2, 2, 3
13; CHECK-NEXT:    stxsdx 34, 0, 3
14; CHECK-NEXT:    mr 3, 4
15; CHECK-NEXT:    blr
16entry:
17  %lhs = load i64, ptr %a, align 8
18  %rhs = load i64, ptr %b, align 8
19  %sum = add i64 %lhs, %rhs
20  %lv = insertelement <2 x i64> undef, i64 %lhs, i32 0
21  %rv = insertelement <2 x i64> undef, i64 %rhs, i32 0
22  %lhc = bitcast <2 x i64> %lv to <16 x i8>
23  %rhc = bitcast <2 x i64> %rv to <16 x i8>
24  %add = call <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8> %lhc, <16 x i8> %rhc)
25  %cb = bitcast <16 x i8> %add to <2 x i64>
26  %fv = extractelement <2 x i64> %cb, i32 0
27  store i64 %fv, ptr %a, align 8
28  ret i64 %sum
29}
30
31define i64 @test2(ptr %a, ptr %b) {
32; CHECK-LABEL: test2:
33; CHECK:       # %bb.0: # %entry
34; CHECK-NEXT:    ld 5, 0(3)
35; CHECK-NEXT:    ld 6, 0(4)
36; CHECK-NEXT:    mtvsrd 34, 5
37; CHECK-NEXT:    mtvsrd 35, 6
38; CHECK-NEXT:    add 4, 5, 6
39; CHECK-NEXT:    vadduhm 2, 2, 3
40; CHECK-NEXT:    stxsdx 34, 0, 3
41; CHECK-NEXT:    mr 3, 4
42; CHECK-NEXT:    blr
43entry:
44  %lhs = load i64, ptr %a, align 8
45  %rhs = load i64, ptr %b, align 8
46  %sum = add i64 %lhs, %rhs
47  %lv = insertelement <2 x i64> undef, i64 %lhs, i32 0
48  %rv = insertelement <2 x i64> undef, i64 %rhs, i32 0
49  %lhc = bitcast <2 x i64> %lv to <8 x i16>
50  %rhc = bitcast <2 x i64> %rv to <8 x i16>
51  %add = add <8 x i16> %lhc, %rhc
52  %cb = bitcast <8 x i16> %add to <2 x i64>
53  %fv = extractelement <2 x i64> %cb, i32 0
54  store i64 %fv, ptr %a, align 8
55  ret i64 %sum
56}
57
58; Ensure that vec-ops with multiple uses aren't simplified.
59define signext i16 @vecop_uses(ptr %addr) {
60; CHECK-LABEL: vecop_uses:
61; CHECK:       # %bb.0: # %entry
62; CHECK-NEXT:    li 4, 16
63; CHECK-NEXT:    lxvd2x 0, 3, 4
64; CHECK-NEXT:    xxswapd 34, 0
65; CHECK-NEXT:    lxvd2x 0, 0, 3
66; CHECK-NEXT:    xxswapd 35, 0
67; CHECK-NEXT:    vminsh 2, 3, 2
68; CHECK-NEXT:    xxswapd 35, 34
69; CHECK-NEXT:    vminsh 2, 2, 3
70; CHECK-NEXT:    xxspltw 35, 34, 2
71; CHECK-NEXT:    vminsh 2, 2, 3
72; CHECK-NEXT:    vsplth 3, 2, 6
73; CHECK-NEXT:    vminsh 2, 2, 3
74; CHECK-NEXT:    xxswapd 0, 34
75; CHECK-NEXT:    mffprd 3, 0
76; CHECK-NEXT:    clrldi 3, 3, 48
77; CHECK-NEXT:    extsh 3, 3
78; CHECK-NEXT:    blr
79entry:
80  %0 = load <16 x i16>, ptr %addr, align 2
81  %1 = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %0)
82  ret i16 %1
83}
84
85define signext i32 @vecop_uses2(ptr %a, ptr %b, ptr %c) {
86; CHECK-LABEL: vecop_uses2:
87; CHECK:       # %bb.0: # %entry
88; CHECK-NEXT:    lxvd2x 0, 0, 3
89; CHECK-NEXT:    xxswapd 34, 0
90; CHECK-NEXT:    lxvd2x 0, 0, 4
91; CHECK-NEXT:    xxswapd 35, 0
92; CHECK-NEXT:    xxsldwi 0, 34, 34, 3
93; CHECK-NEXT:    vmuluwm 2, 3, 2
94; CHECK-NEXT:    mffprwz 3, 0
95; CHECK-NEXT:    extsw 3, 3
96; CHECK-NEXT:    xxswapd 1, 34
97; CHECK-NEXT:    stxvd2x 1, 0, 5
98; CHECK-NEXT:    blr
99entry:
100  %0 = load <4 x i32>, ptr %a, align 4
101  %1 = load <4 x i32>, ptr %b, align 4
102  %2 = mul <4 x i32> %1, %0
103  store <4 x i32> %2, ptr %c, align 4
104  %3 = extractelement <4 x i32> %0, i32 3
105  ret i32 %3
106}
107
108declare <16 x i8> @llvm.ppc.altivec.vavgsb(<16 x i8>, <16 x i8>)
109declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)
110