1; RUN: llc -verify-machineinstrs -mcpu=ppc64 -O0 -frame-pointer=all -fast-isel=false < %s | FileCheck %s 2 3target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" 4target triple = "powerpc64-unknown-linux-gnu" 5 6%struct.s1 = type { i8 } 7%struct.s2 = type { i16 } 8%struct.s4 = type { i32 } 9%struct.t1 = type { i8 } 10%struct.t3 = type <{ i16, i8 }> 11%struct.t5 = type <{ i32, i8 }> 12%struct.t6 = type <{ i32, i16 }> 13%struct.t7 = type <{ i32, i16, i8 }> 14%struct.s3 = type { i16, i8 } 15%struct.s5 = type { i32, i8 } 16%struct.s6 = type { i32, i16 } 17%struct.s7 = type { i32, i16, i8 } 18%struct.t2 = type <{ i16 }> 19%struct.t4 = type <{ i32 }> 20 21@caller1.p1 = private unnamed_addr constant %struct.s1 { i8 1 }, align 1 22@caller1.p2 = private unnamed_addr constant %struct.s2 { i16 2 }, align 2 23@caller1.p3 = private unnamed_addr constant { i16, i8, i8 } { i16 4, i8 8, i8 undef }, align 2 24@caller1.p4 = private unnamed_addr constant %struct.s4 { i32 16 }, align 4 25@caller1.p5 = private unnamed_addr constant { i32, i8, [3 x i8] } { i32 32, i8 64, [3 x i8] undef }, align 4 26@caller1.p6 = private unnamed_addr constant { i32, i16, [2 x i8] } { i32 128, i16 256, [2 x i8] undef }, align 4 27@caller1.p7 = private unnamed_addr constant { i32, i16, i8, i8 } { i32 512, i16 1024, i8 -3, i8 undef }, align 4 28@caller2.p1 = private unnamed_addr constant %struct.t1 { i8 1 }, align 1 29@caller2.p2 = private unnamed_addr constant { i16 } { i16 2 }, align 1 30@caller2.p3 = private unnamed_addr constant %struct.t3 <{ i16 4, i8 8 }>, align 1 31@caller2.p4 = private unnamed_addr constant { i32 } { i32 16 }, align 1 32@caller2.p5 = private unnamed_addr constant %struct.t5 <{ i32 32, i8 64 }>, align 1 33@caller2.p6 = private unnamed_addr constant %struct.t6 <{ i32 128, i16 256 }>, align 1 34@caller2.p7 = private unnamed_addr constant %struct.t7 <{ i32 512, i16 1024, i8 -3 }>, align 1 35 36define i32 @caller1() nounwind { 37entry: 38 %p1 = alloca %struct.s1 39 %p2 = alloca %struct.s2 40 %p3 = alloca %struct.s3 41 %p4 = alloca %struct.s4 42 %p5 = alloca %struct.s5 43 %p6 = alloca %struct.s6 44 %p7 = alloca %struct.s7 45 call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr @caller1.p1, i64 1, i1 false) 46 call void @llvm.memcpy.p0.p0.i64(ptr align 2 %p2, ptr align 2 @caller1.p2, i64 2, i1 false) 47 call void @llvm.memcpy.p0.p0.i64(ptr align 2 %p3, ptr align 2 @caller1.p3, i64 4, i1 false) 48 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p4, ptr align 4 @caller1.p4, i64 4, i1 false) 49 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p5, ptr align 4 @caller1.p5, i64 8, i1 false) 50 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p6, ptr align 4 @caller1.p6, i64 8, i1 false) 51 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p7, ptr align 4 @caller1.p7, i64 8, i1 false) 52 %call = call i32 @callee1(ptr byval(%struct.s1) %p1, ptr byval(%struct.s2) %p2, ptr byval(%struct.s3) %p3, ptr byval(%struct.s4) %p4, ptr byval(%struct.s5) %p5, ptr byval(%struct.s6) %p6, ptr byval(%struct.s7) %p7) 53 ret i32 %call 54 55; CHECK-LABEL: caller1 56; CHECK: ld 9, 112(31) 57; CHECK: ld 8, 120(31) 58; CHECK: ld 7, 128(31) 59; CHECK: lwz 6, 136(31) 60; CHECK: lwz 5, 144(31) 61; CHECK: lhz 4, 152(31) 62; CHECK: lbz 3, 160(31) 63} 64 65declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind 66 67define internal i32 @callee1(ptr byval(%struct.s1) %v1, ptr byval(%struct.s2) %v2, ptr byval(%struct.s3) %v3, ptr byval(%struct.s4) %v4, ptr byval(%struct.s5) %v5, ptr byval(%struct.s6) %v6, ptr byval(%struct.s7) %v7) nounwind { 68entry: 69 %0 = load i8, ptr %v1, align 1 70 %conv = zext i8 %0 to i32 71 %1 = load i16, ptr %v2, align 2 72 %conv2 = sext i16 %1 to i32 73 %add = add nsw i32 %conv, %conv2 74 %2 = load i16, ptr %v3, align 2 75 %conv4 = sext i16 %2 to i32 76 %add5 = add nsw i32 %add, %conv4 77 %3 = load i32, ptr %v4, align 4 78 %add7 = add nsw i32 %add5, %3 79 %4 = load i32, ptr %v5, align 4 80 %add9 = add nsw i32 %add7, %4 81 %5 = load i32, ptr %v6, align 4 82 %add11 = add nsw i32 %add9, %5 83 %6 = load i32, ptr %v7, align 4 84 %add13 = add nsw i32 %add11, %6 85 ret i32 %add13 86 87; CHECK-LABEL: callee1 88; CHECK-DAG: std 9, 96(1) 89; CHECK-DAG: std 8, 88(1) 90; CHECK-DAG: std 7, 80(1) 91; CHECK-DAG: stw 6, 76(1) 92; CHECK-DAG: stw 5, 68(1) 93; CHECK-DAG: sth 4, 62(1) 94; CHECK-DAG: stb 3, 55(1) 95; CHECK-DAG: lha {{[0-9]+}}, 62(1) 96; CHECK-DAG: lha {{[0-9]+}}, 68(1) 97; CHECK-DAG: lbz {{[0-9]+}}, 55(1) 98; CHECK-DAG: lwz {{[0-9]+}}, 76(1) 99; CHECK-DAG: lwz {{[0-9]+}}, 80(1) 100; CHECK-DAG: lwz {{[0-9]+}}, 88(1) 101; CHECK-DAG: lwz {{[0-9]+}}, 96(1) 102} 103 104define i32 @caller2() nounwind { 105entry: 106 %p1 = alloca %struct.t1 107 %p2 = alloca %struct.t2 108 %p3 = alloca %struct.t3 109 %p4 = alloca %struct.t4 110 %p5 = alloca %struct.t5 111 %p6 = alloca %struct.t6 112 %p7 = alloca %struct.t7 113 call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr @caller2.p1, i64 1, i1 false) 114 call void @llvm.memcpy.p0.p0.i64(ptr %p2, ptr @caller2.p2, i64 2, i1 false) 115 call void @llvm.memcpy.p0.p0.i64(ptr %p3, ptr @caller2.p3, i64 3, i1 false) 116 call void @llvm.memcpy.p0.p0.i64(ptr %p4, ptr @caller2.p4, i64 4, i1 false) 117 call void @llvm.memcpy.p0.p0.i64(ptr %p5, ptr @caller2.p5, i64 5, i1 false) 118 call void @llvm.memcpy.p0.p0.i64(ptr %p6, ptr @caller2.p6, i64 6, i1 false) 119 call void @llvm.memcpy.p0.p0.i64(ptr %p7, ptr @caller2.p7, i64 7, i1 false) 120 %call = call i32 @callee2(ptr byval(%struct.t1) %p1, ptr byval(%struct.t2) %p2, ptr byval(%struct.t3) %p3, ptr byval(%struct.t4) %p4, ptr byval(%struct.t5) %p5, ptr byval(%struct.t6) %p6, ptr byval(%struct.t7) %p7) 121 ret i32 %call 122 123; CHECK-LABEL: caller2 124; CHECK: stb {{[0-9]+}}, 71(1) 125; CHECK: sth {{[0-9]+}}, 69(1) 126; CHECK: stb {{[0-9]+}}, 87(1) 127; CHECK: stw {{[0-9]+}}, 83(1) 128; CHECK: sth {{[0-9]+}}, 94(1) 129; CHECK: stw {{[0-9]+}}, 90(1) 130; CHECK: stw {{[0-9]+}}, 100(1) 131; CHECK: stw {{[0-9]+}}, 97(1) 132; CHECK: ld 9, 96(1) 133; CHECK: ld 8, 88(1) 134; CHECK: ld 7, 80(1) 135; CHECK: lwz 6, 136(31) 136; CHECK: ld 5, 64(1) 137; CHECK: lhz 4, 152(31) 138; CHECK: lbz 3, 160(31) 139} 140 141define internal i32 @callee2(ptr byval(%struct.t1) %v1, ptr byval(%struct.t2) %v2, ptr byval(%struct.t3) %v3, ptr byval(%struct.t4) %v4, ptr byval(%struct.t5) %v5, ptr byval(%struct.t6) %v6, ptr byval(%struct.t7) %v7) nounwind { 142entry: 143 %0 = load i8, ptr %v1, align 1 144 %conv = zext i8 %0 to i32 145 %1 = load i16, ptr %v2, align 1 146 %conv2 = sext i16 %1 to i32 147 %add = add nsw i32 %conv, %conv2 148 %2 = load i16, ptr %v3, align 1 149 %conv4 = sext i16 %2 to i32 150 %add5 = add nsw i32 %add, %conv4 151 %3 = load i32, ptr %v4, align 1 152 %add7 = add nsw i32 %add5, %3 153 %4 = load i32, ptr %v5, align 1 154 %add9 = add nsw i32 %add7, %4 155 %5 = load i32, ptr %v6, align 1 156 %add11 = add nsw i32 %add9, %5 157 %6 = load i32, ptr %v7, align 1 158 %add13 = add nsw i32 %add11, %6 159 ret i32 %add13 160 161; CHECK-LABEL: callee2 162; CHECK: stb 9, 103(1) 163; CHECK: rldicl 10, 9, 56, 8 164; CHECK: sth 10, 101(1) 165; CHECK: rldicl 9, 9, 40, 24 166; CHECK: stw 9, 97(1) 167; CHECK: sth 8, 94(1) 168; CHECK: rldicl 8, 8, 48, 16 169; CHECK: stw 8, 90(1) 170; CHECK: stb 7, 87(1) 171; CHECK: rldicl 7, 7, 56, 8 172; CHECK: stw 7, 83(1) 173; CHECK: stb 5, 71(1) 174; CHECK: rldicl 5, 5, 56, 8 175; CHECK: sth 5, 69(1) 176; CHECK: stw 6, 76(1) 177; CHECK: sth 4, 62(1) 178; CHECK: stb 3, 55(1) 179; CHECK-DAG: lha {{[0-9]+}}, 62(1) 180; CHECK-DAG: lha {{[0-9]+}}, 69(1) 181; CHECK-DAG: lbz {{[0-9]+}}, 55(1) 182; CHECK-DAG: lwz {{[0-9]+}}, 76(1) 183; CHECK-DAG: lwz {{[0-9]+}}, 83(1) 184; CHECK-DAG: lwz {{[0-9]+}}, 90(1) 185; CHECK-DAG: lwz {{[0-9]+}}, 97(1) 186} 187