1; RUN: llc -verify-machineinstrs -mcpu=ppc64 -O0 -frame-pointer=all -fast-isel=false < %s | FileCheck %s 2 3target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" 4target triple = "powerpc64-unknown-linux-gnu" 5 6%struct.s1 = type { i8 } 7%struct.s2 = type { i16 } 8%struct.s4 = type { i32 } 9%struct.t1 = type { i8 } 10%struct.t3 = type <{ i16, i8 }> 11%struct.t5 = type <{ i32, i8 }> 12%struct.t6 = type <{ i32, i16 }> 13%struct.t7 = type <{ i32, i16, i8 }> 14%struct.s3 = type { i16, i8 } 15%struct.s5 = type { i32, i8 } 16%struct.s6 = type { i32, i16 } 17%struct.s7 = type { i32, i16, i8 } 18%struct.t2 = type <{ i16 }> 19%struct.t4 = type <{ i32 }> 20 21@caller1.p1 = private unnamed_addr constant %struct.s1 { i8 1 }, align 1 22@caller1.p2 = private unnamed_addr constant %struct.s2 { i16 2 }, align 2 23@caller1.p3 = private unnamed_addr constant { i16, i8, i8 } { i16 4, i8 8, i8 undef }, align 2 24@caller1.p4 = private unnamed_addr constant %struct.s4 { i32 16 }, align 4 25@caller1.p5 = private unnamed_addr constant { i32, i8, [3 x i8] } { i32 32, i8 64, [3 x i8] undef }, align 4 26@caller1.p6 = private unnamed_addr constant { i32, i16, [2 x i8] } { i32 128, i16 256, [2 x i8] undef }, align 4 27@caller1.p7 = private unnamed_addr constant { i32, i16, i8, i8 } { i32 512, i16 1024, i8 -3, i8 undef }, align 4 28@caller2.p1 = private unnamed_addr constant %struct.t1 { i8 1 }, align 1 29@caller2.p2 = private unnamed_addr constant { i16 } { i16 2 }, align 1 30@caller2.p3 = private unnamed_addr constant %struct.t3 <{ i16 4, i8 8 }>, align 1 31@caller2.p4 = private unnamed_addr constant { i32 } { i32 16 }, align 1 32@caller2.p5 = private unnamed_addr constant %struct.t5 <{ i32 32, i8 64 }>, align 1 33@caller2.p6 = private unnamed_addr constant %struct.t6 <{ i32 128, i16 256 }>, align 1 34@caller2.p7 = private unnamed_addr constant %struct.t7 <{ i32 512, i16 1024, i8 -3 }>, align 1 35 36define i32 @caller1() nounwind { 37entry: 38 %p1 = alloca %struct.s1, align 1 39 %p2 = alloca %struct.s2, align 2 40 %p3 = alloca %struct.s3, align 2 41 %p4 = alloca %struct.s4, align 4 42 %p5 = alloca %struct.s5, align 4 43 %p6 = alloca %struct.s6, align 4 44 %p7 = alloca %struct.s7, align 4 45 call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr @caller1.p1, i64 1, i1 false) 46 call void @llvm.memcpy.p0.p0.i64(ptr align 2 %p2, ptr align 2 @caller1.p2, i64 2, i1 false) 47 call void @llvm.memcpy.p0.p0.i64(ptr align 2 %p3, ptr align 2 @caller1.p3, i64 4, i1 false) 48 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p4, ptr align 4 @caller1.p4, i64 4, i1 false) 49 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p5, ptr align 4 @caller1.p5, i64 8, i1 false) 50 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p6, ptr align 4 @caller1.p6, i64 8, i1 false) 51 call void @llvm.memcpy.p0.p0.i64(ptr align 4 %p7, ptr align 4 @caller1.p7, i64 8, i1 false) 52 %call = call i32 @callee1(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, ptr byval(%struct.s1) %p1, ptr byval(%struct.s2) %p2, ptr byval(%struct.s3) %p3, ptr byval(%struct.s4) %p4, ptr byval(%struct.s5) %p5, ptr byval(%struct.s6) %p6, ptr byval(%struct.s7) %p7) 53 ret i32 %call 54 55; CHECK: stb {{[0-9]+}}, 119(1) 56; CHECK: sth {{[0-9]+}}, 126(1) 57; CHECK: stw {{[0-9]+}}, 132(1) 58; CHECK: stw {{[0-9]+}}, 140(1) 59; CHECK: std {{[0-9]+}}, 144(1) 60; CHECK: std {{[0-9]+}}, 152(1) 61; CHECK: std {{[0-9]+}}, 160(1) 62} 63 64declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind 65 66define internal i32 @callee1(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, ptr byval(%struct.s1) %v1, ptr byval(%struct.s2) %v2, ptr byval(%struct.s3) %v3, ptr byval(%struct.s4) %v4, ptr byval(%struct.s5) %v5, ptr byval(%struct.s6) %v6, ptr byval(%struct.s7) %v7) nounwind { 67entry: 68 %z1.addr = alloca i32, align 4 69 %z2.addr = alloca i32, align 4 70 %z3.addr = alloca i32, align 4 71 %z4.addr = alloca i32, align 4 72 %z5.addr = alloca i32, align 4 73 %z6.addr = alloca i32, align 4 74 %z7.addr = alloca i32, align 4 75 %z8.addr = alloca i32, align 4 76 store i32 %z1, ptr %z1.addr, align 4 77 store i32 %z2, ptr %z2.addr, align 4 78 store i32 %z3, ptr %z3.addr, align 4 79 store i32 %z4, ptr %z4.addr, align 4 80 store i32 %z5, ptr %z5.addr, align 4 81 store i32 %z6, ptr %z6.addr, align 4 82 store i32 %z7, ptr %z7.addr, align 4 83 store i32 %z8, ptr %z8.addr, align 4 84 %0 = load i8, ptr %v1, align 1 85 %conv = zext i8 %0 to i32 86 %1 = load i16, ptr %v2, align 2 87 %conv2 = sext i16 %1 to i32 88 %add = add nsw i32 %conv, %conv2 89 %2 = load i16, ptr %v3, align 2 90 %conv4 = sext i16 %2 to i32 91 %add5 = add nsw i32 %add, %conv4 92 %3 = load i32, ptr %v4, align 4 93 %add7 = add nsw i32 %add5, %3 94 %4 = load i32, ptr %v5, align 4 95 %add9 = add nsw i32 %add7, %4 96 %5 = load i32, ptr %v6, align 4 97 %add11 = add nsw i32 %add9, %5 98 %6 = load i32, ptr %v7, align 4 99 %add13 = add nsw i32 %add11, %6 100 ret i32 %add13 101 102; CHECK-DAG: lha {{[0-9]+}}, 126(1) 103; CHECK-DAG: lha {{[0-9]+}}, 132(1) 104; CHECK-DAG: lbz {{[0-9]+}}, 119(1) 105; CHECK-DAG: lwz {{[0-9]+}}, 140(1) 106; CHECK-DAG: lwz {{[0-9]+}}, 144(1) 107; CHECK-DAG: lwz {{[0-9]+}}, 152(1) 108; CHECK-DAG: lwz {{[0-9]+}}, 160(1) 109} 110 111define i32 @caller2() nounwind { 112entry: 113 %p1 = alloca %struct.t1, align 1 114 %p2 = alloca %struct.t2, align 1 115 %p3 = alloca %struct.t3, align 1 116 %p4 = alloca %struct.t4, align 1 117 %p5 = alloca %struct.t5, align 1 118 %p6 = alloca %struct.t6, align 1 119 %p7 = alloca %struct.t7, align 1 120 call void @llvm.memcpy.p0.p0.i64(ptr %p1, ptr @caller2.p1, i64 1, i1 false) 121 call void @llvm.memcpy.p0.p0.i64(ptr %p2, ptr @caller2.p2, i64 2, i1 false) 122 call void @llvm.memcpy.p0.p0.i64(ptr %p3, ptr @caller2.p3, i64 3, i1 false) 123 call void @llvm.memcpy.p0.p0.i64(ptr %p4, ptr @caller2.p4, i64 4, i1 false) 124 call void @llvm.memcpy.p0.p0.i64(ptr %p5, ptr @caller2.p5, i64 5, i1 false) 125 call void @llvm.memcpy.p0.p0.i64(ptr %p6, ptr @caller2.p6, i64 6, i1 false) 126 call void @llvm.memcpy.p0.p0.i64(ptr %p7, ptr @caller2.p7, i64 7, i1 false) 127 %call = call i32 @callee2(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, ptr byval(%struct.t1) %p1, ptr byval(%struct.t2) %p2, ptr byval(%struct.t3) %p3, ptr byval(%struct.t4) %p4, ptr byval(%struct.t5) %p5, ptr byval(%struct.t6) %p6, ptr byval(%struct.t7) %p7) 128 ret i32 %call 129 130; CHECK: stb {{[0-9]+}}, 119(1) 131; CHECK: sth {{[0-9]+}}, 126(1) 132; CHECK: stb {{[0-9]+}}, 135(1) 133; CHECK: sth {{[0-9]+}}, 133(1) 134; CHECK: stw {{[0-9]+}}, 140(1) 135; CHECK: stb {{[0-9]+}}, 151(1) 136; CHECK: stw {{[0-9]+}}, 147(1) 137; CHECK: sth {{[0-9]+}}, 158(1) 138; CHECK: stw {{[0-9]+}}, 154(1) 139; CHECK: stw {{[0-9]+}}, 164(1) 140; CHECK: stw {{[0-9]+}}, 161(1) 141} 142 143define internal i32 @callee2(i32 %z1, i32 %z2, i32 %z3, i32 %z4, i32 %z5, i32 %z6, i32 %z7, i32 %z8, ptr byval(%struct.t1) %v1, ptr byval(%struct.t2) %v2, ptr byval(%struct.t3) %v3, ptr byval(%struct.t4) %v4, ptr byval(%struct.t5) %v5, ptr byval(%struct.t6) %v6, ptr byval(%struct.t7) %v7) nounwind { 144entry: 145 %z1.addr = alloca i32, align 4 146 %z2.addr = alloca i32, align 4 147 %z3.addr = alloca i32, align 4 148 %z4.addr = alloca i32, align 4 149 %z5.addr = alloca i32, align 4 150 %z6.addr = alloca i32, align 4 151 %z7.addr = alloca i32, align 4 152 %z8.addr = alloca i32, align 4 153 store i32 %z1, ptr %z1.addr, align 4 154 store i32 %z2, ptr %z2.addr, align 4 155 store i32 %z3, ptr %z3.addr, align 4 156 store i32 %z4, ptr %z4.addr, align 4 157 store i32 %z5, ptr %z5.addr, align 4 158 store i32 %z6, ptr %z6.addr, align 4 159 store i32 %z7, ptr %z7.addr, align 4 160 store i32 %z8, ptr %z8.addr, align 4 161 %0 = load i8, ptr %v1, align 1 162 %conv = zext i8 %0 to i32 163 %1 = load i16, ptr %v2, align 1 164 %conv2 = sext i16 %1 to i32 165 %add = add nsw i32 %conv, %conv2 166 %2 = load i16, ptr %v3, align 1 167 %conv4 = sext i16 %2 to i32 168 %add5 = add nsw i32 %add, %conv4 169 %3 = load i32, ptr %v4, align 1 170 %add7 = add nsw i32 %add5, %3 171 %4 = load i32, ptr %v5, align 1 172 %add9 = add nsw i32 %add7, %4 173 %5 = load i32, ptr %v6, align 1 174 %add11 = add nsw i32 %add9, %5 175 %6 = load i32, ptr %v7, align 1 176 %add13 = add nsw i32 %add11, %6 177 ret i32 %add13 178 179; CHECK-DAG: lha {{[0-9]+}}, 126(1) 180; CHECK-DAG: lha {{[0-9]+}}, 133(1) 181; CHECK-DAG: lbz {{[0-9]+}}, 119(1) 182; CHECK-DAG: lwz {{[0-9]+}}, 140(1) 183; CHECK-DAG: lwz {{[0-9]+}}, 147(1) 184; CHECK-DAG: lwz {{[0-9]+}}, 154(1) 185; CHECK-DAG: lwz {{[0-9]+}}, 161(1) 186} 187