1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \ 3; RUN: -mattr=+spe | FileCheck %s -check-prefixes=CHECK,SPE 4; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \ 5; RUN: -mattr=+efpu2 | FileCheck %s -check-prefixes=CHECK,EFPU2 6 7; single tests (identical for -mattr=+spe and -mattr=+efpu2) 8 9declare float @llvm.fabs.float(float) 10define float @test_float_abs(float %a) #0 { 11; CHECK-LABEL: test_float_abs: 12; CHECK: # %bb.0: # %entry 13; CHECK-NEXT: efsabs 3, 3 14; CHECK-NEXT: blr 15 entry: 16 %0 = tail call float @llvm.fabs.float(float %a) 17 ret float %0 18} 19 20define float @test_fnabs(float %a) #0 { 21; CHECK-LABEL: test_fnabs: 22; CHECK: # %bb.0: # %entry 23; CHECK-NEXT: efsnabs 3, 3 24; CHECK-NEXT: blr 25 entry: 26 %0 = tail call float @llvm.fabs.float(float %a) 27 %sub = fsub float -0.000000e+00, %0 28 ret float %sub 29} 30 31define float @test_fdiv(float %a, float %b) #0 { 32; CHECK-LABEL: test_fdiv: 33; CHECK: # %bb.0: # %entry 34; CHECK-NEXT: efsdiv 3, 3, 4 35; CHECK-NEXT: blr 36entry: 37 %v = fdiv float %a, %b 38 ret float %v 39 40} 41 42define float @test_fmul(float %a, float %b) #0 { 43; CHECK-LABEL: test_fmul: 44; CHECK: # %bb.0: # %entry 45; CHECK-NEXT: efsmul 3, 3, 4 46; CHECK-NEXT: blr 47 entry: 48 %v = fmul float %a, %b 49 ret float %v 50} 51 52define float @test_fadd(float %a, float %b) #0 { 53; CHECK-LABEL: test_fadd: 54; CHECK: # %bb.0: # %entry 55; CHECK-NEXT: efsadd 3, 3, 4 56; CHECK-NEXT: blr 57 entry: 58 %v = fadd float %a, %b 59 ret float %v 60} 61 62define float @test_fsub(float %a, float %b) #0 { 63; CHECK-LABEL: test_fsub: 64; CHECK: # %bb.0: # %entry 65; CHECK-NEXT: efssub 3, 3, 4 66; CHECK-NEXT: blr 67 entry: 68 %v = fsub float %a, %b 69 ret float %v 70} 71 72define float @test_fneg(float %a) #0 { 73; CHECK-LABEL: test_fneg: 74; CHECK: # %bb.0: # %entry 75; CHECK-NEXT: efsneg 3, 3 76; CHECK-NEXT: blr 77 entry: 78 %v = fsub float -0.0, %a 79 ret float %v 80} 81 82define i32 @test_fcmpgt(float %a, float %b) #0 { 83; CHECK-LABEL: test_fcmpgt: 84; CHECK: # %bb.0: # %entry 85; CHECK-NEXT: stwu 1, -16(1) 86; CHECK-NEXT: efscmpgt 0, 3, 4 87; CHECK-NEXT: ble 0, .LBB7_2 88; CHECK-NEXT: # %bb.1: # %tr 89; CHECK-NEXT: li 3, 1 90; CHECK-NEXT: b .LBB7_3 91; CHECK-NEXT: .LBB7_2: # %fa 92; CHECK-NEXT: li 3, 0 93; CHECK-NEXT: .LBB7_3: # %ret 94; CHECK-NEXT: stw 3, 12(1) 95; CHECK-NEXT: lwz 3, 12(1) 96; CHECK-NEXT: addi 1, 1, 16 97; CHECK-NEXT: blr 98 entry: 99 %r = alloca i32, align 4 100 %c = fcmp ogt float %a, %b 101 br i1 %c, label %tr, label %fa 102tr: 103 store i32 1, ptr %r, align 4 104 br label %ret 105fa: 106 store i32 0, ptr %r, align 4 107 br label %ret 108ret: 109 %0 = load i32, ptr %r, align 4 110 ret i32 %0 111} 112 113define i32 @test_fcmpugt(float %a, float %b) #0 { 114; CHECK-LABEL: test_fcmpugt: 115; CHECK: # %bb.0: # %entry 116; CHECK-NEXT: stwu 1, -16(1) 117; CHECK-NEXT: efscmpeq 0, 4, 4 118; CHECK-NEXT: bc 4, 1, .LBB8_4 119; CHECK-NEXT: # %bb.1: # %entry 120; CHECK-NEXT: efscmpeq 0, 3, 3 121; CHECK-NEXT: bc 4, 1, .LBB8_4 122; CHECK-NEXT: # %bb.2: # %entry 123; CHECK-NEXT: efscmpgt 0, 3, 4 124; CHECK-NEXT: bc 12, 1, .LBB8_4 125; CHECK-NEXT: # %bb.3: # %fa 126; CHECK-NEXT: li 3, 0 127; CHECK-NEXT: b .LBB8_5 128; CHECK-NEXT: .LBB8_4: # %tr 129; CHECK-NEXT: li 3, 1 130; CHECK-NEXT: .LBB8_5: # %ret 131; CHECK-NEXT: stw 3, 12(1) 132; CHECK-NEXT: lwz 3, 12(1) 133; CHECK-NEXT: addi 1, 1, 16 134; CHECK-NEXT: blr 135 entry: 136 %r = alloca i32, align 4 137 %c = fcmp ugt float %a, %b 138 br i1 %c, label %tr, label %fa 139tr: 140 store i32 1, ptr %r, align 4 141 br label %ret 142fa: 143 store i32 0, ptr %r, align 4 144 br label %ret 145ret: 146 %0 = load i32, ptr %r, align 4 147 ret i32 %0 148} 149 150define i32 @test_fcmple(float %a, float %b) #0 { 151; CHECK-LABEL: test_fcmple: 152; CHECK: # %bb.0: # %entry 153; CHECK-NEXT: stwu 1, -16(1) 154; CHECK-NEXT: efscmpeq 0, 3, 3 155; CHECK-NEXT: bc 4, 1, .LBB9_4 156; CHECK-NEXT: # %bb.1: # %entry 157; CHECK-NEXT: efscmpeq 0, 4, 4 158; CHECK-NEXT: bc 4, 1, .LBB9_4 159; CHECK-NEXT: # %bb.2: # %entry 160; CHECK-NEXT: efscmpgt 0, 3, 4 161; CHECK-NEXT: bc 12, 1, .LBB9_4 162; CHECK-NEXT: # %bb.3: # %tr 163; CHECK-NEXT: li 3, 1 164; CHECK-NEXT: b .LBB9_5 165; CHECK-NEXT: .LBB9_4: # %fa 166; CHECK-NEXT: li 3, 0 167; CHECK-NEXT: .LBB9_5: # %ret 168; CHECK-NEXT: stw 3, 12(1) 169; CHECK-NEXT: lwz 3, 12(1) 170; CHECK-NEXT: addi 1, 1, 16 171; CHECK-NEXT: blr 172 entry: 173 %r = alloca i32, align 4 174 %c = fcmp ole float %a, %b 175 br i1 %c, label %tr, label %fa 176tr: 177 store i32 1, ptr %r, align 4 178 br label %ret 179fa: 180 store i32 0, ptr %r, align 4 181 br label %ret 182ret: 183 %0 = load i32, ptr %r, align 4 184 ret i32 %0 185} 186 187define i32 @test_fcmpule(float %a, float %b) #0 { 188; CHECK-LABEL: test_fcmpule: 189; CHECK: # %bb.0: # %entry 190; CHECK-NEXT: stwu 1, -16(1) 191; CHECK-NEXT: efscmpgt 0, 3, 4 192; CHECK-NEXT: bgt 0, .LBB10_2 193; CHECK-NEXT: # %bb.1: # %tr 194; CHECK-NEXT: li 3, 1 195; CHECK-NEXT: b .LBB10_3 196; CHECK-NEXT: .LBB10_2: # %fa 197; CHECK-NEXT: li 3, 0 198; CHECK-NEXT: .LBB10_3: # %ret 199; CHECK-NEXT: stw 3, 12(1) 200; CHECK-NEXT: lwz 3, 12(1) 201; CHECK-NEXT: addi 1, 1, 16 202; CHECK-NEXT: blr 203 entry: 204 %r = alloca i32, align 4 205 %c = fcmp ule float %a, %b 206 br i1 %c, label %tr, label %fa 207tr: 208 store i32 1, ptr %r, align 4 209 br label %ret 210fa: 211 store i32 0, ptr %r, align 4 212 br label %ret 213ret: 214 %0 = load i32, ptr %r, align 4 215 ret i32 %0 216} 217 218; The type of comparison found in C's if (x == y) 219define i32 @test_fcmpeq(float %a, float %b) #0 { 220; CHECK-LABEL: test_fcmpeq: 221; CHECK: # %bb.0: # %entry 222; CHECK-NEXT: stwu 1, -16(1) 223; CHECK-NEXT: efscmpeq 0, 3, 4 224; CHECK-NEXT: ble 0, .LBB11_2 225; CHECK-NEXT: # %bb.1: # %tr 226; CHECK-NEXT: li 3, 1 227; CHECK-NEXT: b .LBB11_3 228; CHECK-NEXT: .LBB11_2: # %fa 229; CHECK-NEXT: li 3, 0 230; CHECK-NEXT: .LBB11_3: # %ret 231; CHECK-NEXT: stw 3, 12(1) 232; CHECK-NEXT: lwz 3, 12(1) 233; CHECK-NEXT: addi 1, 1, 16 234; CHECK-NEXT: blr 235 entry: 236 %r = alloca i32, align 4 237 %c = fcmp oeq float %a, %b 238 br i1 %c, label %tr, label %fa 239tr: 240 store i32 1, ptr %r, align 4 241 br label %ret 242fa: 243 store i32 0, ptr %r, align 4 244 br label %ret 245ret: 246 %0 = load i32, ptr %r, align 4 247 ret i32 %0 248} 249 250; (un)ordered tests are expanded to une and oeq so verify 251define i1 @test_fcmpuno(float %a, float %b) #0 { 252; CHECK-LABEL: test_fcmpuno: 253; CHECK: # %bb.0: # %entry 254; CHECK-NEXT: efscmpeq 0, 3, 3 255; CHECK-NEXT: li 3, 0 256; CHECK-NEXT: bc 4, 1, .LBB12_2 257; CHECK-NEXT: # %bb.1: # %entry 258; CHECK-NEXT: efscmpeq 0, 4, 4 259; CHECK-NEXT: bclr 12, 1, 0 260; CHECK-NEXT: .LBB12_2: # %entry 261; CHECK-NEXT: li 3, 1 262; CHECK-NEXT: blr 263 entry: 264 %r = fcmp uno float %a, %b 265 ret i1 %r 266} 267 268define i1 @test_fcmpord(float %a, float %b) #0 { 269; CHECK-LABEL: test_fcmpord: 270; CHECK: # %bb.0: # %entry 271; CHECK-NEXT: mr 5, 3 272; CHECK-NEXT: efscmpeq 0, 4, 4 273; CHECK-NEXT: li 3, 0 274; CHECK-NEXT: bclr 4, 1, 0 275; CHECK-NEXT: # %bb.1: # %entry 276; CHECK-NEXT: efscmpeq 0, 5, 5 277; CHECK-NEXT: bclr 4, 1, 0 278; CHECK-NEXT: # %bb.2: # %entry 279; CHECK-NEXT: li 3, 1 280; CHECK-NEXT: blr 281 entry: 282 %r = fcmp ord float %a, %b 283 ret i1 %r 284} 285 286define i1 @test_fcmpueq(float %a, float %b) #0 { 287; CHECK-LABEL: test_fcmpueq: 288; CHECK: # %bb.0: # %entry 289; CHECK-NEXT: mr 5, 3 290; CHECK-NEXT: efscmpgt 0, 3, 4 291; CHECK-NEXT: li 3, 0 292; CHECK-NEXT: bclr 12, 1, 0 293; CHECK-NEXT: # %bb.1: # %entry 294; CHECK-NEXT: efscmplt 0, 5, 4 295; CHECK-NEXT: bclr 12, 1, 0 296; CHECK-NEXT: # %bb.2: # %entry 297; CHECK-NEXT: li 3, 1 298; CHECK-NEXT: blr 299 entry: 300 %r = fcmp ueq float %a, %b 301 ret i1 %r 302} 303 304define i1 @test_fcmpne(float %a, float %b) #0 { 305; CHECK-LABEL: test_fcmpne: 306; CHECK: # %bb.0: # %entry 307; CHECK-NEXT: mr 5, 3 308; CHECK-NEXT: efscmplt 0, 3, 4 309; CHECK-NEXT: li 3, 0 310; CHECK-NEXT: bc 12, 1, .LBB15_2 311; CHECK-NEXT: # %bb.1: # %entry 312; CHECK-NEXT: efscmpgt 0, 5, 4 313; CHECK-NEXT: bclr 4, 1, 0 314; CHECK-NEXT: .LBB15_2: # %entry 315; CHECK-NEXT: li 3, 1 316; CHECK-NEXT: blr 317 entry: 318 %r = fcmp one float %a, %b 319 ret i1 %r 320} 321 322define i32 @test_fcmpune(float %a, float %b) #0 { 323; CHECK-LABEL: test_fcmpune: 324; CHECK: # %bb.0: # %entry 325; CHECK-NEXT: stwu 1, -16(1) 326; CHECK-NEXT: efscmpeq 0, 3, 4 327; CHECK-NEXT: bgt 0, .LBB16_2 328; CHECK-NEXT: # %bb.1: # %tr 329; CHECK-NEXT: li 3, 1 330; CHECK-NEXT: b .LBB16_3 331; CHECK-NEXT: .LBB16_2: # %fa 332; CHECK-NEXT: li 3, 0 333; CHECK-NEXT: .LBB16_3: # %ret 334; CHECK-NEXT: stw 3, 12(1) 335; CHECK-NEXT: lwz 3, 12(1) 336; CHECK-NEXT: addi 1, 1, 16 337; CHECK-NEXT: blr 338 entry: 339 %r = alloca i32, align 4 340 %c = fcmp une float %a, %b 341 br i1 %c, label %tr, label %fa 342tr: 343 store i32 1, ptr %r, align 4 344 br label %ret 345fa: 346 store i32 0, ptr %r, align 4 347 br label %ret 348ret: 349 %0 = load i32, ptr %r, align 4 350 ret i32 %0 351} 352 353define i32 @test_fcmplt(float %a, float %b) #0 { 354; CHECK-LABEL: test_fcmplt: 355; CHECK: # %bb.0: # %entry 356; CHECK-NEXT: stwu 1, -16(1) 357; CHECK-NEXT: efscmplt 0, 3, 4 358; CHECK-NEXT: ble 0, .LBB17_2 359; CHECK-NEXT: # %bb.1: # %tr 360; CHECK-NEXT: li 3, 1 361; CHECK-NEXT: b .LBB17_3 362; CHECK-NEXT: .LBB17_2: # %fa 363; CHECK-NEXT: li 3, 0 364; CHECK-NEXT: .LBB17_3: # %ret 365; CHECK-NEXT: stw 3, 12(1) 366; CHECK-NEXT: lwz 3, 12(1) 367; CHECK-NEXT: addi 1, 1, 16 368; CHECK-NEXT: blr 369 entry: 370 %r = alloca i32, align 4 371 %c = fcmp olt float %a, %b 372 br i1 %c, label %tr, label %fa 373tr: 374 store i32 1, ptr %r, align 4 375 br label %ret 376fa: 377 store i32 0, ptr %r, align 4 378 br label %ret 379ret: 380 %0 = load i32, ptr %r, align 4 381 ret i32 %0 382} 383 384define i1 @test_fcmpult(float %a, float %b) #0 { 385; CHECK-LABEL: test_fcmpult: 386; CHECK: # %bb.0: # %entry 387; CHECK-NEXT: mr 5, 3 388; CHECK-NEXT: efscmpeq 0, 3, 3 389; CHECK-NEXT: li 3, 0 390; CHECK-NEXT: bc 4, 1, .LBB18_3 391; CHECK-NEXT: # %bb.1: # %entry 392; CHECK-NEXT: efscmpeq 0, 4, 4 393; CHECK-NEXT: bc 4, 1, .LBB18_3 394; CHECK-NEXT: # %bb.2: # %entry 395; CHECK-NEXT: efscmplt 0, 5, 4 396; CHECK-NEXT: bclr 4, 1, 0 397; CHECK-NEXT: .LBB18_3: # %entry 398; CHECK-NEXT: li 3, 1 399; CHECK-NEXT: blr 400 entry: 401 %r = fcmp ult float %a, %b 402 ret i1 %r 403} 404 405define i32 @test_fcmpge(float %a, float %b) #0 { 406; CHECK-LABEL: test_fcmpge: 407; CHECK: # %bb.0: # %entry 408; CHECK-NEXT: stwu 1, -16(1) 409; CHECK-NEXT: efscmpeq 0, 3, 3 410; CHECK-NEXT: bc 4, 1, .LBB19_4 411; CHECK-NEXT: # %bb.1: # %entry 412; CHECK-NEXT: efscmpeq 0, 4, 4 413; CHECK-NEXT: bc 4, 1, .LBB19_4 414; CHECK-NEXT: # %bb.2: # %entry 415; CHECK-NEXT: efscmplt 0, 3, 4 416; CHECK-NEXT: bc 12, 1, .LBB19_4 417; CHECK-NEXT: # %bb.3: # %tr 418; CHECK-NEXT: li 3, 1 419; CHECK-NEXT: b .LBB19_5 420; CHECK-NEXT: .LBB19_4: # %fa 421; CHECK-NEXT: li 3, 0 422; CHECK-NEXT: .LBB19_5: # %ret 423; CHECK-NEXT: stw 3, 12(1) 424; CHECK-NEXT: lwz 3, 12(1) 425; CHECK-NEXT: addi 1, 1, 16 426; CHECK-NEXT: blr 427 entry: 428 %r = alloca i32, align 4 429 %c = fcmp oge float %a, %b 430 br i1 %c, label %tr, label %fa 431tr: 432 store i32 1, ptr %r, align 4 433 br label %ret 434fa: 435 store i32 0, ptr %r, align 4 436 br label %ret 437ret: 438 %0 = load i32, ptr %r, align 4 439 ret i32 %0 440} 441 442define i32 @test_fcmpuge(float %a, float %b) #0 { 443; CHECK-LABEL: test_fcmpuge: 444; CHECK: # %bb.0: # %entry 445; CHECK-NEXT: stwu 1, -16(1) 446; CHECK-NEXT: efscmplt 0, 3, 4 447; CHECK-NEXT: bgt 0, .LBB20_2 448; CHECK-NEXT: # %bb.1: # %tr 449; CHECK-NEXT: li 3, 1 450; CHECK-NEXT: b .LBB20_3 451; CHECK-NEXT: .LBB20_2: # %fa 452; CHECK-NEXT: li 3, 0 453; CHECK-NEXT: .LBB20_3: # %ret 454; CHECK-NEXT: stw 3, 12(1) 455; CHECK-NEXT: lwz 3, 12(1) 456; CHECK-NEXT: addi 1, 1, 16 457; CHECK-NEXT: blr 458 entry: 459 %r = alloca i32, align 4 460 %c = fcmp uge float %a, %b 461 br i1 %c, label %tr, label %fa 462tr: 463 store i32 1, ptr %r, align 4 464 br label %ret 465fa: 466 store i32 0, ptr %r, align 4 467 br label %ret 468ret: 469 %0 = load i32, ptr %r, align 4 470 ret i32 %0 471} 472 473 474define i32 @test_ftoui(float %a) #0 { 475; CHECK-LABEL: test_ftoui: 476; CHECK: # %bb.0: 477; CHECK-NEXT: efsctuiz 3, 3 478; CHECK-NEXT: blr 479 %v = fptoui float %a to i32 480 ret i32 %v 481} 482 483define i32 @test_ftosi(float %a) #0 { 484; CHECK-LABEL: test_ftosi: 485; CHECK: # %bb.0: 486; CHECK-NEXT: efsctsiz 3, 3 487; CHECK-NEXT: blr 488 %v = fptosi float %a to i32 489 ret i32 %v 490} 491 492define float @test_ffromui(i32 %a) #0 { 493; CHECK-LABEL: test_ffromui: 494; CHECK: # %bb.0: 495; CHECK-NEXT: efscfui 3, 3 496; CHECK-NEXT: blr 497 %v = uitofp i32 %a to float 498 ret float %v 499} 500 501define float @test_ffromsi(i32 %a) #0 { 502; CHECK-LABEL: test_ffromsi: 503; CHECK: # %bb.0: 504; CHECK-NEXT: efscfsi 3, 3 505; CHECK-NEXT: blr 506 %v = sitofp i32 %a to float 507 ret float %v 508} 509 510define i32 @test_fasmconst(float %x) #0 { 511; CHECK-LABEL: test_fasmconst: 512; CHECK: # %bb.0: # %entry 513; CHECK-NEXT: stwu 1, -32(1) 514; CHECK-NEXT: stw 3, 20(1) 515; CHECK-NEXT: stw 3, 24(1) 516; CHECK-NEXT: lwz 3, 20(1) 517; CHECK-NEXT: #APP 518; CHECK-NEXT: efsctsi 3, 3 519; CHECK-NEXT: #NO_APP 520; CHECK-NEXT: addi 1, 1, 32 521; CHECK-NEXT: blr 522entry: 523 %x.addr = alloca float, align 8 524 store float %x, ptr %x.addr, align 8 525 %0 = load float, ptr %x.addr, align 8 526 %1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0) 527 ret i32 %1 528; Check that it's not loading a double 529} 530attributes #0 = { nounwind } 531 532; Double tests 533; results depend on -mattr=+spe or -mattr=+efpu2 534 535define float @test_dtos(double %a) #0 { 536; SPE-LABEL: test_dtos: 537; SPE: # %bb.0: # %entry 538; SPE-NEXT: evmergelo 3, 3, 4 539; SPE-NEXT: efscfd 3, 3 540; SPE-NEXT: blr 541; 542; EFPU2-LABEL: test_dtos: 543; EFPU2: # %bb.0: # %entry 544; EFPU2-NEXT: mflr 0 545; EFPU2-NEXT: stwu 1, -16(1) 546; EFPU2-NEXT: stw 0, 20(1) 547; EFPU2-NEXT: bl __truncdfsf2 548; EFPU2-NEXT: lwz 0, 20(1) 549; EFPU2-NEXT: addi 1, 1, 16 550; EFPU2-NEXT: mtlr 0 551; EFPU2-NEXT: blr 552 entry: 553 %v = fptrunc double %a to float 554 ret float %v 555} 556 557define void @test_double_abs(ptr %aa) #0 { 558; SPE-LABEL: test_double_abs: 559; SPE: # %bb.0: # %entry 560; SPE-NEXT: evldd 4, 0(3) 561; SPE-NEXT: efdabs 4, 4 562; SPE-NEXT: evstdd 4, 0(3) 563; SPE-NEXT: blr 564; 565; EFPU2-LABEL: test_double_abs: 566; EFPU2: # %bb.0: # %entry 567; EFPU2-NEXT: lwz 4, 0(3) 568; EFPU2-NEXT: clrlwi 4, 4, 1 569; EFPU2-NEXT: stw 4, 0(3) 570; EFPU2-NEXT: blr 571 entry: 572 %0 = load double, ptr %aa 573 %1 = tail call double @llvm.fabs.f64(double %0) #2 574 store double %1, ptr %aa 575 ret void 576} 577 578; Function Attrs: nounwind readnone 579declare double @llvm.fabs.f64(double) #1 580 581define void @test_dnabs(ptr %aa) #0 { 582; SPE-LABEL: test_dnabs: 583; SPE: # %bb.0: # %entry 584; SPE-NEXT: evldd 4, 0(3) 585; SPE-NEXT: efdnabs 4, 4 586; SPE-NEXT: evstdd 4, 0(3) 587; SPE-NEXT: blr 588; 589; EFPU2-LABEL: test_dnabs: 590; EFPU2: # %bb.0: # %entry 591; EFPU2-NEXT: lwz 4, 0(3) 592; EFPU2-NEXT: oris 4, 4, 32768 593; EFPU2-NEXT: stw 4, 0(3) 594; EFPU2-NEXT: blr 595 entry: 596 %0 = load double, ptr %aa 597 %1 = tail call double @llvm.fabs.f64(double %0) #2 598 %sub = fsub double -0.000000e+00, %1 599 store double %sub, ptr %aa 600 ret void 601} 602 603define double @test_ddiv(double %a, double %b) #0 { 604; SPE-LABEL: test_ddiv: 605; SPE: # %bb.0: # %entry 606; SPE-NEXT: evmergelo 5, 5, 6 607; SPE-NEXT: evmergelo 3, 3, 4 608; SPE-NEXT: efddiv 4, 3, 5 609; SPE-NEXT: evmergehi 3, 4, 4 610; SPE-NEXT: blr 611; 612; EFPU2-LABEL: test_ddiv: 613; EFPU2: # %bb.0: # %entry 614; EFPU2-NEXT: mflr 0 615; EFPU2-NEXT: stwu 1, -16(1) 616; EFPU2-NEXT: stw 0, 20(1) 617; EFPU2-NEXT: bl __divdf3 618; EFPU2-NEXT: lwz 0, 20(1) 619; EFPU2-NEXT: addi 1, 1, 16 620; EFPU2-NEXT: mtlr 0 621; EFPU2-NEXT: blr 622entry: 623 %v = fdiv double %a, %b 624 ret double %v 625 626} 627 628define double @test_dmul(double %a, double %b) #0 { 629; SPE-LABEL: test_dmul: 630; SPE: # %bb.0: # %entry 631; SPE-NEXT: evmergelo 5, 5, 6 632; SPE-NEXT: evmergelo 3, 3, 4 633; SPE-NEXT: efdmul 4, 3, 5 634; SPE-NEXT: evmergehi 3, 4, 4 635; SPE-NEXT: blr 636; 637; EFPU2-LABEL: test_dmul: 638; EFPU2: # %bb.0: # %entry 639; EFPU2-NEXT: mflr 0 640; EFPU2-NEXT: stwu 1, -16(1) 641; EFPU2-NEXT: stw 0, 20(1) 642; EFPU2-NEXT: bl __muldf3 643; EFPU2-NEXT: lwz 0, 20(1) 644; EFPU2-NEXT: addi 1, 1, 16 645; EFPU2-NEXT: mtlr 0 646; EFPU2-NEXT: blr 647 entry: 648 %v = fmul double %a, %b 649 ret double %v 650} 651 652define double @test_dadd(double %a, double %b) #0 { 653; SPE-LABEL: test_dadd: 654; SPE: # %bb.0: # %entry 655; SPE-NEXT: evmergelo 5, 5, 6 656; SPE-NEXT: evmergelo 3, 3, 4 657; SPE-NEXT: efdadd 4, 3, 5 658; SPE-NEXT: evmergehi 3, 4, 4 659; SPE-NEXT: blr 660; 661; EFPU2-LABEL: test_dadd: 662; EFPU2: # %bb.0: # %entry 663; EFPU2-NEXT: mflr 0 664; EFPU2-NEXT: stwu 1, -16(1) 665; EFPU2-NEXT: stw 0, 20(1) 666; EFPU2-NEXT: bl __adddf3 667; EFPU2-NEXT: lwz 0, 20(1) 668; EFPU2-NEXT: addi 1, 1, 16 669; EFPU2-NEXT: mtlr 0 670; EFPU2-NEXT: blr 671 entry: 672 %v = fadd double %a, %b 673 ret double %v 674} 675 676define double @test_dsub(double %a, double %b) #0 { 677; SPE-LABEL: test_dsub: 678; SPE: # %bb.0: # %entry 679; SPE-NEXT: evmergelo 5, 5, 6 680; SPE-NEXT: evmergelo 3, 3, 4 681; SPE-NEXT: efdsub 4, 3, 5 682; SPE-NEXT: evmergehi 3, 4, 4 683; SPE-NEXT: blr 684; 685; EFPU2-LABEL: test_dsub: 686; EFPU2: # %bb.0: # %entry 687; EFPU2-NEXT: mflr 0 688; EFPU2-NEXT: stwu 1, -16(1) 689; EFPU2-NEXT: stw 0, 20(1) 690; EFPU2-NEXT: bl __subdf3 691; EFPU2-NEXT: lwz 0, 20(1) 692; EFPU2-NEXT: addi 1, 1, 16 693; EFPU2-NEXT: mtlr 0 694; EFPU2-NEXT: blr 695 entry: 696 %v = fsub double %a, %b 697 ret double %v 698} 699 700define double @test_dneg(double %a) #0 { 701; SPE-LABEL: test_dneg: 702; SPE: # %bb.0: # %entry 703; SPE-NEXT: evmergelo 3, 3, 4 704; SPE-NEXT: efdneg 4, 3 705; SPE-NEXT: evmergehi 3, 4, 4 706; SPE-NEXT: blr 707; 708; EFPU2-LABEL: test_dneg: 709; EFPU2: # %bb.0: # %entry 710; EFPU2-NEXT: xoris 3, 3, 32768 711; EFPU2-NEXT: blr 712 entry: 713 %v = fsub double -0.0, %a 714 ret double %v 715} 716 717define double @test_stod(float %a) #0 { 718; SPE-LABEL: test_stod: 719; SPE: # %bb.0: # %entry 720; SPE-NEXT: efdcfs 4, 3 721; SPE-NEXT: evmergehi 3, 4, 4 722; SPE-NEXT: blr 723; 724; EFPU2-LABEL: test_stod: 725; EFPU2: # %bb.0: # %entry 726; EFPU2-NEXT: mflr 0 727; EFPU2-NEXT: stwu 1, -16(1) 728; EFPU2-NEXT: stw 0, 20(1) 729; EFPU2-NEXT: bl __extendsfdf2 730; EFPU2-NEXT: lwz 0, 20(1) 731; EFPU2-NEXT: addi 1, 1, 16 732; EFPU2-NEXT: mtlr 0 733; EFPU2-NEXT: blr 734 entry: 735 %v = fpext float %a to double 736 ret double %v 737} 738 739; (un)ordered tests are expanded to une and oeq so verify 740define i1 @test_dcmpuno(double %a, double %b) #0 { 741; SPE-LABEL: test_dcmpuno: 742; SPE: # %bb.0: # %entry 743; SPE-NEXT: evmergelo 5, 5, 6 744; SPE-NEXT: evmergelo 3, 3, 4 745; SPE-NEXT: efdcmpeq 0, 3, 3 746; SPE-NEXT: li 3, 0 747; SPE-NEXT: bc 4, 1, .LBB35_2 748; SPE-NEXT: # %bb.1: # %entry 749; SPE-NEXT: efdcmpeq 0, 5, 5 750; SPE-NEXT: bclr 12, 1, 0 751; SPE-NEXT: .LBB35_2: # %entry 752; SPE-NEXT: li 3, 1 753; SPE-NEXT: blr 754; 755; EFPU2-LABEL: test_dcmpuno: 756; EFPU2: # %bb.0: # %entry 757; EFPU2-NEXT: mflr 0 758; EFPU2-NEXT: stwu 1, -16(1) 759; EFPU2-NEXT: stw 0, 20(1) 760; EFPU2-NEXT: bl __unorddf2 761; EFPU2-NEXT: cntlzw 3, 3 762; EFPU2-NEXT: not 3, 3 763; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31 764; EFPU2-NEXT: lwz 0, 20(1) 765; EFPU2-NEXT: addi 1, 1, 16 766; EFPU2-NEXT: mtlr 0 767; EFPU2-NEXT: blr 768 entry: 769 %r = fcmp uno double %a, %b 770 ret i1 %r 771} 772 773define i1 @test_dcmpord(double %a, double %b) #0 { 774; SPE-LABEL: test_dcmpord: 775; SPE: # %bb.0: # %entry 776; SPE-NEXT: evmergelo 4, 3, 4 777; SPE-NEXT: evmergelo 3, 5, 6 778; SPE-NEXT: efdcmpeq 0, 3, 3 779; SPE-NEXT: li 3, 0 780; SPE-NEXT: bclr 4, 1, 0 781; SPE-NEXT: # %bb.1: # %entry 782; SPE-NEXT: efdcmpeq 0, 4, 4 783; SPE-NEXT: bclr 4, 1, 0 784; SPE-NEXT: # %bb.2: # %entry 785; SPE-NEXT: li 3, 1 786; SPE-NEXT: blr 787; 788; EFPU2-LABEL: test_dcmpord: 789; EFPU2: # %bb.0: # %entry 790; EFPU2-NEXT: mflr 0 791; EFPU2-NEXT: stwu 1, -16(1) 792; EFPU2-NEXT: stw 0, 20(1) 793; EFPU2-NEXT: bl __unorddf2 794; EFPU2-NEXT: cntlzw 3, 3 795; EFPU2-NEXT: rlwinm 3, 3, 27, 31, 31 796; EFPU2-NEXT: lwz 0, 20(1) 797; EFPU2-NEXT: addi 1, 1, 16 798; EFPU2-NEXT: mtlr 0 799; EFPU2-NEXT: blr 800 entry: 801 %r = fcmp ord double %a, %b 802 ret i1 %r 803} 804 805define i32 @test_dcmpgt(double %a, double %b) #0 { 806; SPE-LABEL: test_dcmpgt: 807; SPE: # %bb.0: # %entry 808; SPE-NEXT: stwu 1, -16(1) 809; SPE-NEXT: evmergelo 5, 5, 6 810; SPE-NEXT: evmergelo 3, 3, 4 811; SPE-NEXT: efdcmpgt 0, 3, 5 812; SPE-NEXT: ble 0, .LBB37_2 813; SPE-NEXT: # %bb.1: # %tr 814; SPE-NEXT: li 3, 1 815; SPE-NEXT: b .LBB37_3 816; SPE-NEXT: .LBB37_2: # %fa 817; SPE-NEXT: li 3, 0 818; SPE-NEXT: .LBB37_3: # %ret 819; SPE-NEXT: stw 3, 12(1) 820; SPE-NEXT: lwz 3, 12(1) 821; SPE-NEXT: addi 1, 1, 16 822; SPE-NEXT: blr 823; 824; EFPU2-LABEL: test_dcmpgt: 825; EFPU2: # %bb.0: # %entry 826; EFPU2-NEXT: mflr 0 827; EFPU2-NEXT: stwu 1, -16(1) 828; EFPU2-NEXT: stw 0, 20(1) 829; EFPU2-NEXT: bl __gtdf2 830; EFPU2-NEXT: cmpwi 3, 0 831; EFPU2-NEXT: ble 0, .LBB37_2 832; EFPU2-NEXT: # %bb.1: # %tr 833; EFPU2-NEXT: li 3, 1 834; EFPU2-NEXT: b .LBB37_3 835; EFPU2-NEXT: .LBB37_2: # %fa 836; EFPU2-NEXT: li 3, 0 837; EFPU2-NEXT: .LBB37_3: # %ret 838; EFPU2-NEXT: stw 3, 12(1) 839; EFPU2-NEXT: lwz 3, 12(1) 840; EFPU2-NEXT: lwz 0, 20(1) 841; EFPU2-NEXT: addi 1, 1, 16 842; EFPU2-NEXT: mtlr 0 843; EFPU2-NEXT: blr 844 entry: 845 %r = alloca i32, align 4 846 %c = fcmp ogt double %a, %b 847 br i1 %c, label %tr, label %fa 848tr: 849 store i32 1, ptr %r, align 4 850 br label %ret 851fa: 852 store i32 0, ptr %r, align 4 853 br label %ret 854ret: 855 %0 = load i32, ptr %r, align 4 856 ret i32 %0 857} 858 859define i32 @test_dcmpugt(double %a, double %b) #0 { 860; SPE-LABEL: test_dcmpugt: 861; SPE: # %bb.0: # %entry 862; SPE-NEXT: stwu 1, -16(1) 863; SPE-NEXT: evmergelo 3, 3, 4 864; SPE-NEXT: evmergelo 4, 5, 6 865; SPE-NEXT: efdcmpeq 0, 4, 4 866; SPE-NEXT: bc 4, 1, .LBB38_4 867; SPE-NEXT: # %bb.1: # %entry 868; SPE-NEXT: efdcmpeq 0, 3, 3 869; SPE-NEXT: bc 4, 1, .LBB38_4 870; SPE-NEXT: # %bb.2: # %entry 871; SPE-NEXT: efdcmpgt 0, 3, 4 872; SPE-NEXT: bc 12, 1, .LBB38_4 873; SPE-NEXT: # %bb.3: # %fa 874; SPE-NEXT: li 3, 0 875; SPE-NEXT: b .LBB38_5 876; SPE-NEXT: .LBB38_4: # %tr 877; SPE-NEXT: li 3, 1 878; SPE-NEXT: .LBB38_5: # %ret 879; SPE-NEXT: stw 3, 12(1) 880; SPE-NEXT: lwz 3, 12(1) 881; SPE-NEXT: addi 1, 1, 16 882; SPE-NEXT: blr 883; 884; EFPU2-LABEL: test_dcmpugt: 885; EFPU2: # %bb.0: # %entry 886; EFPU2-NEXT: mflr 0 887; EFPU2-NEXT: stwu 1, -16(1) 888; EFPU2-NEXT: stw 0, 20(1) 889; EFPU2-NEXT: bl __ledf2 890; EFPU2-NEXT: cmpwi 3, 0 891; EFPU2-NEXT: ble 0, .LBB38_2 892; EFPU2-NEXT: # %bb.1: # %tr 893; EFPU2-NEXT: li 3, 1 894; EFPU2-NEXT: b .LBB38_3 895; EFPU2-NEXT: .LBB38_2: # %fa 896; EFPU2-NEXT: li 3, 0 897; EFPU2-NEXT: .LBB38_3: # %ret 898; EFPU2-NEXT: stw 3, 12(1) 899; EFPU2-NEXT: lwz 3, 12(1) 900; EFPU2-NEXT: lwz 0, 20(1) 901; EFPU2-NEXT: addi 1, 1, 16 902; EFPU2-NEXT: mtlr 0 903; EFPU2-NEXT: blr 904 entry: 905 %r = alloca i32, align 4 906 %c = fcmp ugt double %a, %b 907 br i1 %c, label %tr, label %fa 908tr: 909 store i32 1, ptr %r, align 4 910 br label %ret 911fa: 912 store i32 0, ptr %r, align 4 913 br label %ret 914ret: 915 %0 = load i32, ptr %r, align 4 916 ret i32 %0 917} 918 919define i32 @test_dcmple(double %a, double %b) #0 { 920; SPE-LABEL: test_dcmple: 921; SPE: # %bb.0: # %entry 922; SPE-NEXT: stwu 1, -16(1) 923; SPE-NEXT: evmergelo 5, 5, 6 924; SPE-NEXT: evmergelo 3, 3, 4 925; SPE-NEXT: efdcmpgt 0, 3, 5 926; SPE-NEXT: bgt 0, .LBB39_2 927; SPE-NEXT: # %bb.1: # %tr 928; SPE-NEXT: li 3, 1 929; SPE-NEXT: b .LBB39_3 930; SPE-NEXT: .LBB39_2: # %fa 931; SPE-NEXT: li 3, 0 932; SPE-NEXT: .LBB39_3: # %ret 933; SPE-NEXT: stw 3, 12(1) 934; SPE-NEXT: lwz 3, 12(1) 935; SPE-NEXT: addi 1, 1, 16 936; SPE-NEXT: blr 937; 938; EFPU2-LABEL: test_dcmple: 939; EFPU2: # %bb.0: # %entry 940; EFPU2-NEXT: mflr 0 941; EFPU2-NEXT: stwu 1, -16(1) 942; EFPU2-NEXT: stw 0, 20(1) 943; EFPU2-NEXT: bl __gtdf2 944; EFPU2-NEXT: cmpwi 3, 0 945; EFPU2-NEXT: bgt 0, .LBB39_2 946; EFPU2-NEXT: # %bb.1: # %tr 947; EFPU2-NEXT: li 3, 1 948; EFPU2-NEXT: b .LBB39_3 949; EFPU2-NEXT: .LBB39_2: # %fa 950; EFPU2-NEXT: li 3, 0 951; EFPU2-NEXT: .LBB39_3: # %ret 952; EFPU2-NEXT: stw 3, 12(1) 953; EFPU2-NEXT: lwz 3, 12(1) 954; EFPU2-NEXT: lwz 0, 20(1) 955; EFPU2-NEXT: addi 1, 1, 16 956; EFPU2-NEXT: mtlr 0 957; EFPU2-NEXT: blr 958 entry: 959 %r = alloca i32, align 4 960 %c = fcmp ule double %a, %b 961 br i1 %c, label %tr, label %fa 962tr: 963 store i32 1, ptr %r, align 4 964 br label %ret 965fa: 966 store i32 0, ptr %r, align 4 967 br label %ret 968ret: 969 %0 = load i32, ptr %r, align 4 970 ret i32 %0 971} 972 973define i32 @test_dcmpule(double %a, double %b) #0 { 974; SPE-LABEL: test_dcmpule: 975; SPE: # %bb.0: # %entry 976; SPE-NEXT: stwu 1, -16(1) 977; SPE-NEXT: evmergelo 5, 5, 6 978; SPE-NEXT: evmergelo 3, 3, 4 979; SPE-NEXT: efdcmpgt 0, 3, 5 980; SPE-NEXT: bgt 0, .LBB40_2 981; SPE-NEXT: # %bb.1: # %tr 982; SPE-NEXT: li 3, 1 983; SPE-NEXT: b .LBB40_3 984; SPE-NEXT: .LBB40_2: # %fa 985; SPE-NEXT: li 3, 0 986; SPE-NEXT: .LBB40_3: # %ret 987; SPE-NEXT: stw 3, 12(1) 988; SPE-NEXT: lwz 3, 12(1) 989; SPE-NEXT: addi 1, 1, 16 990; SPE-NEXT: blr 991; 992; EFPU2-LABEL: test_dcmpule: 993; EFPU2: # %bb.0: # %entry 994; EFPU2-NEXT: mflr 0 995; EFPU2-NEXT: stwu 1, -16(1) 996; EFPU2-NEXT: stw 0, 20(1) 997; EFPU2-NEXT: bl __gtdf2 998; EFPU2-NEXT: cmpwi 3, 0 999; EFPU2-NEXT: bgt 0, .LBB40_2 1000; EFPU2-NEXT: # %bb.1: # %tr 1001; EFPU2-NEXT: li 3, 1 1002; EFPU2-NEXT: b .LBB40_3 1003; EFPU2-NEXT: .LBB40_2: # %fa 1004; EFPU2-NEXT: li 3, 0 1005; EFPU2-NEXT: .LBB40_3: # %ret 1006; EFPU2-NEXT: stw 3, 12(1) 1007; EFPU2-NEXT: lwz 3, 12(1) 1008; EFPU2-NEXT: lwz 0, 20(1) 1009; EFPU2-NEXT: addi 1, 1, 16 1010; EFPU2-NEXT: mtlr 0 1011; EFPU2-NEXT: blr 1012 entry: 1013 %r = alloca i32, align 4 1014 %c = fcmp ule double %a, %b 1015 br i1 %c, label %tr, label %fa 1016tr: 1017 store i32 1, ptr %r, align 4 1018 br label %ret 1019fa: 1020 store i32 0, ptr %r, align 4 1021 br label %ret 1022ret: 1023 %0 = load i32, ptr %r, align 4 1024 ret i32 %0 1025} 1026 1027; The type of comparison found in C's if (x == y) 1028define i32 @test_dcmpeq(double %a, double %b) #0 { 1029; SPE-LABEL: test_dcmpeq: 1030; SPE: # %bb.0: # %entry 1031; SPE-NEXT: stwu 1, -16(1) 1032; SPE-NEXT: evmergelo 5, 5, 6 1033; SPE-NEXT: evmergelo 3, 3, 4 1034; SPE-NEXT: efdcmpeq 0, 3, 5 1035; SPE-NEXT: ble 0, .LBB41_2 1036; SPE-NEXT: # %bb.1: # %tr 1037; SPE-NEXT: li 3, 1 1038; SPE-NEXT: b .LBB41_3 1039; SPE-NEXT: .LBB41_2: # %fa 1040; SPE-NEXT: li 3, 0 1041; SPE-NEXT: .LBB41_3: # %ret 1042; SPE-NEXT: stw 3, 12(1) 1043; SPE-NEXT: lwz 3, 12(1) 1044; SPE-NEXT: addi 1, 1, 16 1045; SPE-NEXT: blr 1046; 1047; EFPU2-LABEL: test_dcmpeq: 1048; EFPU2: # %bb.0: # %entry 1049; EFPU2-NEXT: mflr 0 1050; EFPU2-NEXT: stwu 1, -16(1) 1051; EFPU2-NEXT: stw 0, 20(1) 1052; EFPU2-NEXT: bl __nedf2 1053; EFPU2-NEXT: cmplwi 3, 0 1054; EFPU2-NEXT: bne 0, .LBB41_2 1055; EFPU2-NEXT: # %bb.1: # %tr 1056; EFPU2-NEXT: li 3, 1 1057; EFPU2-NEXT: b .LBB41_3 1058; EFPU2-NEXT: .LBB41_2: # %fa 1059; EFPU2-NEXT: li 3, 0 1060; EFPU2-NEXT: .LBB41_3: # %ret 1061; EFPU2-NEXT: stw 3, 12(1) 1062; EFPU2-NEXT: lwz 3, 12(1) 1063; EFPU2-NEXT: lwz 0, 20(1) 1064; EFPU2-NEXT: addi 1, 1, 16 1065; EFPU2-NEXT: mtlr 0 1066; EFPU2-NEXT: blr 1067 entry: 1068 %r = alloca i32, align 4 1069 %c = fcmp oeq double %a, %b 1070 br i1 %c, label %tr, label %fa 1071tr: 1072 store i32 1, ptr %r, align 4 1073 br label %ret 1074fa: 1075 store i32 0, ptr %r, align 4 1076 br label %ret 1077ret: 1078 %0 = load i32, ptr %r, align 4 1079 ret i32 %0 1080} 1081 1082define i32 @test_dcmpueq(double %a, double %b) #0 { 1083; SPE-LABEL: test_dcmpueq: 1084; SPE: # %bb.0: # %entry 1085; SPE-NEXT: stwu 1, -16(1) 1086; SPE-NEXT: evmergelo 5, 5, 6 1087; SPE-NEXT: evmergelo 3, 3, 4 1088; SPE-NEXT: efdcmplt 0, 3, 5 1089; SPE-NEXT: bc 12, 1, .LBB42_3 1090; SPE-NEXT: # %bb.1: # %entry 1091; SPE-NEXT: efdcmpgt 0, 3, 5 1092; SPE-NEXT: bc 12, 1, .LBB42_3 1093; SPE-NEXT: # %bb.2: # %tr 1094; SPE-NEXT: li 3, 1 1095; SPE-NEXT: b .LBB42_4 1096; SPE-NEXT: .LBB42_3: # %fa 1097; SPE-NEXT: li 3, 0 1098; SPE-NEXT: .LBB42_4: # %ret 1099; SPE-NEXT: stw 3, 12(1) 1100; SPE-NEXT: lwz 3, 12(1) 1101; SPE-NEXT: addi 1, 1, 16 1102; SPE-NEXT: blr 1103; 1104; EFPU2-LABEL: test_dcmpueq: 1105; EFPU2: # %bb.0: # %entry 1106; EFPU2-NEXT: mflr 0 1107; EFPU2-NEXT: stwu 1, -48(1) 1108; EFPU2-NEXT: mfcr 12 1109; EFPU2-NEXT: stw 0, 52(1) 1110; EFPU2-NEXT: stw 12, 24(1) 1111; EFPU2-NEXT: stw 27, 28(1) # 4-byte Folded Spill 1112; EFPU2-NEXT: mr 27, 3 1113; EFPU2-NEXT: stw 28, 32(1) # 4-byte Folded Spill 1114; EFPU2-NEXT: mr 28, 4 1115; EFPU2-NEXT: stw 29, 36(1) # 4-byte Folded Spill 1116; EFPU2-NEXT: mr 29, 5 1117; EFPU2-NEXT: stw 30, 40(1) # 4-byte Folded Spill 1118; EFPU2-NEXT: mr 30, 6 1119; EFPU2-NEXT: bl __eqdf2 1120; EFPU2-NEXT: cmpwi 2, 3, 0 1121; EFPU2-NEXT: mr 3, 27 1122; EFPU2-NEXT: mr 4, 28 1123; EFPU2-NEXT: mr 5, 29 1124; EFPU2-NEXT: mr 6, 30 1125; EFPU2-NEXT: bl __unorddf2 1126; EFPU2-NEXT: bc 12, 10, .LBB42_3 1127; EFPU2-NEXT: # %bb.1: # %entry 1128; EFPU2-NEXT: cmpwi 3, 0 1129; EFPU2-NEXT: bc 4, 2, .LBB42_3 1130; EFPU2-NEXT: # %bb.2: # %fa 1131; EFPU2-NEXT: li 3, 0 1132; EFPU2-NEXT: b .LBB42_4 1133; EFPU2-NEXT: .LBB42_3: # %tr 1134; EFPU2-NEXT: li 3, 1 1135; EFPU2-NEXT: .LBB42_4: # %ret 1136; EFPU2-NEXT: stw 3, 20(1) 1137; EFPU2-NEXT: lwz 3, 20(1) 1138; EFPU2-NEXT: lwz 30, 40(1) # 4-byte Folded Reload 1139; EFPU2-NEXT: lwz 29, 36(1) # 4-byte Folded Reload 1140; EFPU2-NEXT: lwz 28, 32(1) # 4-byte Folded Reload 1141; EFPU2-NEXT: lwz 12, 24(1) 1142; EFPU2-NEXT: lwz 27, 28(1) # 4-byte Folded Reload 1143; EFPU2-NEXT: mtcrf 32, 12 # cr2 1144; EFPU2-NEXT: lwz 0, 52(1) 1145; EFPU2-NEXT: addi 1, 1, 48 1146; EFPU2-NEXT: mtlr 0 1147; EFPU2-NEXT: blr 1148 entry: 1149 %r = alloca i32, align 4 1150 %c = fcmp ueq double %a, %b 1151 br i1 %c, label %tr, label %fa 1152tr: 1153 store i32 1, ptr %r, align 4 1154 br label %ret 1155fa: 1156 store i32 0, ptr %r, align 4 1157 br label %ret 1158ret: 1159 %0 = load i32, ptr %r, align 4 1160 ret i32 %0 1161} 1162 1163define i1 @test_dcmpne(double %a, double %b) #0 { 1164; SPE-LABEL: test_dcmpne: 1165; SPE: # %bb.0: # %entry 1166; SPE-NEXT: evmergelo 5, 5, 6 1167; SPE-NEXT: evmergelo 4, 3, 4 1168; SPE-NEXT: li 3, 0 1169; SPE-NEXT: efdcmplt 0, 4, 5 1170; SPE-NEXT: bc 12, 1, .LBB43_2 1171; SPE-NEXT: # %bb.1: # %entry 1172; SPE-NEXT: efdcmpgt 0, 4, 5 1173; SPE-NEXT: bclr 4, 1, 0 1174; SPE-NEXT: .LBB43_2: # %entry 1175; SPE-NEXT: li 3, 1 1176; SPE-NEXT: blr 1177; 1178; EFPU2-LABEL: test_dcmpne: 1179; EFPU2: # %bb.0: # %entry 1180; EFPU2-NEXT: mflr 0 1181; EFPU2-NEXT: stwu 1, -48(1) 1182; EFPU2-NEXT: mfcr 12 1183; EFPU2-NEXT: stw 0, 52(1) 1184; EFPU2-NEXT: stw 12, 24(1) 1185; EFPU2-NEXT: stw 27, 28(1) # 4-byte Folded Spill 1186; EFPU2-NEXT: mr 27, 3 1187; EFPU2-NEXT: stw 28, 32(1) # 4-byte Folded Spill 1188; EFPU2-NEXT: mr 28, 4 1189; EFPU2-NEXT: stw 29, 36(1) # 4-byte Folded Spill 1190; EFPU2-NEXT: mr 29, 5 1191; EFPU2-NEXT: stw 30, 40(1) # 4-byte Folded Spill 1192; EFPU2-NEXT: mr 30, 6 1193; EFPU2-NEXT: bl __unorddf2 1194; EFPU2-NEXT: cmpwi 2, 3, 0 1195; EFPU2-NEXT: mr 3, 27 1196; EFPU2-NEXT: mr 4, 28 1197; EFPU2-NEXT: mr 5, 29 1198; EFPU2-NEXT: mr 6, 30 1199; EFPU2-NEXT: bl __eqdf2 1200; EFPU2-NEXT: mr 4, 3 1201; EFPU2-NEXT: li 3, 0 1202; EFPU2-NEXT: bc 4, 10, .LBB43_3 1203; EFPU2-NEXT: # %bb.1: # %entry 1204; EFPU2-NEXT: cmpwi 4, 0 1205; EFPU2-NEXT: bc 12, 2, .LBB43_3 1206; EFPU2-NEXT: # %bb.2: # %entry 1207; EFPU2-NEXT: li 3, 1 1208; EFPU2-NEXT: .LBB43_3: # %entry 1209; EFPU2-NEXT: lwz 30, 40(1) # 4-byte Folded Reload 1210; EFPU2-NEXT: lwz 29, 36(1) # 4-byte Folded Reload 1211; EFPU2-NEXT: lwz 28, 32(1) # 4-byte Folded Reload 1212; EFPU2-NEXT: lwz 12, 24(1) 1213; EFPU2-NEXT: lwz 27, 28(1) # 4-byte Folded Reload 1214; EFPU2-NEXT: mtcrf 32, 12 # cr2 1215; EFPU2-NEXT: lwz 0, 52(1) 1216; EFPU2-NEXT: addi 1, 1, 48 1217; EFPU2-NEXT: mtlr 0 1218; EFPU2-NEXT: blr 1219 entry: 1220 %r = fcmp one double %a, %b 1221 ret i1 %r 1222} 1223 1224define i32 @test_dcmpune(double %a, double %b) #0 { 1225; SPE-LABEL: test_dcmpune: 1226; SPE: # %bb.0: # %entry 1227; SPE-NEXT: stwu 1, -16(1) 1228; SPE-NEXT: evmergelo 5, 5, 6 1229; SPE-NEXT: evmergelo 3, 3, 4 1230; SPE-NEXT: efdcmpeq 0, 3, 5 1231; SPE-NEXT: bgt 0, .LBB44_2 1232; SPE-NEXT: # %bb.1: # %tr 1233; SPE-NEXT: li 3, 1 1234; SPE-NEXT: b .LBB44_3 1235; SPE-NEXT: .LBB44_2: # %fa 1236; SPE-NEXT: li 3, 0 1237; SPE-NEXT: .LBB44_3: # %ret 1238; SPE-NEXT: stw 3, 12(1) 1239; SPE-NEXT: lwz 3, 12(1) 1240; SPE-NEXT: addi 1, 1, 16 1241; SPE-NEXT: blr 1242; 1243; EFPU2-LABEL: test_dcmpune: 1244; EFPU2: # %bb.0: # %entry 1245; EFPU2-NEXT: mflr 0 1246; EFPU2-NEXT: stwu 1, -16(1) 1247; EFPU2-NEXT: stw 0, 20(1) 1248; EFPU2-NEXT: bl __eqdf2 1249; EFPU2-NEXT: cmplwi 3, 0 1250; EFPU2-NEXT: beq 0, .LBB44_2 1251; EFPU2-NEXT: # %bb.1: # %tr 1252; EFPU2-NEXT: li 3, 1 1253; EFPU2-NEXT: b .LBB44_3 1254; EFPU2-NEXT: .LBB44_2: # %fa 1255; EFPU2-NEXT: li 3, 0 1256; EFPU2-NEXT: .LBB44_3: # %ret 1257; EFPU2-NEXT: stw 3, 12(1) 1258; EFPU2-NEXT: lwz 3, 12(1) 1259; EFPU2-NEXT: lwz 0, 20(1) 1260; EFPU2-NEXT: addi 1, 1, 16 1261; EFPU2-NEXT: mtlr 0 1262; EFPU2-NEXT: blr 1263 entry: 1264 %r = alloca i32, align 4 1265 %c = fcmp une double %a, %b 1266 br i1 %c, label %tr, label %fa 1267tr: 1268 store i32 1, ptr %r, align 4 1269 br label %ret 1270fa: 1271 store i32 0, ptr %r, align 4 1272 br label %ret 1273ret: 1274 %0 = load i32, ptr %r, align 4 1275 ret i32 %0 1276} 1277 1278define i32 @test_dcmplt(double %a, double %b) #0 { 1279; SPE-LABEL: test_dcmplt: 1280; SPE: # %bb.0: # %entry 1281; SPE-NEXT: stwu 1, -16(1) 1282; SPE-NEXT: evmergelo 5, 5, 6 1283; SPE-NEXT: evmergelo 3, 3, 4 1284; SPE-NEXT: efdcmplt 0, 3, 5 1285; SPE-NEXT: ble 0, .LBB45_2 1286; SPE-NEXT: # %bb.1: # %tr 1287; SPE-NEXT: li 3, 1 1288; SPE-NEXT: b .LBB45_3 1289; SPE-NEXT: .LBB45_2: # %fa 1290; SPE-NEXT: li 3, 0 1291; SPE-NEXT: .LBB45_3: # %ret 1292; SPE-NEXT: stw 3, 12(1) 1293; SPE-NEXT: lwz 3, 12(1) 1294; SPE-NEXT: addi 1, 1, 16 1295; SPE-NEXT: blr 1296; 1297; EFPU2-LABEL: test_dcmplt: 1298; EFPU2: # %bb.0: # %entry 1299; EFPU2-NEXT: mflr 0 1300; EFPU2-NEXT: stwu 1, -16(1) 1301; EFPU2-NEXT: stw 0, 20(1) 1302; EFPU2-NEXT: bl __ltdf2 1303; EFPU2-NEXT: cmpwi 3, 0 1304; EFPU2-NEXT: bge 0, .LBB45_2 1305; EFPU2-NEXT: # %bb.1: # %tr 1306; EFPU2-NEXT: li 3, 1 1307; EFPU2-NEXT: b .LBB45_3 1308; EFPU2-NEXT: .LBB45_2: # %fa 1309; EFPU2-NEXT: li 3, 0 1310; EFPU2-NEXT: .LBB45_3: # %ret 1311; EFPU2-NEXT: stw 3, 12(1) 1312; EFPU2-NEXT: lwz 3, 12(1) 1313; EFPU2-NEXT: lwz 0, 20(1) 1314; EFPU2-NEXT: addi 1, 1, 16 1315; EFPU2-NEXT: mtlr 0 1316; EFPU2-NEXT: blr 1317 entry: 1318 %r = alloca i32, align 4 1319 %c = fcmp olt double %a, %b 1320 br i1 %c, label %tr, label %fa 1321tr: 1322 store i32 1, ptr %r, align 4 1323 br label %ret 1324fa: 1325 store i32 0, ptr %r, align 4 1326 br label %ret 1327ret: 1328 %0 = load i32, ptr %r, align 4 1329 ret i32 %0 1330} 1331 1332define i32 @test_dcmpult(double %a, double %b) #0 { 1333; SPE-LABEL: test_dcmpult: 1334; SPE: # %bb.0: # %entry 1335; SPE-NEXT: stwu 1, -16(1) 1336; SPE-NEXT: evmergelo 3, 3, 4 1337; SPE-NEXT: evmergelo 4, 5, 6 1338; SPE-NEXT: efdcmpeq 0, 4, 4 1339; SPE-NEXT: bc 4, 1, .LBB46_4 1340; SPE-NEXT: # %bb.1: # %entry 1341; SPE-NEXT: efdcmpeq 0, 3, 3 1342; SPE-NEXT: bc 4, 1, .LBB46_4 1343; SPE-NEXT: # %bb.2: # %entry 1344; SPE-NEXT: efdcmplt 0, 3, 4 1345; SPE-NEXT: bc 12, 1, .LBB46_4 1346; SPE-NEXT: # %bb.3: # %fa 1347; SPE-NEXT: li 3, 0 1348; SPE-NEXT: b .LBB46_5 1349; SPE-NEXT: .LBB46_4: # %tr 1350; SPE-NEXT: li 3, 1 1351; SPE-NEXT: .LBB46_5: # %ret 1352; SPE-NEXT: stw 3, 12(1) 1353; SPE-NEXT: lwz 3, 12(1) 1354; SPE-NEXT: addi 1, 1, 16 1355; SPE-NEXT: blr 1356; 1357; EFPU2-LABEL: test_dcmpult: 1358; EFPU2: # %bb.0: # %entry 1359; EFPU2-NEXT: mflr 0 1360; EFPU2-NEXT: stwu 1, -16(1) 1361; EFPU2-NEXT: stw 0, 20(1) 1362; EFPU2-NEXT: bl __gedf2 1363; EFPU2-NEXT: cmpwi 3, 0 1364; EFPU2-NEXT: bge 0, .LBB46_2 1365; EFPU2-NEXT: # %bb.1: # %tr 1366; EFPU2-NEXT: li 3, 1 1367; EFPU2-NEXT: b .LBB46_3 1368; EFPU2-NEXT: .LBB46_2: # %fa 1369; EFPU2-NEXT: li 3, 0 1370; EFPU2-NEXT: .LBB46_3: # %ret 1371; EFPU2-NEXT: stw 3, 12(1) 1372; EFPU2-NEXT: lwz 3, 12(1) 1373; EFPU2-NEXT: lwz 0, 20(1) 1374; EFPU2-NEXT: addi 1, 1, 16 1375; EFPU2-NEXT: mtlr 0 1376; EFPU2-NEXT: blr 1377 entry: 1378 %r = alloca i32, align 4 1379 %c = fcmp ult double %a, %b 1380 br i1 %c, label %tr, label %fa 1381tr: 1382 store i32 1, ptr %r, align 4 1383 br label %ret 1384fa: 1385 store i32 0, ptr %r, align 4 1386 br label %ret 1387ret: 1388 %0 = load i32, ptr %r, align 4 1389 ret i32 %0 1390} 1391 1392define i1 @test_dcmpge(double %a, double %b) #0 { 1393; SPE-LABEL: test_dcmpge: 1394; SPE: # %bb.0: # %entry 1395; SPE-NEXT: evmergelo 4, 3, 4 1396; SPE-NEXT: evmergelo 5, 5, 6 1397; SPE-NEXT: li 3, 0 1398; SPE-NEXT: efdcmpeq 0, 5, 5 1399; SPE-NEXT: bclr 4, 1, 0 1400; SPE-NEXT: # %bb.1: # %entry 1401; SPE-NEXT: efdcmpeq 0, 4, 4 1402; SPE-NEXT: bclr 4, 1, 0 1403; SPE-NEXT: # %bb.2: # %entry 1404; SPE-NEXT: efdcmplt 0, 4, 5 1405; SPE-NEXT: bclr 12, 1, 0 1406; SPE-NEXT: # %bb.3: # %entry 1407; SPE-NEXT: li 3, 1 1408; SPE-NEXT: blr 1409; 1410; EFPU2-LABEL: test_dcmpge: 1411; EFPU2: # %bb.0: # %entry 1412; EFPU2-NEXT: mflr 0 1413; EFPU2-NEXT: stwu 1, -16(1) 1414; EFPU2-NEXT: stw 0, 20(1) 1415; EFPU2-NEXT: bl __gedf2 1416; EFPU2-NEXT: not 3, 3 1417; EFPU2-NEXT: srwi 3, 3, 31 1418; EFPU2-NEXT: lwz 0, 20(1) 1419; EFPU2-NEXT: addi 1, 1, 16 1420; EFPU2-NEXT: mtlr 0 1421; EFPU2-NEXT: blr 1422 entry: 1423 %r = fcmp oge double %a, %b 1424 ret i1 %r 1425} 1426 1427define i32 @test_dcmpuge(double %a, double %b) #0 { 1428; SPE-LABEL: test_dcmpuge: 1429; SPE: # %bb.0: # %entry 1430; SPE-NEXT: stwu 1, -16(1) 1431; SPE-NEXT: evmergelo 5, 5, 6 1432; SPE-NEXT: evmergelo 3, 3, 4 1433; SPE-NEXT: efdcmplt 0, 3, 5 1434; SPE-NEXT: bgt 0, .LBB48_2 1435; SPE-NEXT: # %bb.1: # %tr 1436; SPE-NEXT: li 3, 1 1437; SPE-NEXT: b .LBB48_3 1438; SPE-NEXT: .LBB48_2: # %fa 1439; SPE-NEXT: li 3, 0 1440; SPE-NEXT: .LBB48_3: # %ret 1441; SPE-NEXT: stw 3, 12(1) 1442; SPE-NEXT: lwz 3, 12(1) 1443; SPE-NEXT: addi 1, 1, 16 1444; SPE-NEXT: blr 1445; 1446; EFPU2-LABEL: test_dcmpuge: 1447; EFPU2: # %bb.0: # %entry 1448; EFPU2-NEXT: mflr 0 1449; EFPU2-NEXT: stwu 1, -16(1) 1450; EFPU2-NEXT: stw 0, 20(1) 1451; EFPU2-NEXT: bl __ltdf2 1452; EFPU2-NEXT: cmpwi 3, 0 1453; EFPU2-NEXT: blt 0, .LBB48_2 1454; EFPU2-NEXT: # %bb.1: # %tr 1455; EFPU2-NEXT: li 3, 1 1456; EFPU2-NEXT: b .LBB48_3 1457; EFPU2-NEXT: .LBB48_2: # %fa 1458; EFPU2-NEXT: li 3, 0 1459; EFPU2-NEXT: .LBB48_3: # %ret 1460; EFPU2-NEXT: stw 3, 12(1) 1461; EFPU2-NEXT: lwz 3, 12(1) 1462; EFPU2-NEXT: lwz 0, 20(1) 1463; EFPU2-NEXT: addi 1, 1, 16 1464; EFPU2-NEXT: mtlr 0 1465; EFPU2-NEXT: blr 1466 entry: 1467 %r = alloca i32, align 4 1468 %c = fcmp uge double %a, %b 1469 br i1 %c, label %tr, label %fa 1470tr: 1471 store i32 1, ptr %r, align 4 1472 br label %ret 1473fa: 1474 store i32 0, ptr %r, align 4 1475 br label %ret 1476ret: 1477 %0 = load i32, ptr %r, align 4 1478 ret i32 %0 1479} 1480 1481define double @test_dselect(double %a, double %b, i1 %c) #0 { 1482; SPE-LABEL: test_dselect: 1483; SPE: # %bb.0: # %entry 1484; SPE-NEXT: andi. 7, 7, 1 1485; SPE-NEXT: evmergelo 5, 5, 6 1486; SPE-NEXT: evmergelo 4, 3, 4 1487; SPE-NEXT: bc 12, 1, .LBB49_2 1488; SPE-NEXT: # %bb.1: # %entry 1489; SPE-NEXT: evor 4, 5, 5 1490; SPE-NEXT: .LBB49_2: # %entry 1491; SPE-NEXT: evmergehi 3, 4, 4 1492; SPE-NEXT: blr 1493; 1494; EFPU2-LABEL: test_dselect: 1495; EFPU2: # %bb.0: # %entry 1496; EFPU2-NEXT: andi. 7, 7, 1 1497; EFPU2-NEXT: bc 12, 1, .LBB49_2 1498; EFPU2-NEXT: # %bb.1: # %entry 1499; EFPU2-NEXT: mr 3, 5 1500; EFPU2-NEXT: .LBB49_2: # %entry 1501; EFPU2-NEXT: bclr 12, 1, 0 1502; EFPU2-NEXT: # %bb.3: # %entry 1503; EFPU2-NEXT: mr 4, 6 1504; EFPU2-NEXT: blr 1505entry: 1506 %r = select i1 %c, double %a, double %b 1507 ret double %r 1508} 1509 1510define i32 @test_dtoui(double %a) #0 { 1511; SPE-LABEL: test_dtoui: 1512; SPE: # %bb.0: # %entry 1513; SPE-NEXT: evmergelo 3, 3, 4 1514; SPE-NEXT: efdctuiz 3, 3 1515; SPE-NEXT: blr 1516; 1517; EFPU2-LABEL: test_dtoui: 1518; EFPU2: # %bb.0: # %entry 1519; EFPU2-NEXT: mflr 0 1520; EFPU2-NEXT: stwu 1, -16(1) 1521; EFPU2-NEXT: stw 0, 20(1) 1522; EFPU2-NEXT: bl __fixunsdfsi 1523; EFPU2-NEXT: lwz 0, 20(1) 1524; EFPU2-NEXT: addi 1, 1, 16 1525; EFPU2-NEXT: mtlr 0 1526; EFPU2-NEXT: blr 1527entry: 1528 %v = fptoui double %a to i32 1529 ret i32 %v 1530} 1531 1532define i32 @test_dtosi(double %a) #0 { 1533; SPE-LABEL: test_dtosi: 1534; SPE: # %bb.0: # %entry 1535; SPE-NEXT: evmergelo 3, 3, 4 1536; SPE-NEXT: efdctsiz 3, 3 1537; SPE-NEXT: blr 1538; 1539; EFPU2-LABEL: test_dtosi: 1540; EFPU2: # %bb.0: # %entry 1541; EFPU2-NEXT: mflr 0 1542; EFPU2-NEXT: stwu 1, -16(1) 1543; EFPU2-NEXT: stw 0, 20(1) 1544; EFPU2-NEXT: bl __fixdfsi 1545; EFPU2-NEXT: lwz 0, 20(1) 1546; EFPU2-NEXT: addi 1, 1, 16 1547; EFPU2-NEXT: mtlr 0 1548; EFPU2-NEXT: blr 1549entry: 1550 %v = fptosi double %a to i32 1551 ret i32 %v 1552} 1553 1554define double @test_dfromui(i32 %a) #0 { 1555; SPE-LABEL: test_dfromui: 1556; SPE: # %bb.0: # %entry 1557; SPE-NEXT: efdcfui 4, 3 1558; SPE-NEXT: evmergehi 3, 4, 4 1559; SPE-NEXT: blr 1560; 1561; EFPU2-LABEL: test_dfromui: 1562; EFPU2: # %bb.0: # %entry 1563; EFPU2-NEXT: mflr 0 1564; EFPU2-NEXT: stwu 1, -16(1) 1565; EFPU2-NEXT: stw 0, 20(1) 1566; EFPU2-NEXT: bl __floatunsidf 1567; EFPU2-NEXT: lwz 0, 20(1) 1568; EFPU2-NEXT: addi 1, 1, 16 1569; EFPU2-NEXT: mtlr 0 1570; EFPU2-NEXT: blr 1571entry: 1572 %v = uitofp i32 %a to double 1573 ret double %v 1574} 1575 1576define double @test_dfromsi(i32 %a) #0 { 1577; SPE-LABEL: test_dfromsi: 1578; SPE: # %bb.0: # %entry 1579; SPE-NEXT: efdcfsi 4, 3 1580; SPE-NEXT: evmergehi 3, 4, 4 1581; SPE-NEXT: blr 1582; 1583; EFPU2-LABEL: test_dfromsi: 1584; EFPU2: # %bb.0: # %entry 1585; EFPU2-NEXT: mflr 0 1586; EFPU2-NEXT: stwu 1, -16(1) 1587; EFPU2-NEXT: stw 0, 20(1) 1588; EFPU2-NEXT: bl __floatsidf 1589; EFPU2-NEXT: lwz 0, 20(1) 1590; EFPU2-NEXT: addi 1, 1, 16 1591; EFPU2-NEXT: mtlr 0 1592; EFPU2-NEXT: blr 1593entry: 1594 %v = sitofp i32 %a to double 1595 ret double %v 1596} 1597 1598declare double @test_spill_spe_regs(double, double); 1599define dso_local void @test_func2() #0 { 1600; CHECK-LABEL: test_func2: 1601; CHECK: # %bb.0: # %entry 1602; CHECK-NEXT: blr 1603entry: 1604 ret void 1605} 1606 1607declare void @test_memset(ptr nocapture writeonly, i8, i32, i1) 1608@global_var1 = global i32 0, align 4 1609define double @test_spill(double %a, i32 %a1, i64 %a2, ptr %a3, ptr %a4, ptr %a5) #0 { 1610; SPE-LABEL: test_spill: 1611; SPE: # %bb.0: # %entry 1612; SPE-NEXT: mflr 0 1613; SPE-NEXT: stwu 1, -288(1) 1614; SPE-NEXT: li 5, 256 1615; SPE-NEXT: stw 0, 292(1) 1616; SPE-NEXT: lis 6, .LCPI55_0@ha 1617; SPE-NEXT: evstddx 30, 1, 5 # 8-byte Folded Spill 1618; SPE-NEXT: li 5, .LCPI55_0@l 1619; SPE-NEXT: evlddx 5, 6, 5 1620; SPE-NEXT: stw 31, 284(1) # 4-byte Folded Spill 1621; SPE-NEXT: evstdd 14, 128(1) # 8-byte Folded Spill 1622; SPE-NEXT: evstdd 15, 136(1) # 8-byte Folded Spill 1623; SPE-NEXT: evstdd 16, 144(1) # 8-byte Folded Spill 1624; SPE-NEXT: evstdd 17, 152(1) # 8-byte Folded Spill 1625; SPE-NEXT: evstdd 18, 160(1) # 8-byte Folded Spill 1626; SPE-NEXT: evstdd 19, 168(1) # 8-byte Folded Spill 1627; SPE-NEXT: evstdd 20, 176(1) # 8-byte Folded Spill 1628; SPE-NEXT: evstdd 21, 184(1) # 8-byte Folded Spill 1629; SPE-NEXT: evstdd 22, 192(1) # 8-byte Folded Spill 1630; SPE-NEXT: evstdd 23, 200(1) # 8-byte Folded Spill 1631; SPE-NEXT: evstdd 24, 208(1) # 8-byte Folded Spill 1632; SPE-NEXT: evstdd 25, 216(1) # 8-byte Folded Spill 1633; SPE-NEXT: evstdd 26, 224(1) # 8-byte Folded Spill 1634; SPE-NEXT: evstdd 27, 232(1) # 8-byte Folded Spill 1635; SPE-NEXT: evstdd 28, 240(1) # 8-byte Folded Spill 1636; SPE-NEXT: evstdd 29, 248(1) # 8-byte Folded Spill 1637; SPE-NEXT: evmergelo 3, 3, 4 1638; SPE-NEXT: lwz 4, 296(1) 1639; SPE-NEXT: efdadd 3, 3, 3 1640; SPE-NEXT: efdadd 3, 3, 5 1641; SPE-NEXT: evstdd 3, 24(1) # 8-byte Folded Spill 1642; SPE-NEXT: stw 4, 20(1) # 4-byte Folded Spill 1643; SPE-NEXT: #APP 1644; SPE-NEXT: #NO_APP 1645; SPE-NEXT: addi 3, 1, 76 1646; SPE-NEXT: li 4, 0 1647; SPE-NEXT: li 5, 24 1648; SPE-NEXT: li 6, 1 1649; SPE-NEXT: li 30, 0 1650; SPE-NEXT: bl test_memset 1651; SPE-NEXT: lwz 3, 20(1) # 4-byte Folded Reload 1652; SPE-NEXT: stw 30, 0(3) 1653; SPE-NEXT: bl test_func2 1654; SPE-NEXT: addi 3, 1, 32 1655; SPE-NEXT: li 4, 0 1656; SPE-NEXT: li 5, 20 1657; SPE-NEXT: li 6, 1 1658; SPE-NEXT: bl test_memset 1659; SPE-NEXT: evldd 4, 24(1) # 8-byte Folded Reload 1660; SPE-NEXT: li 5, 256 1661; SPE-NEXT: evmergehi 3, 4, 4 1662; SPE-NEXT: evlddx 30, 1, 5 # 8-byte Folded Reload 1663; SPE-NEXT: evldd 29, 248(1) # 8-byte Folded Reload 1664; SPE-NEXT: evldd 28, 240(1) # 8-byte Folded Reload 1665; SPE-NEXT: evldd 27, 232(1) # 8-byte Folded Reload 1666; SPE-NEXT: evldd 26, 224(1) # 8-byte Folded Reload 1667; SPE-NEXT: evldd 25, 216(1) # 8-byte Folded Reload 1668; SPE-NEXT: evldd 24, 208(1) # 8-byte Folded Reload 1669; SPE-NEXT: evldd 23, 200(1) # 8-byte Folded Reload 1670; SPE-NEXT: evldd 22, 192(1) # 8-byte Folded Reload 1671; SPE-NEXT: evldd 21, 184(1) # 8-byte Folded Reload 1672; SPE-NEXT: evldd 20, 176(1) # 8-byte Folded Reload 1673; SPE-NEXT: evldd 19, 168(1) # 8-byte Folded Reload 1674; SPE-NEXT: evldd 18, 160(1) # 8-byte Folded Reload 1675; SPE-NEXT: evldd 17, 152(1) # 8-byte Folded Reload 1676; SPE-NEXT: evldd 16, 144(1) # 8-byte Folded Reload 1677; SPE-NEXT: evldd 15, 136(1) # 8-byte Folded Reload 1678; SPE-NEXT: evldd 14, 128(1) # 8-byte Folded Reload 1679; SPE-NEXT: lwz 31, 284(1) # 4-byte Folded Reload 1680; SPE-NEXT: lwz 0, 292(1) 1681; SPE-NEXT: addi 1, 1, 288 1682; SPE-NEXT: mtlr 0 1683; SPE-NEXT: blr 1684; 1685; EFPU2-LABEL: test_spill: 1686; EFPU2: # %bb.0: # %entry 1687; EFPU2-NEXT: mflr 0 1688; EFPU2-NEXT: stwu 1, -128(1) 1689; EFPU2-NEXT: mr 5, 3 1690; EFPU2-NEXT: mr 6, 4 1691; EFPU2-NEXT: stw 0, 132(1) 1692; EFPU2-NEXT: stw 27, 108(1) # 4-byte Folded Spill 1693; EFPU2-NEXT: stw 28, 112(1) # 4-byte Folded Spill 1694; EFPU2-NEXT: stw 29, 116(1) # 4-byte Folded Spill 1695; EFPU2-NEXT: stw 30, 120(1) # 4-byte Folded Spill 1696; EFPU2-NEXT: lwz 28, 136(1) 1697; EFPU2-NEXT: bl __adddf3 1698; EFPU2-NEXT: lis 5, 16393 1699; EFPU2-NEXT: lis 6, -4069 1700; EFPU2-NEXT: ori 5, 5, 8697 1701; EFPU2-NEXT: ori 6, 6, 34414 1702; EFPU2-NEXT: #APP 1703; EFPU2-NEXT: #NO_APP 1704; EFPU2-NEXT: bl __adddf3 1705; EFPU2-NEXT: mr 30, 3 1706; EFPU2-NEXT: mr 29, 4 1707; EFPU2-NEXT: addi 3, 1, 56 1708; EFPU2-NEXT: li 4, 0 1709; EFPU2-NEXT: li 5, 24 1710; EFPU2-NEXT: li 6, 1 1711; EFPU2-NEXT: li 27, 0 1712; EFPU2-NEXT: bl test_memset 1713; EFPU2-NEXT: stw 27, 0(28) 1714; EFPU2-NEXT: bl test_func2 1715; EFPU2-NEXT: addi 3, 1, 12 1716; EFPU2-NEXT: li 4, 0 1717; EFPU2-NEXT: li 5, 20 1718; EFPU2-NEXT: li 6, 1 1719; EFPU2-NEXT: bl test_memset 1720; EFPU2-NEXT: mr 3, 30 1721; EFPU2-NEXT: mr 4, 29 1722; EFPU2-NEXT: lwz 30, 120(1) # 4-byte Folded Reload 1723; EFPU2-NEXT: lwz 29, 116(1) # 4-byte Folded Reload 1724; EFPU2-NEXT: lwz 28, 112(1) # 4-byte Folded Reload 1725; EFPU2-NEXT: lwz 27, 108(1) # 4-byte Folded Reload 1726; EFPU2-NEXT: lwz 0, 132(1) 1727; EFPU2-NEXT: addi 1, 1, 128 1728; EFPU2-NEXT: mtlr 0 1729; EFPU2-NEXT: blr 1730entry: 1731 %v1 = alloca [13 x i32], align 4 1732 %v2 = alloca [11 x i32], align 4 1733 %0 = fadd double %a, %a 1734 call void asm sideeffect "","~{s0},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() nounwind 1735 %1 = fadd double %0, 3.14159 1736 call void @test_memset(ptr align 4 %v1, i8 0, i32 24, i1 true) 1737 store i32 0, ptr %a5, align 4 1738 call void @test_func2() 1739 call void @test_memset(ptr align 4 %v2, i8 0, i32 20, i1 true) 1740 br label %return 1741 1742return: 1743 ret double %1 1744 1745} 1746 1747define dso_local float @test_fma(i32 %d) local_unnamed_addr #0 { 1748; CHECK-LABEL: test_fma: 1749; CHECK: # %bb.0: # %entry 1750; CHECK-NEXT: mflr 0 1751; CHECK-NEXT: stwu 1, -32(1) 1752; CHECK-NEXT: cmpwi 3, 0 1753; CHECK-NEXT: stw 0, 36(1) 1754; CHECK-NEXT: stw 29, 20(1) # 4-byte Folded Spill 1755; CHECK-NEXT: stw 30, 24(1) # 4-byte Folded Spill 1756; CHECK-NEXT: ble 0, .LBB56_3 1757; CHECK-NEXT: # %bb.1: # %for.body.preheader 1758; CHECK-NEXT: mr 30, 3 1759; CHECK-NEXT: li 29, 0 1760; CHECK-NEXT: # implicit-def: $r5 1761; CHECK-NEXT: .LBB56_2: # %for.body 1762; CHECK-NEXT: # 1763; CHECK-NEXT: efscfsi 3, 29 1764; CHECK-NEXT: mr 4, 3 1765; CHECK-NEXT: bl fmaf 1766; CHECK-NEXT: addi 30, 30, -1 1767; CHECK-NEXT: mr 5, 3 1768; CHECK-NEXT: cmplwi 30, 0 1769; CHECK-NEXT: addi 29, 29, 1 1770; CHECK-NEXT: bc 12, 1, .LBB56_2 1771; CHECK-NEXT: b .LBB56_4 1772; CHECK-NEXT: .LBB56_3: 1773; CHECK-NEXT: # implicit-def: $r5 1774; CHECK-NEXT: .LBB56_4: # %for.cond.cleanup 1775; CHECK-NEXT: mr 3, 5 1776; CHECK-NEXT: lwz 30, 24(1) # 4-byte Folded Reload 1777; CHECK-NEXT: lwz 29, 20(1) # 4-byte Folded Reload 1778; CHECK-NEXT: lwz 0, 36(1) 1779; CHECK-NEXT: addi 1, 1, 32 1780; CHECK-NEXT: mtlr 0 1781; CHECK-NEXT: blr 1782entry: 1783 %cmp8 = icmp sgt i32 %d, 0 1784 br i1 %cmp8, label %for.body, label %for.cond.cleanup 1785 1786for.cond.cleanup: ; preds = %for.body, %entry 1787 %e.0.lcssa = phi float [ undef, %entry ], [ %0, %for.body ] 1788 ret float %e.0.lcssa 1789 1790for.body: ; preds = %for.body, %entry 1791 %f.010 = phi i32 [ %inc, %for.body ], [ 0, %entry ] 1792 %e.09 = phi float [ %0, %for.body ], [ undef, %entry ] 1793 %conv = sitofp i32 %f.010 to float 1794 %0 = tail call float @llvm.fma.f32(float %conv, float %conv, float %e.09) 1795 %inc = add nuw nsw i32 %f.010, 1 1796 %exitcond = icmp eq i32 %inc, %d 1797 br i1 %exitcond, label %for.cond.cleanup, label %for.body 1798} 1799 1800; Function Attrs: nounwind readnone speculatable willreturn 1801declare float @llvm.fma.f32(float, float, float) #1 1802 1803attributes #1 = { nounwind readnone speculatable willreturn } 1804 1805%struct.a = type { float, float } 1806 1807declare i32 @foo(double) 1808 1809define void @d(ptr %e, ptr %f) #0 { 1810; SPE-LABEL: d: 1811; SPE: # %bb.0: # %entry 1812; SPE-NEXT: mflr 0 1813; SPE-NEXT: stwu 1, -48(1) 1814; SPE-NEXT: stw 0, 52(1) 1815; SPE-NEXT: lwz 4, 0(4) 1816; SPE-NEXT: lwz 3, 0(3) 1817; SPE-NEXT: evstdd 29, 8(1) # 8-byte Folded Spill 1818; SPE-NEXT: efdcfs 29, 4 1819; SPE-NEXT: stw 28, 32(1) # 4-byte Folded Spill 1820; SPE-NEXT: mr 4, 29 1821; SPE-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill 1822; SPE-NEXT: efdcfs 30, 3 1823; SPE-NEXT: evmergehi 3, 29, 29 1824; SPE-NEXT: bl foo 1825; SPE-NEXT: mr 28, 3 1826; SPE-NEXT: evmergehi 3, 30, 30 1827; SPE-NEXT: mr 4, 30 1828; SPE-NEXT: bl foo 1829; SPE-NEXT: efdcfsi 3, 28 1830; SPE-NEXT: evldd 30, 16(1) # 8-byte Folded Reload 1831; SPE-NEXT: efdmul 3, 29, 3 1832; SPE-NEXT: efscfd 3, 3 1833; SPE-NEXT: evldd 29, 8(1) # 8-byte Folded Reload 1834; SPE-NEXT: stw 3, 0(3) 1835; SPE-NEXT: lwz 28, 32(1) # 4-byte Folded Reload 1836; SPE-NEXT: lwz 0, 52(1) 1837; SPE-NEXT: addi 1, 1, 48 1838; SPE-NEXT: mtlr 0 1839; SPE-NEXT: blr 1840; 1841; EFPU2-LABEL: d: 1842; EFPU2: # %bb.0: # %entry 1843; EFPU2-NEXT: mflr 0 1844; EFPU2-NEXT: stwu 1, -32(1) 1845; EFPU2-NEXT: stw 0, 36(1) 1846; EFPU2-NEXT: lwz 3, 0(3) 1847; EFPU2-NEXT: stw 26, 8(1) # 4-byte Folded Spill 1848; EFPU2-NEXT: stw 27, 12(1) # 4-byte Folded Spill 1849; EFPU2-NEXT: stw 28, 16(1) # 4-byte Folded Spill 1850; EFPU2-NEXT: stw 29, 20(1) # 4-byte Folded Spill 1851; EFPU2-NEXT: stw 30, 24(1) # 4-byte Folded Spill 1852; EFPU2-NEXT: mr 30, 4 1853; EFPU2-NEXT: bl __extendsfdf2 1854; EFPU2-NEXT: mr 28, 3 1855; EFPU2-NEXT: lwz 3, 0(30) 1856; EFPU2-NEXT: mr 29, 4 1857; EFPU2-NEXT: bl __extendsfdf2 1858; EFPU2-NEXT: mr 30, 4 1859; EFPU2-NEXT: mr 27, 3 1860; EFPU2-NEXT: bl foo 1861; EFPU2-NEXT: mr 26, 3 1862; EFPU2-NEXT: mr 3, 28 1863; EFPU2-NEXT: mr 4, 29 1864; EFPU2-NEXT: bl foo 1865; EFPU2-NEXT: mr 3, 26 1866; EFPU2-NEXT: bl __floatsidf 1867; EFPU2-NEXT: mr 6, 4 1868; EFPU2-NEXT: mr 5, 3 1869; EFPU2-NEXT: mr 3, 27 1870; EFPU2-NEXT: mr 4, 30 1871; EFPU2-NEXT: bl __muldf3 1872; EFPU2-NEXT: bl __truncdfsf2 1873; EFPU2-NEXT: stw 3, 0(3) 1874; EFPU2-NEXT: lwz 30, 24(1) # 4-byte Folded Reload 1875; EFPU2-NEXT: lwz 29, 20(1) # 4-byte Folded Reload 1876; EFPU2-NEXT: lwz 28, 16(1) # 4-byte Folded Reload 1877; EFPU2-NEXT: lwz 27, 12(1) # 4-byte Folded Reload 1878; EFPU2-NEXT: lwz 26, 8(1) # 4-byte Folded Reload 1879; EFPU2-NEXT: lwz 0, 36(1) 1880; EFPU2-NEXT: addi 1, 1, 32 1881; EFPU2-NEXT: mtlr 0 1882; EFPU2-NEXT: blr 1883entry: 1884 %0 = load float, ptr undef 1885 %conv = fpext float %0 to double 1886 %1 = load float, ptr %f 1887 %g = fpext float %1 to double 1888 %2 = call i32 @foo(double %g) 1889 %h = call i32 @foo(double %conv) 1890 %n = sitofp i32 %2 to double 1891 %k = fmul double %g, %n 1892 %l = fptrunc double %k to float 1893 store float %l, ptr undef 1894 ret void 1895} 1896attributes #0 = { nounwind } 1897