1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \ 3; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \ 4; RUN: -check-prefix=CHECK-LE %s 5; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \ 6; RUN: -mtriple=powerpc-linux-gnu < %s | FileCheck \ 7; RUN: -check-prefix=CHECK-32 %s 8 9define i64 @f0(i64 %x) { 10; CHECK-LE-LABEL: f0: 11; CHECK-LE: # %bb.0: 12; CHECK-LE-NEXT: cmpdi r3, 0 13; CHECK-LE-NEXT: li r3, 125 14; CHECK-LE-NEXT: li r4, -3 15; CHECK-LE-NEXT: isellt r3, r4, r3 16; CHECK-LE-NEXT: blr 17; 18; CHECK-32-LABEL: f0: 19; CHECK-32: # %bb.0: 20; CHECK-32-NEXT: cmpwi r3, 0 21; CHECK-32-NEXT: li r4, -3 22; CHECK-32-NEXT: blt cr0, .LBB0_2 23; CHECK-32-NEXT: # %bb.1: 24; CHECK-32-NEXT: li r4, 125 25; CHECK-32-NEXT: .LBB0_2: 26; CHECK-32-NEXT: srawi r3, r3, 31 27; CHECK-32-NEXT: blr 28 %c = icmp slt i64 %x, 0 29 %r = select i1 %c, i64 -3, i64 125 30 ret i64 %r 31} 32 33define i64 @f1(i64 %x) { 34; CHECK-LE-LABEL: f1: 35; CHECK-LE: # %bb.0: 36; CHECK-LE-NEXT: cmpdi r3, 0 37; CHECK-LE-NEXT: li r3, 512 38; CHECK-LE-NEXT: li r4, 64 39; CHECK-LE-NEXT: isellt r3, r4, r3 40; CHECK-LE-NEXT: blr 41; 42; CHECK-32-LABEL: f1: 43; CHECK-32: # %bb.0: 44; CHECK-32-NEXT: cmpwi r3, 0 45; CHECK-32-NEXT: li r4, 64 46; CHECK-32-NEXT: blt cr0, .LBB1_2 47; CHECK-32-NEXT: # %bb.1: 48; CHECK-32-NEXT: li r4, 512 49; CHECK-32-NEXT: .LBB1_2: 50; CHECK-32-NEXT: li r3, 0 51; CHECK-32-NEXT: blr 52 %c = icmp slt i64 %x, 0 53 %r = select i1 %c, i64 64, i64 512 54 ret i64 %r 55} 56 57define i64 @f2(i64 %x) { 58; CHECK-LE-LABEL: f2: 59; CHECK-LE: # %bb.0: 60; CHECK-LE-NEXT: cmpdi r3, 0 61; CHECK-LE-NEXT: li r3, 1024 62; CHECK-LE-NEXT: iseleq r3, 0, r3 63; CHECK-LE-NEXT: blr 64; 65; CHECK-32-LABEL: f2: 66; CHECK-32: # %bb.0: 67; CHECK-32-NEXT: or. r3, r4, r3 68; CHECK-32-NEXT: li r4, 0 69; CHECK-32-NEXT: bc 12, eq, .LBB2_2 70; CHECK-32-NEXT: # %bb.1: 71; CHECK-32-NEXT: li r4, 1024 72; CHECK-32-NEXT: .LBB2_2: 73; CHECK-32-NEXT: li r3, 0 74; CHECK-32-NEXT: blr 75 %c = icmp eq i64 %x, 0 76 %r = select i1 %c, i64 0, i64 1024 77 ret i64 %r 78} 79 80define i64 @f3(i64 %x, i64 %y) { 81; CHECK-LE-LABEL: f3: 82; CHECK-LE: # %bb.0: 83; CHECK-LE-NEXT: cmpldi r3, 0 84; CHECK-LE-NEXT: iseleq r3, 0, r4 85; CHECK-LE-NEXT: blr 86; 87; CHECK-32-LABEL: f3: 88; CHECK-32: # %bb.0: 89; CHECK-32-NEXT: mr r7, r4 90; CHECK-32-NEXT: or. r3, r7, r3 91; CHECK-32-NEXT: li r4, 0 92; CHECK-32-NEXT: li r3, 0 93; CHECK-32-NEXT: beq cr0, .LBB3_2 94; CHECK-32-NEXT: # %bb.1: 95; CHECK-32-NEXT: mr r3, r5 96; CHECK-32-NEXT: .LBB3_2: 97; CHECK-32-NEXT: beqlr cr0 98; CHECK-32-NEXT: # %bb.3: 99; CHECK-32-NEXT: mr r4, r6 100; CHECK-32-NEXT: blr 101 %c = icmp eq i64 %x, 0 102 %r = select i1 %c, i64 0, i64 %y 103 ret i64 %r 104} 105 106define i64 @f4(i64 %x) { 107; CHECK-LE-LABEL: f4: 108; CHECK-LE: # %bb.0: 109; CHECK-LE-NEXT: sradi r4, r3, 63 110; CHECK-LE-NEXT: xor r3, r3, r4 111; CHECK-LE-NEXT: sub r3, r4, r3 112; CHECK-LE-NEXT: blr 113; 114; CHECK-32-LABEL: f4: 115; CHECK-32: # %bb.0: 116; CHECK-32-NEXT: srawi r5, r3, 31 117; CHECK-32-NEXT: xor r4, r4, r5 118; CHECK-32-NEXT: xor r3, r3, r5 119; CHECK-32-NEXT: subc r4, r5, r4 120; CHECK-32-NEXT: subfe r3, r3, r5 121; CHECK-32-NEXT: blr 122 %c = icmp sgt i64 %x, 0 123 %x.neg = sub i64 0, %x 124 %r = select i1 %c, i64 %x.neg, i64 %x 125 ret i64 %r 126} 127 128define i64 @f4_sge_0(i64 %x) { 129; CHECK-LE-LABEL: f4_sge_0: 130; CHECK-LE: # %bb.0: 131; CHECK-LE-NEXT: cmpdi r3, -1 132; CHECK-LE-NEXT: neg r4, r3 133; CHECK-LE-NEXT: iselgt r3, r4, r3 134; CHECK-LE-NEXT: blr 135; 136; CHECK-32-LABEL: f4_sge_0: 137; CHECK-32: # %bb.0: 138; CHECK-32-NEXT: mr r5, r4 139; CHECK-32-NEXT: subfic r4, r4, 0 140; CHECK-32-NEXT: mr r6, r3 141; CHECK-32-NEXT: cmpwi r3, -1 142; CHECK-32-NEXT: subfze r3, r3 143; CHECK-32-NEXT: bgt cr0, .LBB5_2 144; CHECK-32-NEXT: # %bb.1: 145; CHECK-32-NEXT: mr r3, r6 146; CHECK-32-NEXT: .LBB5_2: 147; CHECK-32-NEXT: bgtlr cr0 148; CHECK-32-NEXT: # %bb.3: 149; CHECK-32-NEXT: mr r4, r5 150; CHECK-32-NEXT: blr 151 %c = icmp sge i64 %x, 0 152 %x.neg = sub i64 0, %x 153 %r = select i1 %c, i64 %x.neg, i64 %x 154 ret i64 %r 155} 156 157define i64 @f4_slt_0(i64 %x) { 158; CHECK-LE-LABEL: f4_slt_0: 159; CHECK-LE: # %bb.0: 160; CHECK-LE-NEXT: sradi r4, r3, 63 161; CHECK-LE-NEXT: xor r3, r3, r4 162; CHECK-LE-NEXT: sub r3, r4, r3 163; CHECK-LE-NEXT: blr 164; 165; CHECK-32-LABEL: f4_slt_0: 166; CHECK-32: # %bb.0: 167; CHECK-32-NEXT: srawi r5, r3, 31 168; CHECK-32-NEXT: xor r4, r4, r5 169; CHECK-32-NEXT: xor r3, r3, r5 170; CHECK-32-NEXT: subc r4, r5, r4 171; CHECK-32-NEXT: subfe r3, r3, r5 172; CHECK-32-NEXT: blr 173 %c = icmp slt i64 %x, 0 174 %x.neg = sub i64 0, %x 175 %r = select i1 %c, i64 %x, i64 %x.neg 176 ret i64 %r 177} 178 179define i64 @f4_sle_0(i64 %x) { 180; CHECK-LE-LABEL: f4_sle_0: 181; CHECK-LE: # %bb.0: 182; CHECK-LE-NEXT: cmpdi r3, 1 183; CHECK-LE-NEXT: neg r4, r3 184; CHECK-LE-NEXT: isellt r3, r3, r4 185; CHECK-LE-NEXT: blr 186; 187; CHECK-32-LABEL: f4_sle_0: 188; CHECK-32: # %bb.0: 189; CHECK-32-NEXT: cmplwi r3, 0 190; CHECK-32-NEXT: cmpwi cr1, r3, 0 191; CHECK-32-NEXT: crandc 4*cr5+lt, 4*cr1+lt, eq 192; CHECK-32-NEXT: cmpwi cr1, r4, 0 193; CHECK-32-NEXT: crand 4*cr5+gt, eq, 4*cr1+eq 194; CHECK-32-NEXT: subfic r5, r4, 0 195; CHECK-32-NEXT: cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt 196; CHECK-32-NEXT: subfze r6, r3 197; CHECK-32-NEXT: bc 12, 4*cr5+lt, .LBB7_2 198; CHECK-32-NEXT: # %bb.1: 199; CHECK-32-NEXT: mr r3, r6 200; CHECK-32-NEXT: .LBB7_2: 201; CHECK-32-NEXT: bclr 12, 4*cr5+lt, 0 202; CHECK-32-NEXT: # %bb.3: 203; CHECK-32-NEXT: mr r4, r5 204; CHECK-32-NEXT: blr 205 %c = icmp sle i64 %x, 0 206 %x.neg = sub i64 0, %x 207 %r = select i1 %c, i64 %x, i64 %x.neg 208 ret i64 %r 209} 210 211define i64 @f4_sgt_m1(i64 %x) { 212; CHECK-LE-LABEL: f4_sgt_m1: 213; CHECK-LE: # %bb.0: 214; CHECK-LE-NEXT: sradi r4, r3, 63 215; CHECK-LE-NEXT: xor r3, r3, r4 216; CHECK-LE-NEXT: sub r3, r4, r3 217; CHECK-LE-NEXT: blr 218; 219; CHECK-32-LABEL: f4_sgt_m1: 220; CHECK-32: # %bb.0: 221; CHECK-32-NEXT: srawi r5, r3, 31 222; CHECK-32-NEXT: xor r4, r4, r5 223; CHECK-32-NEXT: xor r3, r3, r5 224; CHECK-32-NEXT: subc r4, r5, r4 225; CHECK-32-NEXT: subfe r3, r3, r5 226; CHECK-32-NEXT: blr 227 %c = icmp sgt i64 %x, -1 228 %x.neg = sub i64 0, %x 229 %r = select i1 %c, i64 %x.neg, i64 %x 230 ret i64 %r 231} 232 233define i64 @f5(i64 %x, i64 %y) { 234; CHECK-LE-LABEL: f5: 235; CHECK-LE: # %bb.0: 236; CHECK-LE-NEXT: cmpldi r3, 0 237; CHECK-LE-NEXT: li r3, 0 238; CHECK-LE-NEXT: iseleq r3, r4, r3 239; CHECK-LE-NEXT: blr 240; 241; CHECK-32-LABEL: f5: 242; CHECK-32: # %bb.0: 243; CHECK-32-NEXT: or. r3, r4, r3 244; CHECK-32-NEXT: mr r3, r5 245; CHECK-32-NEXT: bne cr0, .LBB9_3 246; CHECK-32-NEXT: # %bb.1: 247; CHECK-32-NEXT: bne cr0, .LBB9_4 248; CHECK-32-NEXT: .LBB9_2: 249; CHECK-32-NEXT: mr r4, r6 250; CHECK-32-NEXT: blr 251; CHECK-32-NEXT: .LBB9_3: 252; CHECK-32-NEXT: li r3, 0 253; CHECK-32-NEXT: beq cr0, .LBB9_2 254; CHECK-32-NEXT: .LBB9_4: 255; CHECK-32-NEXT: li r6, 0 256; CHECK-32-NEXT: mr r4, r6 257; CHECK-32-NEXT: blr 258 %c = icmp eq i64 %x, 0 259 %r = select i1 %c, i64 %y, i64 0 260 ret i64 %r 261} 262 263define i32 @f5_i32(i32 %x, i32 %y) { 264; CHECK-LE-LABEL: f5_i32: 265; CHECK-LE: # %bb.0: 266; CHECK-LE-NEXT: cmplwi r3, 0 267; CHECK-LE-NEXT: li r3, 0 268; CHECK-LE-NEXT: iseleq r3, r4, r3 269; CHECK-LE-NEXT: blr 270; 271; CHECK-32-LABEL: f5_i32: 272; CHECK-32: # %bb.0: 273; CHECK-32-NEXT: cmplwi r3, 0 274; CHECK-32-NEXT: mr r3, r4 275; CHECK-32-NEXT: beqlr cr0 276; CHECK-32-NEXT: # %bb.1: 277; CHECK-32-NEXT: li r3, 0 278; CHECK-32-NEXT: blr 279 %c = icmp eq i32 %x, 0 280 %r = select i1 %c, i32 %y, i32 0 281 ret i32 %r 282} 283 284define i64 @f6(i64 %x) { 285; CHECK-LE-LABEL: f6: 286; CHECK-LE: # %bb.0: 287; CHECK-LE-NEXT: cntlzd r3, r3 288; CHECK-LE-NEXT: rldicl r3, r3, 58, 63 289; CHECK-LE-NEXT: blr 290; 291; CHECK-32-LABEL: f6: 292; CHECK-32: # %bb.0: 293; CHECK-32-NEXT: or r3, r4, r3 294; CHECK-32-NEXT: cntlzw r3, r3 295; CHECK-32-NEXT: rlwinm r4, r3, 27, 31, 31 296; CHECK-32-NEXT: li r3, 0 297; CHECK-32-NEXT: blr 298 %c = icmp ne i64 %x, 0 299 %r = select i1 %c, i64 0, i64 1 300 ret i64 %r 301} 302 303define i32 @f6_i32(i32 %x) { 304; CHECK-LE-LABEL: f6_i32: 305; CHECK-LE: # %bb.0: 306; CHECK-LE-NEXT: cntlzw r3, r3 307; CHECK-LE-NEXT: srwi r3, r3, 5 308; CHECK-LE-NEXT: blr 309; 310; CHECK-32-LABEL: f6_i32: 311; CHECK-32: # %bb.0: 312; CHECK-32-NEXT: cntlzw r3, r3 313; CHECK-32-NEXT: rlwinm r3, r3, 27, 31, 31 314; CHECK-32-NEXT: blr 315 %c = icmp ne i32 %x, 0 316 %r = select i1 %c, i32 0, i32 1 317 ret i32 %r 318} 319