1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 3; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9LE 4; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 5; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P9BE 6; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 7; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8LE 8; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \ 9; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s --check-prefix=P8BE 10 11define i8 @scalar_to_vector_half(ptr nocapture readonly %ad) { 12; P9LE-LABEL: scalar_to_vector_half: 13; P9LE: # %bb.0: # %entry 14; P9LE-NEXT: lxsihzx v2, 0, r3 15; P9LE-NEXT: li r3, 0 16; P9LE-NEXT: vsplth v2, v2, 3 17; P9LE-NEXT: vextubrx r3, r3, v2 18; P9LE-NEXT: blr 19; 20; P9BE-LABEL: scalar_to_vector_half: 21; P9BE: # %bb.0: # %entry 22; P9BE-NEXT: lxsihzx v2, 0, r3 23; P9BE-NEXT: li r3, 0 24; P9BE-NEXT: vsplth v2, v2, 3 25; P9BE-NEXT: vextublx r3, r3, v2 26; P9BE-NEXT: blr 27; 28; P8LE-LABEL: scalar_to_vector_half: 29; P8LE: # %bb.0: # %entry 30; P8LE-NEXT: lhz r3, 0(r3) 31; P8LE-NEXT: mtfprd f0, r3 32; P8LE-NEXT: mffprd r3, f0 33; P8LE-NEXT: clrldi r3, r3, 56 34; P8LE-NEXT: blr 35; 36; P8BE-LABEL: scalar_to_vector_half: 37; P8BE: # %bb.0: # %entry 38; P8BE-NEXT: lhz r3, 0(r3) 39; P8BE-NEXT: sldi r3, r3, 48 40; P8BE-NEXT: mtfprd f0, r3 41; P8BE-NEXT: mffprd r3, f0 42; P8BE-NEXT: rldicl r3, r3, 8, 56 43; P8BE-NEXT: blr 44entry: 45 %0 = load <2 x i8>, ptr %ad, align 1 46 %1 = extractelement <2 x i8> %0, i32 0 47 ret i8 %1 48} 49 50