xref: /llvm-project/llvm/test/CodeGen/PowerPC/pzero-fp-xored.ll (revision 1e15e24a761a73f8b2762c33b34e0ce937d8183f)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx -mcpu=pwr8 < %s |  \
3; RUN:   FileCheck %s --implicit-check-not lxvd2x --implicit-check-not lfs
4; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=-altivec -mcpu=pwr8 -mattr=-vsx < %s | \
5; RUN:   FileCheck %s --check-prefix=CHECK-NVSXALT --implicit-check-not xxlxor \
6; RUN:                                             --implicit-check-not vxor
7
8define signext i32 @t1(float %x) local_unnamed_addr #0 {
9; CHECK-LABEL: t1:
10; CHECK:       # %bb.0: # %entry
11; CHECK-NEXT:    xxlxor 0, 0, 0
12; CHECK-NEXT:    li 3, 11
13; CHECK-NEXT:    li 4, 43
14; CHECK-NEXT:    fcmpu 0, 1, 0
15; CHECK-NEXT:    iselgt 3, 4, 3
16; CHECK-NEXT:    blr
17;
18; CHECK-NVSXALT-LABEL: t1:
19; CHECK-NVSXALT:       # %bb.0: # %entry
20; CHECK-NVSXALT-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
21; CHECK-NVSXALT-NEXT:    li 4, 43
22; CHECK-NVSXALT-NEXT:    lfs 0, .LCPI0_0@toc@l(3)
23; CHECK-NVSXALT-NEXT:    li 3, 11
24; CHECK-NVSXALT-NEXT:    fcmpu 0, 1, 0
25; CHECK-NVSXALT-NEXT:    iselgt 3, 4, 3
26; CHECK-NVSXALT-NEXT:    blr
27entry:
28  %cmp = fcmp ogt float %x, 0.000000e+00
29  %tmp = select i1 %cmp, i32 43, i32 11
30  ret i32 %tmp
31
32}
33
34define signext i32 @t2(double %x) local_unnamed_addr #0 {
35; CHECK-LABEL: t2:
36; CHECK:       # %bb.0: # %entry
37; CHECK-NEXT:    xxlxor 0, 0, 0
38; CHECK-NEXT:    li 3, 11
39; CHECK-NEXT:    li 4, 43
40; CHECK-NEXT:    xscmpudp 0, 1, 0
41; CHECK-NEXT:    iselgt 3, 4, 3
42; CHECK-NEXT:    blr
43;
44; CHECK-NVSXALT-LABEL: t2:
45; CHECK-NVSXALT:       # %bb.0: # %entry
46; CHECK-NVSXALT-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
47; CHECK-NVSXALT-NEXT:    li 4, 43
48; CHECK-NVSXALT-NEXT:    lfs 0, .LCPI1_0@toc@l(3)
49; CHECK-NVSXALT-NEXT:    li 3, 11
50; CHECK-NVSXALT-NEXT:    fcmpu 0, 1, 0
51; CHECK-NVSXALT-NEXT:    iselgt 3, 4, 3
52; CHECK-NVSXALT-NEXT:    blr
53entry:
54  %cmp = fcmp ogt double %x, 0.000000e+00
55  %tmp = select i1 %cmp, i32 43, i32 11
56  ret i32 %tmp
57
58}
59
60define signext i32 @t3(ppc_fp128 %x) local_unnamed_addr #0 {
61; CHECK-LABEL: t3:
62; CHECK:       # %bb.0: # %entry
63; CHECK-NEXT:    xxlxor 0, 0, 0
64; CHECK-NEXT:    li 3, 11
65; CHECK-NEXT:    li 4, 43
66; CHECK-NEXT:    fcmpu 0, 2, 0
67; CHECK-NEXT:    fcmpu 1, 1, 0
68; CHECK-NEXT:    crand 20, 6, 1
69; CHECK-NEXT:    cror 20, 5, 20
70; CHECK-NEXT:    isel 3, 4, 3, 20
71; CHECK-NEXT:    blr
72;
73; CHECK-NVSXALT-LABEL: t3:
74; CHECK-NVSXALT:       # %bb.0: # %entry
75; CHECK-NVSXALT-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
76; CHECK-NVSXALT-NEXT:    li 4, 43
77; CHECK-NVSXALT-NEXT:    lfs 0, .LCPI2_0@toc@l(3)
78; CHECK-NVSXALT-NEXT:    li 3, 11
79; CHECK-NVSXALT-NEXT:    fcmpu 0, 2, 0
80; CHECK-NVSXALT-NEXT:    fcmpu 1, 1, 0
81; CHECK-NVSXALT-NEXT:    crand 20, 6, 1
82; CHECK-NVSXALT-NEXT:    cror 20, 5, 20
83; CHECK-NVSXALT-NEXT:    isel 3, 4, 3, 20
84; CHECK-NVSXALT-NEXT:    blr
85entry:
86  %cmp = fcmp ogt ppc_fp128 %x, 0xM00000000000000000000000000000000
87  %tmp = select i1 %cmp, i32 43, i32 11
88  ret i32 %tmp
89
90}
91
92define <2 x double> @t4() local_unnamed_addr #0 {
93; CHECK-LABEL: t4:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    xxlxor 34, 34, 34
96; CHECK-NEXT:    blr
97;
98; CHECK-NVSXALT-LABEL: t4:
99; CHECK-NVSXALT:       # %bb.0:
100; CHECK-NVSXALT-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
101; CHECK-NVSXALT-NEXT:    lfs 1, .LCPI3_0@toc@l(3)
102; CHECK-NVSXALT-NEXT:    fmr 2, 1
103; CHECK-NVSXALT-NEXT:    blr
104  ret <2 x double> zeroinitializer
105}
106
107define <2 x i64> @t5() local_unnamed_addr #0 {
108; CHECK-LABEL: t5:
109; CHECK:       # %bb.0:
110; CHECK-NEXT:    xxlxor 34, 34, 34
111; CHECK-NEXT:    blr
112;
113; CHECK-NVSXALT-LABEL: t5:
114; CHECK-NVSXALT:       # %bb.0:
115; CHECK-NVSXALT-NEXT:    li 3, 0
116; CHECK-NVSXALT-NEXT:    li 4, 0
117; CHECK-NVSXALT-NEXT:    blr
118  ret <2 x i64> zeroinitializer
119}
120