xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr85066.ll (revision 47fd32f81c593ae698765e3f3f13998ac9a9abbf)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2; RUN: llc -mtriple=powerpc64le < %s | FileCheck %s
3
4; Tests from pr85066
5define i64 @test_shl_zext_cttz(i16 %x) {
6; CHECK-LABEL: test_shl_zext_cttz:
7; CHECK:       # %bb.0: # %entry
8; CHECK-NEXT:    oris 3, 3, 1
9; CHECK-NEXT:    neg 4, 3
10; CHECK-NEXT:    and 3, 3, 4
11; CHECK-NEXT:    clrldi 3, 3, 32
12; CHECK-NEXT:    blr
13entry:
14  %cttz = tail call i16 @llvm.cttz.i16(i16 %x, i1 false)
15  %zext = zext i16 %cttz to i64
16  %res = shl i64 1, %zext
17  ret i64 %res
18}
19
20define i64 @test_shl_zext_cttz_zero_is_poison(i16 %x) {
21; CHECK-LABEL: test_shl_zext_cttz_zero_is_poison:
22; CHECK:       # %bb.0: # %entry
23; CHECK-NEXT:    neg 4, 3
24; CHECK-NEXT:    and 3, 3, 4
25; CHECK-NEXT:    clrldi 3, 3, 32
26; CHECK-NEXT:    blr
27entry:
28  %cttz = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
29  %zext = zext i16 %cttz to i64
30  %res = shl i64 1, %zext
31  ret i64 %res
32}
33
34define i16 @test_shl_trunc_cttz(i32 %x) {
35; CHECK-LABEL: test_shl_trunc_cttz:
36; CHECK:       # %bb.0: # %entry
37; CHECK-NEXT:    neg 4, 3
38; CHECK-NEXT:    and 3, 3, 4
39; CHECK-NEXT:    blr
40entry:
41  %cttz = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
42  %trunc = trunc i32 %cttz to i16
43  %res = shl i16 1, %trunc
44  ret i16 %res
45}
46