xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr61882.ll (revision 69b056d5638bbe3c8098b5d3a4980eb9929b9bbe)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mtriple=powerpc \
3; RUN:   -mcpu=pwr7 < %s | FileCheck %s
4; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -mtriple=powerpc \
5; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=PWR8
6
7define void @foo(ptr %a, i32 %x) {
8; CHECK-LABEL: foo:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    rlwinm r5, r3, 3, 27, 28
11; CHECK-NEXT:    extsb r4, r4
12; CHECK-NEXT:    li r6, 255
13; CHECK-NEXT:    sync
14; CHECK-NEXT:    rlwinm r3, r3, 0, 0, 29
15; CHECK-NEXT:    xori r5, r5, 24
16; CHECK-NEXT:    slw r7, r4, r5
17; CHECK-NEXT:    slw r6, r6, r5
18; CHECK-NEXT:    and r7, r7, r6
19; CHECK-NEXT:  .LBB0_1:
20; CHECK-NEXT:    lwarx r8, 0, r3
21; CHECK-NEXT:    and r9, r8, r6
22; CHECK-NEXT:    srw r9, r9, r5
23; CHECK-NEXT:    extsb r9, r9
24; CHECK-NEXT:    cmpw r9, r4
25; CHECK-NEXT:    bgt cr0, .LBB0_3
26; CHECK-NEXT:  # %bb.2:
27; CHECK-NEXT:    andc r8, r8, r6
28; CHECK-NEXT:    or r8, r7, r8
29; CHECK-NEXT:    stwcx. r8, 0, r3
30; CHECK-NEXT:    bne cr0, .LBB0_1
31; CHECK-NEXT:  .LBB0_3:
32; CHECK-NEXT:    lwsync
33; CHECK-NEXT:    blr
34;
35; PWR8-LABEL: foo:
36; PWR8:       # %bb.0:
37; PWR8-NEXT:    sync
38; PWR8-NEXT:    extsb r4, r4
39; PWR8-NEXT:  .LBB0_1:
40; PWR8-NEXT:    lbarx r5, 0, r3
41; PWR8-NEXT:    extsb r5, r5
42; PWR8-NEXT:    cmpw r5, r4
43; PWR8-NEXT:    bgt cr0, .LBB0_3
44; PWR8-NEXT:  # %bb.2:
45; PWR8-NEXT:    stbcx. r4, 0, r3
46; PWR8-NEXT:    bne cr0, .LBB0_1
47; PWR8-NEXT:  .LBB0_3:
48; PWR8-NEXT:    lwsync
49; PWR8-NEXT:    blr
50  %val = trunc i32 %x to i8
51  %1 = atomicrmw max ptr %a, i8 %val seq_cst
52  ret void
53}
54