1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown \ 3; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s 4define dso_local void @_Z1jjPiPj() local_unnamed_addr #0 { 5; CHECK-LABEL: _Z1jjPiPj: 6; CHECK: # %bb.0: # %entry 7; CHECK-NEXT: ld r3, 0(r3) 8; CHECK-NEXT: std r3, -16(r1) 9; CHECK-NEXT: addi r3, r1, -16 10; CHECK-NEXT: lxvd2x vs0, 0, r3 11; CHECK-NEXT: xxswapd vs0, vs0 12; CHECK-NEXT: xxmrglw vs0, vs0, vs0 13; CHECK-NEXT: xxswapd vs0, vs0 14; CHECK-NEXT: stxvd2x vs0, 0, r3 15; CHECK-NEXT: blr 16entry: 17 %wide.load42 = load <2 x i32>, ptr undef, align 4 18 %interleaved.vec49 = shufflevector <2 x i32> %wide.load42, <2 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3> 19 store <4 x i32> %interleaved.vec49, ptr undef, align 4 20 ret void 21} 22