1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \ 3; RUN: FileCheck %s 4 5; With MemorySSA, everything is taken out of the loop by licm. 6; Loads and stores to undef are treated as non-aliasing. 7define void @ec_GFp_nistp256_points_mul() { 8; CHECK-LABEL: ec_GFp_nistp256_points_mul: 9; CHECK: # %bb.0: # %entry 10; CHECK-NEXT: ld 3, 0(3) 11; CHECK-NEXT: li 4, 0 12; CHECK-NEXT: subfic 5, 3, 0 13; CHECK-NEXT: subfze 5, 4 14; CHECK-NEXT: sradi 5, 5, 63 15; CHECK-NEXT: subc 3, 5, 3 16; CHECK-NEXT: subfe 3, 4, 5 17; CHECK-NEXT: sradi 3, 3, 63 18; CHECK-NEXT: std 3, 0(3) 19; CHECK-NEXT: .p2align 4 20; CHECK-NEXT: .LBB0_1: # %fe_cmovznz.exit.i534.i.15 21; CHECK-NEXT: # 22; CHECK-NEXT: b .LBB0_1 23 24entry: 25 br label %fe_cmovznz.exit.i534.i.15 26 27fe_cmovznz.exit.i534.i.15: ; preds = %fe_cmovznz.exit.i534.i.15, %entry 28 %0 = load i64, ptr undef, align 8 29 %1 = load i64, ptr undef, align 8 30 %conv.i69.i.i = zext i64 %0 to i128 31 %sub.i72.i.i = sub nsw i128 0, %conv.i69.i.i 32 %conv.i63.i.i = zext i64 %1 to i128 33 %add.neg.i.i.i = ashr i128 %sub.i72.i.i, 127 34 %sub.i65.i.i = sub nsw i128 %add.neg.i.i.i, %conv.i63.i.i 35 %sub.i65.lobit.i.i = ashr i128 %sub.i65.i.i, 127 36 %conv1.i58.i.i = and i128 %sub.i65.lobit.i.i, 18446744073709551615 37 %add3.i59.i.i = add nuw nsw i128 %conv1.i58.i.i, 0 38 %conv4.i60.i.i = trunc i128 %add3.i59.i.i to i64 39 store i64 %conv4.i60.i.i, ptr undef, align 16 40 br label %fe_cmovznz.exit.i534.i.15 41} 42 43