1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE 4 5define <8 x i16> @pr25080(<8 x i32> %a) { 6; LE-LABEL: pr25080: 7; LE: # %bb.0: # %entry 8; LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha 9; LE-NEXT: xxlxor 36, 36, 36 10; LE-NEXT: addi 3, 3, .LCPI0_0@toc@l 11; LE-NEXT: lxvd2x 0, 0, 3 12; LE-NEXT: xxland 34, 34, 0 13; LE-NEXT: xxland 35, 35, 0 14; LE-NEXT: vcmpequw 2, 2, 4 15; LE-NEXT: vcmpequw 3, 3, 4 16; LE-NEXT: xxswapd 1, 34 17; LE-NEXT: xxsldwi 2, 34, 34, 1 18; LE-NEXT: xxsldwi 3, 34, 34, 3 19; LE-NEXT: xxswapd 0, 35 20; LE-NEXT: xxsldwi 4, 35, 35, 1 21; LE-NEXT: xxsldwi 5, 35, 35, 3 22; LE-NEXT: mffprwz 3, 1 23; LE-NEXT: mtvsrd 36, 3 24; LE-NEXT: mffprwz 3, 2 25; LE-NEXT: mtvsrd 37, 3 26; LE-NEXT: mfvsrwz 3, 34 27; LE-NEXT: mtvsrd 34, 3 28; LE-NEXT: mffprwz 3, 3 29; LE-NEXT: vmrghh 4, 5, 4 30; LE-NEXT: mtvsrd 37, 3 31; LE-NEXT: mffprwz 3, 0 32; LE-NEXT: vmrghh 2, 5, 2 33; LE-NEXT: mtvsrd 37, 3 34; LE-NEXT: mffprwz 3, 4 35; LE-NEXT: mtvsrd 32, 3 36; LE-NEXT: mfvsrwz 3, 35 37; LE-NEXT: mtvsrd 35, 3 38; LE-NEXT: mffprwz 3, 5 39; LE-NEXT: xxmrglw 0, 34, 36 40; LE-NEXT: vmrghh 5, 0, 5 41; LE-NEXT: mtvsrd 32, 3 42; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha 43; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l 44; LE-NEXT: vmrghh 3, 0, 3 45; LE-NEXT: xxmrglw 1, 35, 37 46; LE-NEXT: xxmrgld 34, 1, 0 47; LE-NEXT: lxvd2x 0, 0, 3 48; LE-NEXT: xxswapd 35, 0 49; LE-NEXT: xxlor 34, 34, 35 50; LE-NEXT: blr 51; 52; BE-LABEL: pr25080: 53; BE: # %bb.0: # %entry 54; BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha 55; BE-NEXT: xxlxor 36, 36, 36 56; BE-NEXT: addi 3, 3, .LCPI0_0@toc@l 57; BE-NEXT: lxvw4x 0, 0, 3 58; BE-NEXT: addis 3, 2, .LCPI0_1@toc@ha 59; BE-NEXT: addi 3, 3, .LCPI0_1@toc@l 60; BE-NEXT: xxland 35, 35, 0 61; BE-NEXT: xxland 34, 34, 0 62; BE-NEXT: vcmpequw 3, 3, 4 63; BE-NEXT: vcmpequw 2, 2, 4 64; BE-NEXT: lxvw4x 36, 0, 3 65; BE-NEXT: xxswapd 1, 35 66; BE-NEXT: xxsldwi 2, 35, 35, 1 67; BE-NEXT: xxsldwi 3, 35, 35, 3 68; BE-NEXT: xxswapd 0, 34 69; BE-NEXT: xxsldwi 4, 34, 34, 1 70; BE-NEXT: xxsldwi 5, 34, 34, 3 71; BE-NEXT: mffprwz 3, 1 72; BE-NEXT: mtvsrwz 37, 3 73; BE-NEXT: mffprwz 3, 2 74; BE-NEXT: mtvsrwz 32, 3 75; BE-NEXT: mfvsrwz 3, 35 76; BE-NEXT: mtvsrwz 35, 3 77; BE-NEXT: mffprwz 3, 3 78; BE-NEXT: vperm 5, 0, 5, 4 79; BE-NEXT: mtvsrwz 32, 3 80; BE-NEXT: mffprwz 3, 0 81; BE-NEXT: vperm 3, 0, 3, 4 82; BE-NEXT: mtvsrwz 32, 3 83; BE-NEXT: mffprwz 3, 4 84; BE-NEXT: mtvsrwz 33, 3 85; BE-NEXT: mfvsrwz 3, 34 86; BE-NEXT: mtvsrwz 34, 3 87; BE-NEXT: mffprwz 3, 5 88; BE-NEXT: xxmrghw 0, 35, 37 89; BE-NEXT: vperm 0, 1, 0, 4 90; BE-NEXT: mtvsrwz 33, 3 91; BE-NEXT: addis 3, 2, .LCPI0_2@toc@ha 92; BE-NEXT: addi 3, 3, .LCPI0_2@toc@l 93; BE-NEXT: vperm 2, 1, 2, 4 94; BE-NEXT: xxmrghw 1, 34, 32 95; BE-NEXT: xxmrghd 34, 1, 0 96; BE-NEXT: lxvw4x 0, 0, 3 97; BE-NEXT: xxlor 34, 34, 0 98; BE-NEXT: blr 99entry: 100 %0 = trunc <8 x i32> %a to <8 x i23> 101 %1 = icmp eq <8 x i23> %0, zeroinitializer 102 %2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false> 103 %3 = sext <8 x i1> %2 to <8 x i16> 104 ret <8 x i16> %3 105} 106