xref: /llvm-project/llvm/test/CodeGen/PowerPC/pr22711.ll (revision 732f63d96dc5b2cc5a5ad4e1db16bb3b4297fa24)
1; Verify that the .toc section is aligned on an 8-byte boundary.
2
3; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
4; RUN: -mcpu=pwr8 -filetype=obj -ppc-min-jump-table-entries=4 -o - | llvm-readobj --sections - | FileCheck %s
5
6define void @test(ptr %a) {
7entry:
8  %a.addr = alloca ptr, align 8
9  store ptr %a, ptr %a.addr, align 8
10  %0 = load ptr,  ptr %a.addr, align 8
11  %incdec.ptr = getelementptr inbounds i32, ptr %0, i32 1
12  store ptr %incdec.ptr, ptr %a.addr, align 8
13  %1 = load i32,  ptr %0, align 4
14  switch i32 %1, label %sw.epilog [
15    i32 17, label %sw.bb
16    i32 13, label %sw.bb1
17    i32 11, label %sw.bb2
18    i32 7, label %sw.bb3
19    i32 5, label %sw.bb4
20    i32 3, label %sw.bb5
21    i32 2, label %sw.bb6
22  ]
23
24sw.bb:                                            ; preds = %entry
25  %2 = load ptr,  ptr %a.addr, align 8
26  store i32 2, ptr %2, align 4
27  br label %sw.epilog
28
29sw.bb1:                                           ; preds = %entry
30  %3 = load ptr,  ptr %a.addr, align 8
31  store i32 3, ptr %3, align 4
32  br label %sw.epilog
33
34sw.bb2:                                           ; preds = %entry
35  %4 = load ptr,  ptr %a.addr, align 8
36  store i32 5, ptr %4, align 4
37  br label %sw.epilog
38
39sw.bb3:                                           ; preds = %entry
40  %5 = load ptr,  ptr %a.addr, align 8
41  store i32 7, ptr %5, align 4
42  br label %sw.epilog
43
44sw.bb4:                                           ; preds = %entry
45  %6 = load ptr,  ptr %a.addr, align 8
46  store i32 11, ptr %6, align 4
47  br label %sw.epilog
48
49sw.bb5:                                           ; preds = %entry
50  %7 = load ptr,  ptr %a.addr, align 8
51  store i32 13, ptr %7, align 4
52  br label %sw.epilog
53
54sw.bb6:                                           ; preds = %entry
55  %8 = load ptr,  ptr %a.addr, align 8
56  store i32 17, ptr %8, align 4
57  br label %sw.epilog
58
59sw.epilog:                                        ; preds = %entry, %sw.bb6, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
60  ret void
61}
62
63; CHECK: Name: .toc
64; CHECK: AddressAlignment: 8
65; CHECK: Name: .rela.toc
66
67; This test was generated from the following from PR22711:
68
69;void test(int *a) {
70;  switch (*a++) {
71;  case 17: *a =  2; break;
72;  case 13: *a =  3; break;
73;  case 11: *a =  5; break;
74;  case  7: *a =  7; break;
75;  case  5: *a = 11; break;
76;  case  3: *a = 13; break;
77;  case  2: *a = 17; break;
78;  }
79;}
80