xref: /llvm-project/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll (revision 8e901c255df45e38cb1d69a576804029e20868bf)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
3; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=-isel < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
4target datalayout = "E-m:e-i64:64-n32:64"
5target triple = "powerpc64-unknown-linux-gnu"
6
7; Function Attrs: nounwind
8define void @foo(ptr nocapture %r1, ptr nocapture %r2, ptr nocapture %r3, ptr nocapture %r4, i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) #0 {
9; Make sure that we don't schedule all of the isels together, they should be
10; intermixed with the adds because each isel starts a new dispatch group.
11; CHECK-LABEL: foo:
12; CHECK:       # %bb.0: # %entry
13; CHECK-NEXT:    cmplwi 7, 0
14; CHECK-NEXT:    addi 7, 8, 1
15; CHECK-NEXT:    iseleq 9, 9, 8
16; CHECK-NEXT:    stw 9, 0(3)
17; CHECK-NEXT:    addi 3, 10, -2
18; CHECK-NEXT:    iseleq 9, 10, 8
19; CHECK-NEXT:    iseleq 3, 3, 7
20; CHECK-NEXT:    stw 9, 0(4)
21; CHECK-NEXT:    addi 4, 10, -5
22; CHECK-NEXT:    stw 3, 0(5)
23; CHECK-NEXT:    addi 3, 8, 3
24; CHECK-NEXT:    iseleq 3, 4, 3
25; CHECK-NEXT:    stw 3, 0(6)
26; CHECK-NEXT:    blr
27;
28; CHECK-NO-ISEL-LABEL: foo:
29; CHECK-NO-ISEL:       # %bb.0: # %entry
30; CHECK-NO-ISEL-NEXT:    cmplwi 7, 0
31; CHECK-NO-ISEL-NEXT:    mr 7, 8
32; CHECK-NO-ISEL-NEXT:    bne 0, .LBB0_2
33; CHECK-NO-ISEL-NEXT:  # %bb.1: # %entry
34; CHECK-NO-ISEL-NEXT:    mr 7, 9
35; CHECK-NO-ISEL-NEXT:  .LBB0_2: # %entry
36; CHECK-NO-ISEL-NEXT:    stw 7, 0(3)
37; CHECK-NO-ISEL-NEXT:    mr 3, 8
38; CHECK-NO-ISEL-NEXT:    bne 0, .LBB0_4
39; CHECK-NO-ISEL-NEXT:  # %bb.3: # %entry
40; CHECK-NO-ISEL-NEXT:    mr 3, 10
41; CHECK-NO-ISEL-NEXT:  .LBB0_4: # %entry
42; CHECK-NO-ISEL-NEXT:    stw 3, 0(4)
43; CHECK-NO-ISEL-NEXT:    bne 0, .LBB0_7
44; CHECK-NO-ISEL-NEXT:  # %bb.5: # %entry
45; CHECK-NO-ISEL-NEXT:    addi 3, 10, -2
46; CHECK-NO-ISEL-NEXT:    stw 3, 0(5)
47; CHECK-NO-ISEL-NEXT:    beq 0, .LBB0_8
48; CHECK-NO-ISEL-NEXT:  .LBB0_6:
49; CHECK-NO-ISEL-NEXT:    addi 3, 8, 3
50; CHECK-NO-ISEL-NEXT:    stw 3, 0(6)
51; CHECK-NO-ISEL-NEXT:    blr
52; CHECK-NO-ISEL-NEXT:  .LBB0_7:
53; CHECK-NO-ISEL-NEXT:    addi 3, 8, 1
54; CHECK-NO-ISEL-NEXT:    stw 3, 0(5)
55; CHECK-NO-ISEL-NEXT:    bne 0, .LBB0_6
56; CHECK-NO-ISEL-NEXT:  .LBB0_8: # %entry
57; CHECK-NO-ISEL-NEXT:    addi 3, 10, -5
58; CHECK-NO-ISEL-NEXT:    stw 3, 0(6)
59; CHECK-NO-ISEL-NEXT:    blr
60entry:
61  %tobool = icmp ne i32 %a, 0
62  %cond = select i1 %tobool, i32 %b, i32 %c
63  store i32 %cond, ptr %r1, align 4
64  %cond5 = select i1 %tobool, i32 %b, i32 %d
65  store i32 %cond5, ptr %r2, align 4
66  %add = add nsw i32 %b, 1
67  %sub = add nsw i32 %d, -2
68  %cond10 = select i1 %tobool, i32 %add, i32 %sub
69  store i32 %cond10, ptr %r3, align 4
70  %add13 = add nsw i32 %b, 3
71  %sub15 = add nsw i32 %d, -5
72  %cond17 = select i1 %tobool, i32 %add13, i32 %sub15
73  store i32 %cond17, ptr %r4, align 4
74  ret void
75}
76
77attributes #0 = { nounwind }
78