13136cbe2SAlbion Fung; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 23136cbe2SAlbion Fung; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 33136cbe2SAlbion Fung; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 43136cbe2SAlbion Fung; RUN: FileCheck %s 53136cbe2SAlbion Fung 63136cbe2SAlbion Fung; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 73136cbe2SAlbion Fung; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 83136cbe2SAlbion Fung; RUN: FileCheck %s 93136cbe2SAlbion Fung 103136cbe2SAlbion Fung; These test cases demonstrate that the vector shift quadword instructions 113136cbe2SAlbion Fung; introduced within Power10 are correctly exploited. 123136cbe2SAlbion Fung 133136cbe2SAlbion Fungdefine dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) { 143136cbe2SAlbion Fung; CHECK-LABEL: test_vec_vslq: 153136cbe2SAlbion Fung; CHECK: # %bb.0: # %entry 16*cb0c034eSStefan Pintilie; CHECK-NEXT: xxswapd v3, v3 173136cbe2SAlbion Fung; CHECK-NEXT: vslq v2, v2, v3 183136cbe2SAlbion Fung; CHECK-NEXT: blr 193136cbe2SAlbion Fungentry: 203136cbe2SAlbion Fung %rem = urem <1 x i128> %b, <i128 128> 213136cbe2SAlbion Fung %shl = shl <1 x i128> %a, %rem 223136cbe2SAlbion Fung ret <1 x i128> %shl 233136cbe2SAlbion Fung} 243136cbe2SAlbion Fung 253136cbe2SAlbion Fungdefine dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) { 263136cbe2SAlbion Fung; CHECK-LABEL: test_vec_vsrq: 273136cbe2SAlbion Fung; CHECK: # %bb.0: # %entry 28*cb0c034eSStefan Pintilie; CHECK-NEXT: xxswapd v3, v3 293136cbe2SAlbion Fung; CHECK-NEXT: vsrq v2, v2, v3 303136cbe2SAlbion Fung; CHECK-NEXT: blr 313136cbe2SAlbion Fungentry: 323136cbe2SAlbion Fung %rem = urem <1 x i128> %b, <i128 128> 333136cbe2SAlbion Fung %shr = lshr <1 x i128> %a, %rem 343136cbe2SAlbion Fung ret <1 x i128> %shr 353136cbe2SAlbion Fung} 363136cbe2SAlbion Fung 373136cbe2SAlbion Fungdefine dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) { 383136cbe2SAlbion Fung; CHECK-LABEL: test_vec_vsraq: 393136cbe2SAlbion Fung; CHECK: # %bb.0: # %entry 40*cb0c034eSStefan Pintilie; CHECK-NEXT: xxswapd v3, v3 413136cbe2SAlbion Fung; CHECK-NEXT: vsraq v2, v2, v3 423136cbe2SAlbion Fung; CHECK-NEXT: blr 433136cbe2SAlbion Fungentry: 443136cbe2SAlbion Fung %rem = urem <1 x i128> %b, <i128 128> 453136cbe2SAlbion Fung %shr = ashr <1 x i128> %a, %rem 463136cbe2SAlbion Fung ret <1 x i128> %shr 473136cbe2SAlbion Fung} 483136cbe2SAlbion Fung 493136cbe2SAlbion Fungdefine dso_local <1 x i128> @test_vec_vslq2(<1 x i128> %a, <1 x i128> %b) { 503136cbe2SAlbion Fung; CHECK-LABEL: test_vec_vslq2: 513136cbe2SAlbion Fung; CHECK: # %bb.0: # %entry 52*cb0c034eSStefan Pintilie; CHECK-NEXT: xxswapd v3, v3 533136cbe2SAlbion Fung; CHECK-NEXT: vslq v2, v2, v3 543136cbe2SAlbion Fung; CHECK-NEXT: blr 553136cbe2SAlbion Fungentry: 563136cbe2SAlbion Fung %shl = shl <1 x i128> %a, %b 573136cbe2SAlbion Fung ret <1 x i128> %shl 583136cbe2SAlbion Fung} 593136cbe2SAlbion Fung 603136cbe2SAlbion Fungdefine dso_local <1 x i128> @test_vec_vsrq2(<1 x i128> %a, <1 x i128> %b) { 613136cbe2SAlbion Fung; CHECK-LABEL: test_vec_vsrq2: 623136cbe2SAlbion Fung; CHECK: # %bb.0: # %entry 63*cb0c034eSStefan Pintilie; CHECK-NEXT: xxswapd v3, v3 643136cbe2SAlbion Fung; CHECK-NEXT: vsrq v2, v2, v3 653136cbe2SAlbion Fung; CHECK-NEXT: blr 663136cbe2SAlbion Fungentry: 673136cbe2SAlbion Fung %shr = lshr <1 x i128> %a, %b 683136cbe2SAlbion Fung ret <1 x i128> %shr 693136cbe2SAlbion Fung} 703136cbe2SAlbion Fung 713136cbe2SAlbion Fungdefine dso_local <1 x i128> @test_vec_vsraq2(<1 x i128> %a, <1 x i128> %b) { 723136cbe2SAlbion Fung; CHECK-LABEL: test_vec_vsraq2: 733136cbe2SAlbion Fung; CHECK: # %bb.0: # %entry 74*cb0c034eSStefan Pintilie; CHECK-NEXT: xxswapd v3, v3 753136cbe2SAlbion Fung; CHECK-NEXT: vsraq v2, v2, v3 763136cbe2SAlbion Fung; CHECK-NEXT: blr 773136cbe2SAlbion Fungentry: 783136cbe2SAlbion Fung %shr = ashr <1 x i128> %a, %b 793136cbe2SAlbion Fung ret <1 x i128> %shr 803136cbe2SAlbion Fung} 81