1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s 5 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 7; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 8; RUN: FileCheck %s 9 10; These test cases demonstrate that the vector shift quadword instructions 11; introduced within Power10 are correctly exploited. 12 13define dso_local <1 x i128> @test_vec_vslq(<1 x i128> %a, <1 x i128> %b) { 14; CHECK-LABEL: test_vec_vslq: 15; CHECK: # %bb.0: # %entry 16; CHECK-NEXT: xxswapd v3, v3 17; CHECK-NEXT: vslq v2, v2, v3 18; CHECK-NEXT: blr 19entry: 20 %rem = urem <1 x i128> %b, <i128 128> 21 %shl = shl <1 x i128> %a, %rem 22 ret <1 x i128> %shl 23} 24 25define dso_local <1 x i128> @test_vec_vsrq(<1 x i128> %a, <1 x i128> %b) { 26; CHECK-LABEL: test_vec_vsrq: 27; CHECK: # %bb.0: # %entry 28; CHECK-NEXT: xxswapd v3, v3 29; CHECK-NEXT: vsrq v2, v2, v3 30; CHECK-NEXT: blr 31entry: 32 %rem = urem <1 x i128> %b, <i128 128> 33 %shr = lshr <1 x i128> %a, %rem 34 ret <1 x i128> %shr 35} 36 37define dso_local <1 x i128> @test_vec_vsraq(<1 x i128> %a, <1 x i128> %b) { 38; CHECK-LABEL: test_vec_vsraq: 39; CHECK: # %bb.0: # %entry 40; CHECK-NEXT: xxswapd v3, v3 41; CHECK-NEXT: vsraq v2, v2, v3 42; CHECK-NEXT: blr 43entry: 44 %rem = urem <1 x i128> %b, <i128 128> 45 %shr = ashr <1 x i128> %a, %rem 46 ret <1 x i128> %shr 47} 48 49define dso_local <1 x i128> @test_vec_vslq2(<1 x i128> %a, <1 x i128> %b) { 50; CHECK-LABEL: test_vec_vslq2: 51; CHECK: # %bb.0: # %entry 52; CHECK-NEXT: xxswapd v3, v3 53; CHECK-NEXT: vslq v2, v2, v3 54; CHECK-NEXT: blr 55entry: 56 %shl = shl <1 x i128> %a, %b 57 ret <1 x i128> %shl 58} 59 60define dso_local <1 x i128> @test_vec_vsrq2(<1 x i128> %a, <1 x i128> %b) { 61; CHECK-LABEL: test_vec_vsrq2: 62; CHECK: # %bb.0: # %entry 63; CHECK-NEXT: xxswapd v3, v3 64; CHECK-NEXT: vsrq v2, v2, v3 65; CHECK-NEXT: blr 66entry: 67 %shr = lshr <1 x i128> %a, %b 68 ret <1 x i128> %shr 69} 70 71define dso_local <1 x i128> @test_vec_vsraq2(<1 x i128> %a, <1 x i128> %b) { 72; CHECK-LABEL: test_vec_vsraq2: 73; CHECK: # %bb.0: # %entry 74; CHECK-NEXT: xxswapd v3, v3 75; CHECK-NEXT: vsraq v2, v2, v3 76; CHECK-NEXT: blr 77entry: 78 %shr = ashr <1 x i128> %a, %b 79 ret <1 x i128> %shr 80} 81