1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s -check-prefixes=CHECK,CHECK-LE 5 6; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 7; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 8; RUN: FileCheck %s -check-prefixes=CHECK,CHECK-BE 9 10; This test case aims to test the builtins for vector rotate instructions 11; on Power10. 12 13 14define <1 x i128> @test_vrlq(<1 x i128> %x, <1 x i128> %y) { 15; CHECK-LABEL: test_vrlq: 16; CHECK: # %bb.0: 17; CHECK-NEXT: vrlq v2, v3, v2 18; CHECK-NEXT: blr 19 %shl.i = shl <1 x i128> %y, %x 20 %sub.i = sub <1 x i128> <i128 128>, %x 21 %lshr.i = lshr <1 x i128> %y, %sub.i 22 %tmp = or <1 x i128> %shl.i, %lshr.i 23 ret <1 x i128> %tmp 24} 25 26define <1 x i128> @test_vrlq_cost_mult8(<1 x i128> %x) { 27; CHECK-LE-LABEL: test_vrlq_cost_mult8: 28; CHECK-LE: # %bb.0: 29; CHECK-LE-NEXT: plxv v3, .LCPI1_0@PCREL(0), 1 30; CHECK-LE-NEXT: vrlq v2, v3, v2 31; CHECK-LE-NEXT: blr 32; 33; CHECK-BE-LABEL: test_vrlq_cost_mult8: 34; CHECK-BE: # %bb.0: 35; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha 36; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l 37; CHECK-BE-NEXT: lxv v3, 0(r3) 38; CHECK-BE-NEXT: vrlq v2, v3, v2 39; CHECK-BE-NEXT: blr 40 %shl.i = shl <1 x i128> <i128 16>, %x 41 %sub.i = sub <1 x i128> <i128 128>, %x 42 %lshr.i = lshr <1 x i128> <i128 16>, %sub.i 43 %tmp = or <1 x i128> %shl.i, %lshr.i 44 ret <1 x i128> %tmp 45} 46 47define <1 x i128> @test_vrlq_cost_non_mult8(<1 x i128> %x) { 48; CHECK-LE-LABEL: test_vrlq_cost_non_mult8: 49; CHECK-LE: # %bb.0: 50; CHECK-LE-NEXT: plxv v3, .LCPI2_0@PCREL(0), 1 51; CHECK-LE-NEXT: vrlq v2, v3, v2 52; CHECK-LE-NEXT: blr 53; 54; CHECK-BE-LABEL: test_vrlq_cost_non_mult8: 55; CHECK-BE: # %bb.0: 56; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha 57; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l 58; CHECK-BE-NEXT: lxv v3, 0(r3) 59; CHECK-BE-NEXT: vrlq v2, v3, v2 60; CHECK-BE-NEXT: blr 61 %shl.i = shl <1 x i128> <i128 4>, %x 62 %sub.i = sub <1 x i128> <i128 128>, %x 63 %lshr.i = lshr <1 x i128> <i128 4>, %sub.i 64 %tmp = or <1 x i128> %shl.i, %lshr.i 65 ret <1 x i128> %tmp 66} 67 68; Function Attrs: nounwind readnone 69define <1 x i128> @test_vrlqmi(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) { 70; CHECK-LABEL: test_vrlqmi: 71; CHECK: # %bb.0: # %entry 72; CHECK-NEXT: vrlqmi v3, v2, v4 73; CHECK-NEXT: vmr v2, v3 74; CHECK-NEXT: blr 75entry: 76 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128> %a, <1 x i128> %c, <1 x i128> %b) 77 ret <1 x i128> %tmp 78} 79 80; Function Attrs: nounwind readnone 81define <1 x i128> @test_vrlqnm(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) { 82; CHECK-LE-LABEL: test_vrlqnm: 83; CHECK-LE: # %bb.0: # %entry 84; CHECK-LE-NEXT: plxv vs0, .LCPI4_0@PCREL(0), 1 85; CHECK-LE-NEXT: xxperm v3, v4, vs0 86; CHECK-LE-NEXT: vrlqnm v2, v2, v3 87; CHECK-LE-NEXT: blr 88; 89; CHECK-BE-LABEL: test_vrlqnm: 90; CHECK-BE: # %bb.0: # %entry 91; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha 92; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l 93; CHECK-BE-NEXT: lxv vs0, 0(r3) 94; CHECK-BE-NEXT: xxperm v4, v3, vs0 95; CHECK-BE-NEXT: vrlqnm v2, v2, v4 96; CHECK-BE-NEXT: blr 97entry: 98 %0 = bitcast <1 x i128> %b to <16 x i8> 99 %1 = bitcast <1 x i128> %c to <16 x i8> 100 %shuffle.i = shufflevector <16 x i8> %0, <16 x i8> %1, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 16, i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> 101 %d = bitcast <16 x i8> %shuffle.i to <1 x i128> 102 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128> %a, <1 x i128> %d) 103 ret <1 x i128> %tmp 104} 105 106; Function Attrs: nounwind readnone 107declare <1 x i128> @llvm.ppc.altivec.vrlqmi(<1 x i128>, <1 x i128>, <1 x i128>) 108 109; Function Attrs: nounwind readnone 110declare <1 x i128> @llvm.ppc.altivec.vrlqnm(<1 x i128>, <1 x i128>) 111