1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 4; RUN: FileCheck %s 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 7; RUN: FileCheck %s 8; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \ 9; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ 10; RUN: FileCheck %s 11 12; This test case aims to test the vector divide instructions on Power10. 13; This includes the low order and extended versions of vector divide, 14; that operate on signed and unsigned words and doublewords. 15; This also includes 128 bit vector divide instructions. 16 17define <2 x i64> @test_vdivud(<2 x i64> %a, <2 x i64> %b) { 18; CHECK-LABEL: test_vdivud: 19; CHECK: # %bb.0: # %entry 20; CHECK-NEXT: vdivud v2, v2, v3 21; CHECK-NEXT: blr 22entry: 23 %div = udiv <2 x i64> %a, %b 24 ret <2 x i64> %div 25} 26 27define <2 x i64> @test_vdivsd(<2 x i64> %a, <2 x i64> %b) { 28; CHECK-LABEL: test_vdivsd: 29; CHECK: # %bb.0: # %entry 30; CHECK-NEXT: vdivsd v2, v2, v3 31; CHECK-NEXT: blr 32entry: 33 %div = sdiv <2 x i64> %a, %b 34 ret <2 x i64> %div 35} 36 37define <4 x i32> @test_vdivuw(<4 x i32> %a, <4 x i32> %b) { 38; CHECK-LABEL: test_vdivuw: 39; CHECK: # %bb.0: # %entry 40; CHECK-NEXT: vdivuw v2, v2, v3 41; CHECK-NEXT: blr 42entry: 43 %div = udiv <4 x i32> %a, %b 44 ret <4 x i32> %div 45} 46 47define <4 x i32> @test_vdivsw(<4 x i32> %a, <4 x i32> %b) { 48; CHECK-LABEL: test_vdivsw: 49; CHECK: # %bb.0: # %entry 50; CHECK-NEXT: vdivsw v2, v2, v3 51; CHECK-NEXT: blr 52entry: 53 %div = sdiv <4 x i32> %a, %b 54 ret <4 x i32> %div 55} 56 57; Test the vector divide extended intrinsics. 58declare <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32>, <4 x i32>) 59declare <4 x i32> @llvm.ppc.altivec.vdiveuw(<4 x i32>, <4 x i32>) 60declare <2 x i64> @llvm.ppc.altivec.vdivesd(<2 x i64>, <2 x i64>) 61declare <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64>, <2 x i64>) 62 63define <4 x i32> @test_vdivesw(<4 x i32> %a, <4 x i32> %b) { 64; CHECK-LABEL: test_vdivesw: 65; CHECK: # %bb.0: # %entry 66; CHECK-NEXT: vdivesw v2, v2, v3 67; CHECK-NEXT: blr 68entry: 69 %div = tail call <4 x i32> @llvm.ppc.altivec.vdivesw(<4 x i32> %a, <4 x i32> %b) 70 ret <4 x i32> %div 71} 72 73define <4 x i32> @test_vdiveuw(<4 x i32> %a, <4 x i32> %b) { 74; CHECK-LABEL: test_vdiveuw: 75; CHECK: # %bb.0: # %entry 76; CHECK-NEXT: vdiveuw v2, v2, v3 77; CHECK-NEXT: blr 78entry: 79 %div = tail call <4 x i32> @llvm.ppc.altivec.vdiveuw(<4 x i32> %a, <4 x i32> %b) 80 ret <4 x i32> %div 81} 82 83define <1 x i128> @test_vdivsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone { 84; CHECK-LABEL: test_vdivsq: 85; CHECK: # %bb.0: 86; CHECK-NEXT: vdivsq v2, v2, v3 87; CHECK-NEXT: blr 88 %tmp = sdiv <1 x i128> %x, %y 89 ret <1 x i128> %tmp 90} 91 92define <1 x i128> @test_vdivuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone { 93; CHECK-LABEL: test_vdivuq: 94; CHECK: # %bb.0: 95; CHECK-NEXT: vdivuq v2, v2, v3 96; CHECK-NEXT: blr 97 %tmp = udiv <1 x i128> %x, %y 98 ret <1 x i128> %tmp 99} 100 101define <2 x i64> @test_vdivesd(<2 x i64> %a, <2 x i64> %b) { 102; CHECK-LABEL: test_vdivesd: 103; CHECK: # %bb.0: # %entry 104; CHECK-NEXT: vdivesd v2, v2, v3 105; CHECK-NEXT: blr 106entry: 107 %div = tail call <2 x i64> @llvm.ppc.altivec.vdivesd(<2 x i64> %a, <2 x i64> %b) 108 ret <2 x i64> %div 109} 110 111define <2 x i64> @test_vdiveud(<2 x i64> %a, <2 x i64> %b) { 112; CHECK-LABEL: test_vdiveud: 113; CHECK: # %bb.0: # %entry 114; CHECK-NEXT: vdiveud v2, v2, v3 115; CHECK-NEXT: blr 116entry: 117 %div = tail call <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64> %a, <2 x i64> %b) 118 ret <2 x i64> %div 119} 120 121declare <1 x i128> @llvm.ppc.altivec.vdivesq(<1 x i128>, <1 x i128>) nounwind readnone 122declare <1 x i128> @llvm.ppc.altivec.vdiveuq(<1 x i128>, <1 x i128>) nounwind readnone 123 124define <1 x i128> @test_vdivesq(<1 x i128> %x, <1 x i128> %y) nounwind readnone { 125; CHECK-LABEL: test_vdivesq: 126; CHECK: # %bb.0: 127; CHECK-NEXT: vdivesq v2, v2, v3 128; CHECK-NEXT: blr 129 %tmp = tail call <1 x i128> @llvm.ppc.altivec.vdivesq(<1 x i128> %x, <1 x i128> %y) 130 ret <1 x i128> %tmp 131} 132 133 134define <1 x i128> @test_vdiveuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone { 135; CHECK-LABEL: test_vdiveuq: 136; CHECK: # %bb.0: 137; CHECK-NEXT: vdiveuq v2, v2, v3 138; CHECK-NEXT: blr 139 %tmp = call <1 x i128> @llvm.ppc.altivec.vdiveuq(<1 x i128> %x, <1 x i128> %y) 140 ret <1 x i128> %tmp 141} 142