xref: /llvm-project/llvm/test/CodeGen/PowerPC/mulld.ll (revision b922a3621116b404d868af8b74cab25ab78555be)
1; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
3; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
4; RUN: --check-prefix=CHECK-ITIN
5; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
6; RUN: --check-prefix=CHECK-ITIN
7; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s \
8; RUN: --check-prefix=CHECK-ITIN
9
10define void @bn_mul_comba8(ptr nocapture %r, ptr nocapture readonly %a, ptr nocapture readonly %b) {
11; CHECK-LABEL: bn_mul_comba8:
12; CHECK:    mulhdu
13; CHECK-NEXT:    mulld
14; CHECK:         mulhdu
15; CHECK:         mulld
16; CHECK-NEXT:    mulhdu
17
18
19; CHECK-ITIN-LABEL: bn_mul_comba8:
20; CHECK-ITIN:    mulhdu
21; CHECK-ITIN-NEXT:    mulld
22; CHECK-ITIN-NEXT:    mulhdu
23; CHECK-ITIN:    mulld
24; CHECK-ITIN-NEXT:    mulhdu
25
26  %1 = load i64, ptr %a, align 8
27  %conv = zext i64 %1 to i128
28  %2 = load i64, ptr %b, align 8
29  %conv2 = zext i64 %2 to i128
30  %mul = mul nuw i128 %conv2, %conv
31  %shr = lshr i128 %mul, 64
32  %agep = getelementptr inbounds i64, ptr %a, i64 1
33  %3 = load i64, ptr %agep, align 8
34  %conv14 = zext i64 %3 to i128
35  %mul15 = mul nuw i128 %conv14, %conv
36  %add17 = add i128 %mul15, %shr
37  %shr19 = lshr i128 %add17, 64
38  %conv20 = trunc i128 %shr19 to i64
39  %bgep = getelementptr inbounds i64, ptr %b, i64 1
40  %4 = load i64, ptr %bgep, align 8
41  %conv28 = zext i64 %4 to i128
42  %mul31 = mul nuw i128 %conv28, %conv2
43  %conv32 = and i128 %add17, 18446744073709551615
44  %add33 = add i128 %conv32, %mul31
45  %shr35 = lshr i128 %add33, 64
46  %conv36 = trunc i128 %shr35 to i64
47  %add37 = add i64 %conv36, %conv20
48  %cmp38 = icmp ult i64 %add37, %conv36
49  %conv148 = zext i1 %cmp38 to i64
50  store i64 %conv148, ptr %r, align 8
51  ret void
52}
53
54