1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ 3; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ 4; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ 6; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \ 7; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE 8 9; Function Attrs: nofree nounwind writeonly 10define dso_local void @test1(ptr nocapture readnone %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) { 11; CHECK-LABEL: test1: 12; CHECK: # %bb.0: # %entry 13; CHECK-NEXT: xvi16ger2 acc0, v2, v2 14; CHECK-NEXT: xxmfacc acc0 15; CHECK-NEXT: stxv vs0, 48(r7) 16; CHECK-NEXT: stxv vs1, 32(r7) 17; CHECK-NEXT: stxv vs2, 16(r7) 18; CHECK-NEXT: stxv vs3, 0(r7) 19; CHECK-NEXT: blr 20; 21; CHECK-BE-LABEL: test1: 22; CHECK-BE: # %bb.0: # %entry 23; CHECK-BE-NEXT: xvi16ger2 acc0, v2, v2 24; CHECK-BE-NEXT: xxmfacc acc0 25; CHECK-BE-NEXT: stxv vs1, 16(r7) 26; CHECK-BE-NEXT: stxv vs0, 0(r7) 27; CHECK-BE-NEXT: stxv vs3, 48(r7) 28; CHECK-BE-NEXT: stxv vs2, 32(r7) 29; CHECK-BE-NEXT: blr 30entry: 31 %0 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8> %vc, <16 x i8> %vc) 32 store <512 x i1> %0, ptr %resp, align 64 33 ret void 34} 35 36; Function Attrs: nounwind readnone 37declare <512 x i1> @llvm.ppc.mma.xvi16ger2(<16 x i8>, <16 x i8>) 38 39; Function Attrs: nofree nounwind writeonly 40define dso_local void @test2(ptr nocapture readnone %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) { 41; CHECK-LABEL: test2: 42; CHECK: # %bb.0: # %entry 43; CHECK-NEXT: pmxvi16ger2 acc0, v2, v2, 0, 0, 0 44; CHECK-NEXT: xxmfacc acc0 45; CHECK-NEXT: stxv vs0, 48(r7) 46; CHECK-NEXT: stxv vs1, 32(r7) 47; CHECK-NEXT: stxv vs2, 16(r7) 48; CHECK-NEXT: stxv vs3, 0(r7) 49; CHECK-NEXT: blr 50; 51; CHECK-BE-LABEL: test2: 52; CHECK-BE: # %bb.0: # %entry 53; CHECK-BE-NEXT: pmxvi16ger2 acc0, v2, v2, 0, 0, 0 54; CHECK-BE-NEXT: xxmfacc acc0 55; CHECK-BE-NEXT: stxv vs1, 16(r7) 56; CHECK-BE-NEXT: stxv vs0, 0(r7) 57; CHECK-BE-NEXT: stxv vs3, 48(r7) 58; CHECK-BE-NEXT: stxv vs2, 32(r7) 59; CHECK-BE-NEXT: blr 60entry: 61 %0 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) 62 store <512 x i1> %0, ptr %resp, align 64 63 ret void 64} 65 66; Function Attrs: nounwind readnone 67declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2(<16 x i8>, <16 x i8>, i32, i32, i32) 68 69; Function Attrs: nofree nounwind 70define dso_local void @test3(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) { 71; CHECK-LABEL: test3: 72; CHECK: # %bb.0: # %entry 73; CHECK-NEXT: lxv vs1, 32(r3) 74; CHECK-NEXT: lxv vs0, 48(r3) 75; CHECK-NEXT: lxv vs3, 0(r3) 76; CHECK-NEXT: lxv vs2, 16(r3) 77; CHECK-NEXT: xxmtacc acc0 78; CHECK-NEXT: xvi8ger4spp acc0, v2, v2 79; CHECK-NEXT: xxmfacc acc0 80; CHECK-NEXT: stxv vs0, 48(r7) 81; CHECK-NEXT: stxv vs1, 32(r7) 82; CHECK-NEXT: stxv vs2, 16(r7) 83; CHECK-NEXT: stxv vs3, 0(r7) 84; CHECK-NEXT: blr 85; 86; CHECK-BE-LABEL: test3: 87; CHECK-BE: # %bb.0: # %entry 88; CHECK-BE-NEXT: lxv vs1, 16(r3) 89; CHECK-BE-NEXT: lxv vs0, 0(r3) 90; CHECK-BE-NEXT: lxv vs3, 48(r3) 91; CHECK-BE-NEXT: lxv vs2, 32(r3) 92; CHECK-BE-NEXT: xxmtacc acc0 93; CHECK-BE-NEXT: xvi8ger4spp acc0, v2, v2 94; CHECK-BE-NEXT: xxmfacc acc0 95; CHECK-BE-NEXT: stxv vs1, 16(r7) 96; CHECK-BE-NEXT: stxv vs0, 0(r7) 97; CHECK-BE-NEXT: stxv vs3, 48(r7) 98; CHECK-BE-NEXT: stxv vs2, 32(r7) 99; CHECK-BE-NEXT: blr 100entry: 101 %0 = load <512 x i1>, ptr %vqp, align 64 102 %1 = tail call <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc) 103 store <512 x i1> %1, ptr %resp, align 64 104 ret void 105} 106 107; Function Attrs: nounwind readnone 108declare <512 x i1> @llvm.ppc.mma.xvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>) 109 110; Function Attrs: nofree nounwind 111define dso_local void @test4(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) { 112; CHECK-LABEL: test4: 113; CHECK: # %bb.0: # %entry 114; CHECK-NEXT: lxv vs1, 32(r3) 115; CHECK-NEXT: lxv vs0, 48(r3) 116; CHECK-NEXT: lxv vs3, 0(r3) 117; CHECK-NEXT: lxv vs2, 16(r3) 118; CHECK-NEXT: xxmtacc acc0 119; CHECK-NEXT: xvi16ger2pp acc0, v2, v2 120; CHECK-NEXT: xxmfacc acc0 121; CHECK-NEXT: stxv vs0, 48(r7) 122; CHECK-NEXT: stxv vs1, 32(r7) 123; CHECK-NEXT: stxv vs2, 16(r7) 124; CHECK-NEXT: stxv vs3, 0(r7) 125; CHECK-NEXT: blr 126; 127; CHECK-BE-LABEL: test4: 128; CHECK-BE: # %bb.0: # %entry 129; CHECK-BE-NEXT: lxv vs1, 16(r3) 130; CHECK-BE-NEXT: lxv vs0, 0(r3) 131; CHECK-BE-NEXT: lxv vs3, 48(r3) 132; CHECK-BE-NEXT: lxv vs2, 32(r3) 133; CHECK-BE-NEXT: xxmtacc acc0 134; CHECK-BE-NEXT: xvi16ger2pp acc0, v2, v2 135; CHECK-BE-NEXT: xxmfacc acc0 136; CHECK-BE-NEXT: stxv vs1, 16(r7) 137; CHECK-BE-NEXT: stxv vs0, 0(r7) 138; CHECK-BE-NEXT: stxv vs3, 48(r7) 139; CHECK-BE-NEXT: stxv vs2, 32(r7) 140; CHECK-BE-NEXT: blr 141entry: 142 %0 = load <512 x i1>, ptr %vqp, align 64 143 %1 = tail call <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc) 144 store <512 x i1> %1, ptr %resp, align 64 145 ret void 146} 147 148; Function Attrs: nounwind readnone 149declare <512 x i1> @llvm.ppc.mma.xvi16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>) 150 151; Function Attrs: nofree nounwind 152define dso_local void @test5(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) { 153; CHECK-LABEL: test5: 154; CHECK: # %bb.0: # %entry 155; CHECK-NEXT: lxv vs1, 32(r3) 156; CHECK-NEXT: lxv vs0, 48(r3) 157; CHECK-NEXT: lxv vs3, 0(r3) 158; CHECK-NEXT: lxv vs2, 16(r3) 159; CHECK-NEXT: xxmtacc acc0 160; CHECK-NEXT: pmxvi8ger4spp acc0, v2, v2, 0, 0, 0 161; CHECK-NEXT: xxmfacc acc0 162; CHECK-NEXT: stxv vs0, 48(r7) 163; CHECK-NEXT: stxv vs1, 32(r7) 164; CHECK-NEXT: stxv vs2, 16(r7) 165; CHECK-NEXT: stxv vs3, 0(r7) 166; CHECK-NEXT: blr 167; 168; CHECK-BE-LABEL: test5: 169; CHECK-BE: # %bb.0: # %entry 170; CHECK-BE-NEXT: lxv vs1, 16(r3) 171; CHECK-BE-NEXT: lxv vs0, 0(r3) 172; CHECK-BE-NEXT: lxv vs3, 48(r3) 173; CHECK-BE-NEXT: lxv vs2, 32(r3) 174; CHECK-BE-NEXT: xxmtacc acc0 175; CHECK-BE-NEXT: pmxvi8ger4spp acc0, v2, v2, 0, 0, 0 176; CHECK-BE-NEXT: xxmfacc acc0 177; CHECK-BE-NEXT: stxv vs1, 16(r7) 178; CHECK-BE-NEXT: stxv vs0, 0(r7) 179; CHECK-BE-NEXT: stxv vs3, 48(r7) 180; CHECK-BE-NEXT: stxv vs2, 32(r7) 181; CHECK-BE-NEXT: blr 182entry: 183 %0 = load <512 x i1>, ptr %vqp, align 64 184 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) 185 store <512 x i1> %1, ptr %resp, align 64 186 ret void 187} 188 189; Function Attrs: nounwind readnone 190declare <512 x i1> @llvm.ppc.mma.pmxvi8ger4spp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) 191 192; Function Attrs: nofree nounwind 193define dso_local void @test6(ptr nocapture readonly %vqp, ptr nocapture readnone %vpp, <16 x i8> %vc, ptr nocapture %resp) { 194; CHECK-LABEL: test6: 195; CHECK: # %bb.0: # %entry 196; CHECK-NEXT: lxv vs1, 32(r3) 197; CHECK-NEXT: lxv vs0, 48(r3) 198; CHECK-NEXT: lxv vs3, 0(r3) 199; CHECK-NEXT: lxv vs2, 16(r3) 200; CHECK-NEXT: xxmtacc acc0 201; CHECK-NEXT: pmxvi16ger2pp acc0, v2, v2, 0, 0, 0 202; CHECK-NEXT: xxmfacc acc0 203; CHECK-NEXT: stxv vs0, 48(r7) 204; CHECK-NEXT: stxv vs1, 32(r7) 205; CHECK-NEXT: stxv vs2, 16(r7) 206; CHECK-NEXT: stxv vs3, 0(r7) 207; CHECK-NEXT: blr 208; 209; CHECK-BE-LABEL: test6: 210; CHECK-BE: # %bb.0: # %entry 211; CHECK-BE-NEXT: lxv vs1, 16(r3) 212; CHECK-BE-NEXT: lxv vs0, 0(r3) 213; CHECK-BE-NEXT: lxv vs3, 48(r3) 214; CHECK-BE-NEXT: lxv vs2, 32(r3) 215; CHECK-BE-NEXT: xxmtacc acc0 216; CHECK-BE-NEXT: pmxvi16ger2pp acc0, v2, v2, 0, 0, 0 217; CHECK-BE-NEXT: xxmfacc acc0 218; CHECK-BE-NEXT: stxv vs1, 16(r7) 219; CHECK-BE-NEXT: stxv vs0, 0(r7) 220; CHECK-BE-NEXT: stxv vs3, 48(r7) 221; CHECK-BE-NEXT: stxv vs2, 32(r7) 222; CHECK-BE-NEXT: blr 223entry: 224 %0 = load <512 x i1>, ptr %vqp, align 64 225 %1 = tail call <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc, i32 0, i32 0, i32 0) 226 store <512 x i1> %1, ptr %resp, align 64 227 ret void 228} 229 230; Function Attrs: nounwind readnone 231declare <512 x i1> @llvm.ppc.mma.pmxvi16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>, i32, i32, i32) 232