1; RUN: llc -verify-machineinstrs < %s -enable-misched -pre-RA-sched=source -scheditins=false \ 2; RUN: -disable-ifcvt-triangle-false -disable-post-ra -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s 3; 4target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" 5 6; %val1 is a load live out of %entry. It should be hoisted 7; above the add. 8; CHECK-LABEL: testload: 9; CHECK: %entry 10; CHECK: lwz 11; CHECK: addi 12; CHECK: bne 13; CHECK: %true 14define i32 @testload(ptr %ptr, i32 %sumin) { 15entry: 16 %sum1 = add i32 %sumin, 1 17 %val1 = load i32, ptr %ptr 18 %p = icmp eq i32 %sumin, 0 19 br i1 %p, label %true, label %end, !prof !1 20true: 21 %sum2 = add i32 %sum1, 1 22 %ptr2 = getelementptr i32, ptr %ptr, i32 1 23 %val = load i32, ptr %ptr2 24 %val2 = add i32 %val1, %val 25 br label %end 26end: 27 %valmerge = phi i32 [ %val1, %entry], [ %val2, %true ] 28 %summerge = phi i32 [ %sum1, %entry], [ %sum2, %true ] 29 %sumout = add i32 %valmerge, %summerge 30 ret i32 %sumout 31} 32 33; The prefetch gets a default latency of 3 cycles and should be hoisted 34; above the add. 35; 36; CHECK-LABEL: testprefetch: 37; CHECK: %entry 38; CHECK: dcbt 39; CHECK: addi 40; CHECK: blr 41define i32 @testprefetch(ptr %ptr, i32 %i) { 42entry: 43 %val1 = add i32 %i, 1 44 tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 3, i32 1 ) 45 %p = icmp eq i32 %i, 0 46 br i1 %p, label %true, label %end 47true: 48 %val2 = add i32 %val1, 1 49 br label %end 50end: 51 %valmerge = phi i32 [ %val1, %entry], [ %val2, %true ] 52 ret i32 %valmerge 53} 54declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind 55 56!1 = !{!"branch_weights", i32 2, i32 1} 57