xref: /llvm-project/llvm/test/CodeGen/PowerPC/mem-rr-addr-mode.ll (revision 427fb35192f1f7bb694a5910b05abc5925a798b2)
1; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | grep li.*16
2; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | not grep addi
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4; Codegen lvx (R+16) as t = li 16,  lvx t,R
5; This shares the 16 between the two loads.
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7define void @func(ptr %a, ptr %b) {
8        %tmp1 = getelementptr <4 x float>, ptr %b, i32 1            ; <ptr> [#uses=1]
9        %tmp = load <4 x float>, ptr %tmp1          ; <<4 x float>> [#uses=1]
10        %tmp3 = getelementptr <4 x float>, ptr %a, i32 1            ; <ptr> [#uses=1]
11        %tmp4 = load <4 x float>, ptr %tmp3         ; <<4 x float>> [#uses=1]
12        %tmp5 = fmul <4 x float> %tmp, %tmp4             ; <<4 x float>> [#uses=1]
13        %tmp8 = load <4 x float>, ptr %b            ; <<4 x float>> [#uses=1]
14        %tmp9 = fadd <4 x float> %tmp5, %tmp8            ; <<4 x float>> [#uses=1]
15        store <4 x float> %tmp9, ptr %a
16        ret void
17}
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