1# REQUIRES: asserts 2# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 -x=mir < %s \ 3# RUN: -debug-only=machine-scheduler -start-before=postmisched 2>&1 \ 4# RUN: -mattr=+fuse-zeromove,+fuse-cmp,+fuse-wideimm,+fuse-back2back \ 5# RUN: | FileCheck %s 6 7# CHECK: add_mulld:%bb.0 8# CHECK: Macro fuse: SU(0) - SU(1) / MULLD - ADD8 9--- 10name: add_mulld 11tracksRegLiveness: true 12body: | 13 bb.0.entry: 14 liveins: $x3, $x4, $x5 15 renamable $x4 = MULLD $x3, $x4 16 renamable $x3 = ADD8 killed renamable $x4, $x5 17 BLR8 implicit $lr8, implicit $rm, implicit $x3 18... 19 20# CHECK: add_and:%bb.0 21# CHECK: Macro fuse: SU(0) - SU(1) / ADD8 - AND8 22--- 23name: add_and 24tracksRegLiveness: true 25body: | 26 bb.0.entry: 27 liveins: $x3, $x4, $x5 28 renamable $x4 = ADD8 $x3, $x4 29 renamable $x3 = AND8 killed renamable $x4, $x5 30 BLR8 implicit $lr8, implicit $rm, implicit $x3 31... 32 33# CHECK: xor_subf:%bb.0 34# CHECK: Macro fuse: SU(0) - SU(1) / XOR8 - SUBF8 35--- 36name: xor_subf 37tracksRegLiveness: true 38body: | 39 bb.0.entry: 40 liveins: $x3, $x4, $x5 41 renamable $x4 = XOR8 $x3, $x4 42 renamable $x3 = SUBF8 killed renamable $x4, $x5 43 BLR8 implicit $lr8, implicit $rm, implicit $x3 44... 45 46# CHECK: or_nand:%bb.0 47# CHECK: Macro fuse: SU(0) - SU(1) / OR8 - NAND8 48--- 49name: or_nand 50tracksRegLiveness: true 51body: | 52 bb.0.entry: 53 liveins: $x3, $x4, $x5 54 renamable $x4 = OR8 $x3, $x4 55 renamable $x3 = NAND8 killed renamable $x4, $x5 56 BLR8 implicit $lr8, implicit $rm, implicit $x3 57... 58 59# CHECK: vand_vand:%bb.0 60# CHECK: Macro fuse: SU(0) - SU(1) / VAND - VAND 61--- 62name: vand_vand 63tracksRegLiveness: true 64body: | 65 bb.0.entry: 66 liveins: $v2, $v3, $v4 67 renamable $v2 = VAND $v3, $v2 68 renamable $v2 = VAND killed renamable $v2, $v4 69 BLR8 implicit $lr8, implicit $rm 70... 71 72# CHECK: vadd_vadd:%bb.0 73# CHECK: Macro fuse: SU(0) - SU(1) / VADDUDM - VADDUDM 74--- 75name: vadd_vadd 76tracksRegLiveness: true 77body: | 78 bb.0.entry: 79 liveins: $v2, $v3, $v4 80 renamable $v2 = VADDUDM $v3, $v2 81 renamable $v2 = VADDUDM killed renamable $v2, $v4 82 BLR8 implicit $lr8, implicit $rm 83... 84 85# CHECK: sldi_add:%bb.0 86# CHECK: Macro fuse: SU(0) - SU(1) / RLDICR - ADD8 87--- 88name: sldi_add 89tracksRegLiveness: true 90body: | 91 bb.0.entry: 92 liveins: $x3, $x4, $x5 93 renamable $x4 = RLDICR $x3, 3, 60 94 renamable $x3 = ADD8 killed renamable $x4, $x5 95 BLR8 implicit $lr8, implicit $rm, implicit $x3 96... 97 98# CHECK: rldicl_xor:%bb.0 99# CHECK: Macro fuse: SU(0) - SU(1) / RLDICL - XOR8 100--- 101name: rldicl_xor 102tracksRegLiveness: true 103body: | 104 bb.0.entry: 105 liveins: $x3, $x4, $x5 106 renamable $x4 = RLDICL $x3, 1, 0 107 renamable $x3 = XOR8 killed renamable $x4, $x5 108 BLR8 implicit $lr8, implicit $rm, implicit $x3 109... 110 111# CHECK: rldicr_xor:%bb.0 112# CHECK: Macro fuse: SU(0) - SU(1) / RLDICR - XOR8 113--- 114name: rldicr_xor 115tracksRegLiveness: true 116body: | 117 bb.0.entry: 118 liveins: $x3, $x4, $x5 119 renamable $x4 = RLDICR $x3, 1, 63 120 renamable $x3 = XOR8 killed renamable $x4, $x5 121 BLR8 implicit $lr8, implicit $rm, implicit $x3 122... 123 124# CHECK: ori_oris:%bb.0 125# CHECK: Macro fuse: SU(0) - SU(1) / ORI8 - ORIS8 126--- 127name: ori_oris 128tracksRegLiveness: true 129body: | 130 bb.0.entry: 131 liveins: $x3, $x4 132 renamable $x4 = ORI8 $x3, 63 133 renamable $x3 = ORIS8 killed renamable $x4, 20 134 BLR8 implicit $lr8, implicit $rm, implicit $x3 135... 136 137# CHECK: load_cmp:%bb.0 138# CHECK: Macro fuse: SU(0) - SU(1) / LD - CMPDI 139--- 140name: load_cmp 141tracksRegLiveness: true 142body: | 143 bb.0.entry: 144 liveins: $x3, $x4, $x5 145 renamable $x3 = LD 0, killed renamable $x3 146 renamable $cr0 = CMPDI killed renamable $x3, 0 147 renamable $x3 = ISEL8 killed renamable $x5, killed renamable $x4, renamable $cr0lt, implicit killed $cr0 148 BLR8 implicit $lr8, implicit $rm, implicit $x3 149 150# CHECK: back2back_1:%bb.0 151# CHECK: Macro fuse: SU(0) - SU(1) / VADDUBM - VSUBUBM 152--- 153name: back2back_1 154tracksRegLiveness: true 155body: | 156 bb.0.entry: 157 liveins: $v2, $v3, $v4 158 renamable $v2 = VADDUBM $v3, $v2 159 renamable $v2 = VSUBUBM killed renamable $v2, $v4 160 BLR8 implicit $lr8, implicit $rm 161 162# CHECK: back2back_2:%bb.0 163# CHECK: Macro fuse: SU(0) - SU(1) / XSABSDP - XSNEGDP 164--- 165name: back2back_2 166tracksRegLiveness: true 167body: | 168 bb.0.entry: 169 liveins: $f1, $f2 170 renamable $f2 = XSABSDP $f1, implicit $rm 171 renamable $f1 = XSNEGDP killed renamable $f2, implicit $rm 172 BLR8 implicit $lr8, implicit $rm, implicit $f1 173 174# CHECK: back2back_3:%bb.0 175# CHECK: Macro fuse: SU(0) - SU(1) / VMAXFP - XVMINSP 176--- 177name: back2back_3 178tracksRegLiveness: true 179body: | 180 bb.0.entry: 181 liveins: $v2, $v3, $v4 182 renamable $v3 = VMAXFP $v2, $v3 183 renamable $v2 = XVMINSP killed renamable $v3, $v4, implicit $rm 184 BLR8 implicit $lr8, implicit $rm, implicit $v2 185