xref: /llvm-project/llvm/test/CodeGen/PowerPC/ldexp.ll (revision 6b1db79887df19bc8e8c946108966aa6021c8b87) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
3; RUN:   -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
4
5define float @ldexp_f32(i8 zeroext %x) {
6; CHECK-LABEL: ldexp_f32:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    mflr r0
9; CHECK-NEXT:    stdu r1, -32(r1)
10; CHECK-NEXT:    std r0, 48(r1)
11; CHECK-NEXT:    .cfi_def_cfa_offset 32
12; CHECK-NEXT:    .cfi_offset lr, 16
13; CHECK-NEXT:    vspltisw v2, 1
14; CHECK-NEXT:    mr r4, r3
15; CHECK-NEXT:    xvcvsxwdp vs1, v2
16; CHECK-NEXT:    bl ldexpf
17; CHECK-NEXT:    nop
18; CHECK-NEXT:    addi r1, r1, 32
19; CHECK-NEXT:    ld r0, 16(r1)
20; CHECK-NEXT:    mtlr r0
21; CHECK-NEXT:    blr
22  %zext = zext i8 %x to i32
23  %ldexp = call float @llvm.ldexp.f32.i32(float 1.000000e+00, i32 %zext)
24  ret float %ldexp
25}
26
27define double @ldexp_f64(i8 zeroext %x) {
28; CHECK-LABEL: ldexp_f64:
29; CHECK:       # %bb.0:
30; CHECK-NEXT:    mflr r0
31; CHECK-NEXT:    stdu r1, -32(r1)
32; CHECK-NEXT:    std r0, 48(r1)
33; CHECK-NEXT:    .cfi_def_cfa_offset 32
34; CHECK-NEXT:    .cfi_offset lr, 16
35; CHECK-NEXT:    vspltisw v2, 1
36; CHECK-NEXT:    mr r4, r3
37; CHECK-NEXT:    xvcvsxwdp vs1, v2
38; CHECK-NEXT:    bl ldexp
39; CHECK-NEXT:    nop
40; CHECK-NEXT:    addi r1, r1, 32
41; CHECK-NEXT:    ld r0, 16(r1)
42; CHECK-NEXT:    mtlr r0
43; CHECK-NEXT:    blr
44  %zext = zext i8 %x to i32
45  %ldexp = call double @llvm.ldexp.f64.i32(double 1.000000e+00, i32 %zext)
46  ret double %ldexp
47}
48
49define <2 x float> @ldexp_v2f32(<2 x float> %val, <2 x i32> %exp) {
50; CHECK-LABEL: ldexp_v2f32:
51; CHECK:       # %bb.0:
52; CHECK-NEXT:    mflr r0
53; CHECK-NEXT:    stdu r1, -80(r1)
54; CHECK-NEXT:    std r0, 96(r1)
55; CHECK-NEXT:    .cfi_def_cfa_offset 80
56; CHECK-NEXT:    .cfi_offset lr, 16
57; CHECK-NEXT:    .cfi_offset v29, -48
58; CHECK-NEXT:    .cfi_offset v30, -32
59; CHECK-NEXT:    .cfi_offset v31, -16
60; CHECK-NEXT:    li r3, 0
61; CHECK-NEXT:    xxsldwi vs0, v2, v2, 3
62; CHECK-NEXT:    stxv v29, 32(r1) # 16-byte Folded Spill
63; CHECK-NEXT:    xscvspdpn f1, vs0
64; CHECK-NEXT:    vextuwrx r3, r3, v3
65; CHECK-NEXT:    stxv v30, 48(r1) # 16-byte Folded Spill
66; CHECK-NEXT:    stxv v31, 64(r1) # 16-byte Folded Spill
67; CHECK-NEXT:    extsw r4, r3
68; CHECK-NEXT:    vmr v31, v3
69; CHECK-NEXT:    vmr v30, v2
70; CHECK-NEXT:    bl ldexpf
71; CHECK-NEXT:    nop
72; CHECK-NEXT:    li r3, 4
73; CHECK-NEXT:    xxswapd vs0, v30
74; CHECK-NEXT:    xscvdpspn v29, f1
75; CHECK-NEXT:    xscvspdpn f1, vs0
76; CHECK-NEXT:    vextuwrx r3, r3, v31
77; CHECK-NEXT:    extsw r4, r3
78; CHECK-NEXT:    bl ldexpf
79; CHECK-NEXT:    nop
80; CHECK-NEXT:    xscvdpspn vs0, f1
81; CHECK-NEXT:    lxv v31, 64(r1) # 16-byte Folded Reload
82; CHECK-NEXT:    lxv v30, 48(r1) # 16-byte Folded Reload
83; CHECK-NEXT:    xxmrghw v2, vs0, v29
84; CHECK-NEXT:    lxv v29, 32(r1) # 16-byte Folded Reload
85; CHECK-NEXT:    addi r1, r1, 80
86; CHECK-NEXT:    ld r0, 16(r1)
87; CHECK-NEXT:    mtlr r0
88; CHECK-NEXT:    blr
89  %1 = call <2 x float> @llvm.ldexp.v2f32.v2i32(<2 x float> %val, <2 x i32> %exp)
90  ret <2 x float> %1
91}
92
93define <4 x float> @ldexp_v4f32(<4 x float> %val, <4 x i32> %exp) {
94; CHECK-LABEL: ldexp_v4f32:
95; CHECK:       # %bb.0:
96; CHECK-NEXT:    mflr r0
97; CHECK-NEXT:    stdu r1, -96(r1)
98; CHECK-NEXT:    std r0, 112(r1)
99; CHECK-NEXT:    .cfi_def_cfa_offset 96
100; CHECK-NEXT:    .cfi_offset lr, 16
101; CHECK-NEXT:    .cfi_offset v28, -64
102; CHECK-NEXT:    .cfi_offset v29, -48
103; CHECK-NEXT:    .cfi_offset v30, -32
104; CHECK-NEXT:    .cfi_offset v31, -16
105; CHECK-NEXT:    li r3, 4
106; CHECK-NEXT:    xxswapd vs0, v2
107; CHECK-NEXT:    stxv v28, 32(r1) # 16-byte Folded Spill
108; CHECK-NEXT:    xscvspdpn f1, vs0
109; CHECK-NEXT:    vextuwrx r3, r3, v3
110; CHECK-NEXT:    stxv v29, 48(r1) # 16-byte Folded Spill
111; CHECK-NEXT:    stxv v30, 64(r1) # 16-byte Folded Spill
112; CHECK-NEXT:    stxv v31, 80(r1) # 16-byte Folded Spill
113; CHECK-NEXT:    vmr v31, v3
114; CHECK-NEXT:    extsw r4, r3
115; CHECK-NEXT:    vmr v30, v2
116; CHECK-NEXT:    bl ldexpf
117; CHECK-NEXT:    nop
118; CHECK-NEXT:    li r3, 12
119; CHECK-NEXT:    xscpsgndp v29, f1, f1
120; CHECK-NEXT:    xscvspdpn f1, v30
121; CHECK-NEXT:    vextuwrx r3, r3, v31
122; CHECK-NEXT:    extsw r4, r3
123; CHECK-NEXT:    bl ldexpf
124; CHECK-NEXT:    nop
125; CHECK-NEXT:    xxmrghd vs0, vs1, v29
126; CHECK-NEXT:    li r3, 0
127; CHECK-NEXT:    vextuwrx r3, r3, v31
128; CHECK-NEXT:    xvcvdpsp v28, vs0
129; CHECK-NEXT:    xxsldwi vs0, v30, v30, 3
130; CHECK-NEXT:    extsw r4, r3
131; CHECK-NEXT:    xscvspdpn f1, vs0
132; CHECK-NEXT:    bl ldexpf
133; CHECK-NEXT:    nop
134; CHECK-NEXT:    xxsldwi vs0, v30, v30, 1
135; CHECK-NEXT:    mfvsrwz r3, v31
136; CHECK-NEXT:    xscpsgndp v29, f1, f1
137; CHECK-NEXT:    extsw r4, r3
138; CHECK-NEXT:    xscvspdpn f1, vs0
139; CHECK-NEXT:    bl ldexpf
140; CHECK-NEXT:    nop
141; CHECK-NEXT:    xxmrghd vs0, vs1, v29
142; CHECK-NEXT:    lxv v31, 80(r1) # 16-byte Folded Reload
143; CHECK-NEXT:    lxv v30, 64(r1) # 16-byte Folded Reload
144; CHECK-NEXT:    lxv v29, 48(r1) # 16-byte Folded Reload
145; CHECK-NEXT:    xvcvdpsp v2, vs0
146; CHECK-NEXT:    vmrgew v2, v28, v2
147; CHECK-NEXT:    lxv v28, 32(r1) # 16-byte Folded Reload
148; CHECK-NEXT:    addi r1, r1, 96
149; CHECK-NEXT:    ld r0, 16(r1)
150; CHECK-NEXT:    mtlr r0
151; CHECK-NEXT:    blr
152  %1 = call <4 x float> @llvm.ldexp.v4f32.v4i32(<4 x float> %val, <4 x i32> %exp)
153  ret <4 x float> %1
154}
155
156define half @ldexp_f16(half %arg0, i32 %arg1) {
157; CHECK-LABEL: ldexp_f16:
158; CHECK:       # %bb.0:
159; CHECK-NEXT:    mflr r0
160; CHECK-NEXT:    stdu r1, -32(r1)
161; CHECK-NEXT:    std r0, 48(r1)
162; CHECK-NEXT:    .cfi_def_cfa_offset 32
163; CHECK-NEXT:    .cfi_offset lr, 16
164; CHECK-NEXT:    xscvdphp f0, f1
165; CHECK-NEXT:    extsw r4, r4
166; CHECK-NEXT:    mffprwz r3, f0
167; CHECK-NEXT:    clrlwi r3, r3, 16
168; CHECK-NEXT:    mtfprwz f0, r3
169; CHECK-NEXT:    xscvhpdp f1, f0
170; CHECK-NEXT:    bl ldexpf
171; CHECK-NEXT:    nop
172; CHECK-NEXT:    addi r1, r1, 32
173; CHECK-NEXT:    ld r0, 16(r1)
174; CHECK-NEXT:    mtlr r0
175; CHECK-NEXT:    blr
176  %ldexp = call half @llvm.ldexp.f16.i32(half %arg0, i32 %arg1)
177  ret half %ldexp
178}
179
180define ppc_fp128 @ldexp_fp128(ppc_fp128 %arg0, i32 %arg1) {
181; CHECK-LABEL: ldexp_fp128:
182; CHECK:       # %bb.0:
183; CHECK-NEXT:    mflr r0
184; CHECK-NEXT:    stdu r1, -32(r1)
185; CHECK-NEXT:    std r0, 48(r1)
186; CHECK-NEXT:    .cfi_def_cfa_offset 32
187; CHECK-NEXT:    .cfi_offset lr, 16
188; CHECK-NEXT:    clrldi r5, r5, 32
189; CHECK-NEXT:    bl ldexpl
190; CHECK-NEXT:    nop
191; CHECK-NEXT:    addi r1, r1, 32
192; CHECK-NEXT:    ld r0, 16(r1)
193; CHECK-NEXT:    mtlr r0
194; CHECK-NEXT:    blr
195  %ldexp = call ppc_fp128 @llvm.ldexp.ppcf128.i32(ppc_fp128 %arg0, i32 %arg1)
196  ret ppc_fp128 %ldexp
197}
198
199declare double @llvm.ldexp.f64.i32(double, i32) #0
200declare float @llvm.ldexp.f32.i32(float, i32) #0
201declare <2 x float> @llvm.ldexp.v2f32.v2i32(<2 x float>, <2 x i32>) #0
202declare <4 x float> @llvm.ldexp.v4f32.v4i32(<4 x float>, <4 x i32>) #0
203declare half @llvm.ldexp.f16.i32(half, i32) #0
204declare ppc_fp128 @llvm.ldexp.ppcf128.i32(ppc_fp128, i32) #0
205
206attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
207