xref: /llvm-project/llvm/test/CodeGen/PowerPC/ifcvt_cr_field.ll (revision 1492c88f494cb09de0ebc7fb77a84c41d0aa93ce)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
3; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s
4; RUN: llc < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-64
5; RUN: llc < %s -mtriple=powerpc-unknown-aix -mcpu=pwr9 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-AIX-32
6
7define dso_local signext i32 @test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) local_unnamed_addr {
8; CHECK-LABEL: test:
9; CHECK:       # %bb.0: # %entry
10; CHECK-NEXT:    vcmpgtsw. 2, 2, 3
11; CHECK-NEXT:    bge 6, .LBB0_2
12; CHECK-NEXT:  # %bb.1: # %land.rhs
13; CHECK-NEXT:    vcmpgtsw. 2, 4, 3
14; CHECK-NEXT:    mfocrf 3, 2
15; CHECK-NEXT:    rlwinm 3, 3, 25, 31, 31
16; CHECK-NEXT:    blr
17; CHECK-NEXT:  .LBB0_2:
18; CHECK-NEXT:    li 3, 0
19; CHECK-NEXT:    blr
20;
21; CHECK-AIX-64-LABEL: test:
22; CHECK-AIX-64:       # %bb.0: # %entry
23; CHECK-AIX-64-NEXT:    vcmpgtsw. 2, 2, 3
24; CHECK-AIX-64-NEXT:    bge 6, L..BB0_2
25; CHECK-AIX-64-NEXT:  # %bb.1: # %land.rhs
26; CHECK-AIX-64-NEXT:    vcmpgtsw. 2, 4, 3
27; CHECK-AIX-64-NEXT:    mfocrf 3, 2
28; CHECK-AIX-64-NEXT:    rlwinm 3, 3, 25, 31, 31
29; CHECK-AIX-64-NEXT:    blr
30; CHECK-AIX-64-NEXT:  L..BB0_2:
31; CHECK-AIX-64-NEXT:    li 3, 0
32; CHECK-AIX-64-NEXT:    blr
33;
34; CHECK-AIX-32-LABEL: test:
35; CHECK-AIX-32:       # %bb.0: # %entry
36; CHECK-AIX-32-NEXT:    vcmpgtsw. 2, 2, 3
37; CHECK-AIX-32-NEXT:    bge 6, L..BB0_2
38; CHECK-AIX-32-NEXT:  # %bb.1: # %land.rhs
39; CHECK-AIX-32-NEXT:    vcmpgtsw. 2, 4, 3
40; CHECK-AIX-32-NEXT:    mfocrf 3, 2
41; CHECK-AIX-32-NEXT:    rlwinm 3, 3, 25, 31, 31
42; CHECK-AIX-32-NEXT:    blr
43; CHECK-AIX-32-NEXT:  L..BB0_2:
44; CHECK-AIX-32-NEXT:    li 3, 0
45; CHECK-AIX-32-NEXT:    blr
46entry:
47  %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b)
48  %tobool.not = icmp eq i32 %0, 0
49  br i1 %tobool.not, label %land.end, label %land.rhs
50
51land.rhs:                                         ; preds = %entry
52  %1 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %c, <4 x i32> %b)
53  %tobool1 = icmp ne i32 %1, 0
54  %phi.cast = zext i1 %tobool1 to i32
55  br label %land.end
56
57land.end:                                         ; preds = %land.rhs, %entry
58  %2 = phi i32 [ 0, %entry ], [ %phi.cast, %land.rhs ]
59  ret i32 %2
60}
61
62declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>)
63