1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ 3; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s 4 5@val = external local_unnamed_addr global i32, align 4 6declare i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double>) 7 8define dso_local signext i32 @xvtsqrtdp_and_1_eq(<2 x double> %input) { 9; CHECK-LABEL: xvtsqrtdp_and_1_eq: 10; CHECK: # %bb.0: # %entry 11; CHECK-NEXT: xvtsqrtdp cr0, v2 12; CHECK-NEXT: bnu cr0, .LBB0_2 13; CHECK-NEXT: # %bb.1: # %if.then 14; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 15; CHECK-NEXT: li r4, 100 16; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 17; CHECK-NEXT: stw r4, 0(r3) 18; CHECK-NEXT: .LBB0_2: # %if.end 19; CHECK-NEXT: li r3, 1 20; CHECK-NEXT: blr 21entry: 22 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input) 23 %1 = and i32 %0, 1 24 %cmp.not = icmp eq i32 %1, 0 25 br i1 %cmp.not, label %if.end, label %if.then 26 27if.then: ; preds = %entry 28 store i32 100, ptr @val, align 4 29 br label %if.end 30 31if.end: ; preds = %if.then, %entry 32 ret i32 1 33} 34 35define dso_local signext i32 @xvtsqrtdp_and_2_eq(<2 x double> %input) { 36; CHECK-LABEL: xvtsqrtdp_and_2_eq: 37; CHECK: # %bb.0: # %entry 38; CHECK-NEXT: xvtsqrtdp cr0, v2 39; CHECK-NEXT: bne cr0, .LBB1_2 40; CHECK-NEXT: # %bb.1: # %if.then 41; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 42; CHECK-NEXT: li r4, 100 43; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 44; CHECK-NEXT: stw r4, 0(r3) 45; CHECK-NEXT: .LBB1_2: # %if.end 46; CHECK-NEXT: li r3, 1 47; CHECK-NEXT: blr 48entry: 49 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input) 50 %1 = and i32 %0, 2 51 %cmp.not = icmp eq i32 %1, 0 52 br i1 %cmp.not, label %if.end, label %if.then 53 54if.then: ; preds = %entry 55 store i32 100, ptr @val, align 4 56 br label %if.end 57 58if.end: ; preds = %if.then, %entry 59 ret i32 1 60} 61 62define dso_local signext i32 @xvtsqrtdp_and_4_eq(<2 x double> %input) { 63; CHECK-LABEL: xvtsqrtdp_and_4_eq: 64; CHECK: # %bb.0: # %entry 65; CHECK-NEXT: xvtsqrtdp cr0, v2 66; CHECK-NEXT: ble cr0, .LBB2_2 67; CHECK-NEXT: # %bb.1: # %if.then 68; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 69; CHECK-NEXT: li r4, 100 70; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 71; CHECK-NEXT: stw r4, 0(r3) 72; CHECK-NEXT: .LBB2_2: # %if.end 73; CHECK-NEXT: li r3, 1 74; CHECK-NEXT: blr 75entry: 76 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input) 77 %1 = and i32 %0, 4 78 %cmp.not = icmp eq i32 %1, 0 79 br i1 %cmp.not, label %if.end, label %if.then 80 81if.then: ; preds = %entry 82 store i32 100, ptr @val, align 4 83 br label %if.end 84 85if.end: ; preds = %if.then, %entry 86 ret i32 1 87} 88 89define dso_local signext i32 @xvtsqrtdp_and_8_eq(<2 x double> %input) { 90; CHECK-LABEL: xvtsqrtdp_and_8_eq: 91; CHECK: # %bb.0: # %entry 92; CHECK-NEXT: xvtsqrtdp cr0, v2 93; CHECK-NEXT: bge cr0, .LBB3_2 94; CHECK-NEXT: # %bb.1: # %if.then 95; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 96; CHECK-NEXT: li r4, 100 97; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 98; CHECK-NEXT: stw r4, 0(r3) 99; CHECK-NEXT: .LBB3_2: # %if.end 100; CHECK-NEXT: li r3, 1 101; CHECK-NEXT: blr 102entry: 103 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input) 104 %1 = and i32 %0, 8 105 %cmp.not = icmp eq i32 %1, 0 106 br i1 %cmp.not, label %if.end, label %if.then 107 108if.then: ; preds = %entry 109 store i32 100, ptr @val, align 4 110 br label %if.end 111 112if.end: ; preds = %if.then, %entry 113 ret i32 1 114} 115 116define dso_local signext i32 @xvtsqrtdp_and_1_ne(<2 x double> %input) { 117; CHECK-LABEL: xvtsqrtdp_and_1_ne: 118; CHECK: # %bb.0: # %entry 119; CHECK-NEXT: xvtsqrtdp cr0, v2 120; CHECK-NEXT: bun cr0, .LBB4_2 121; CHECK-NEXT: # %bb.1: # %if.then 122; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 123; CHECK-NEXT: li r4, 100 124; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 125; CHECK-NEXT: stw r4, 0(r3) 126; CHECK-NEXT: .LBB4_2: # %if.end 127; CHECK-NEXT: li r3, 1 128; CHECK-NEXT: blr 129entry: 130 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input) 131 %1 = and i32 %0, 1 132 %cmp.not = icmp ne i32 %1, 0 133 br i1 %cmp.not, label %if.end, label %if.then 134 135if.then: ; preds = %entry 136 store i32 100, ptr @val, align 4 137 br label %if.end 138 139if.end: ; preds = %if.then, %entry 140 ret i32 1 141} 142 143define dso_local signext i32 @xvtsqrtdp_and_2_ne(<2 x double> %input) { 144; CHECK-LABEL: xvtsqrtdp_and_2_ne: 145; CHECK: # %bb.0: # %if.end 146; CHECK-NEXT: li r3, 1 147; CHECK-NEXT: blr 148if.end: ; preds = %if.then, %entry 149 ret i32 1 150} 151 152define dso_local signext i32 @xvtsqrtdp_and_4_ne(<2 x double> %input) { 153; CHECK-LABEL: xvtsqrtdp_and_4_ne: 154; CHECK: # %bb.0: # %entry 155; CHECK-NEXT: xvtsqrtdp cr0, v2 156; CHECK-NEXT: bgt cr0, .LBB6_2 157; CHECK-NEXT: # %bb.1: # %if.then 158; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 159; CHECK-NEXT: li r4, 100 160; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 161; CHECK-NEXT: stw r4, 0(r3) 162; CHECK-NEXT: .LBB6_2: # %if.end 163; CHECK-NEXT: li r3, 1 164; CHECK-NEXT: blr 165entry: 166 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input) 167 %1 = and i32 %0, 4 168 %cmp.not = icmp ne i32 %1, 0 169 br i1 %cmp.not, label %if.end, label %if.then 170 171if.then: ; preds = %entry 172 store i32 100, ptr @val, align 4 173 br label %if.end 174 175if.end: ; preds = %if.then, %entry 176 ret i32 1 177} 178 179define dso_local signext i32 @xvtsqrtdp_and_8_ne(<2 x double> %input) { 180; CHECK-LABEL: xvtsqrtdp_and_8_ne: 181; CHECK: # %bb.0: # %entry 182; CHECK-NEXT: xvtsqrtdp cr0, v2 183; CHECK-NEXT: blt cr0, .LBB7_2 184; CHECK-NEXT: # %bb.1: # %if.then 185; CHECK-NEXT: addis r3, r2, .LC0@toc@ha 186; CHECK-NEXT: li r4, 100 187; CHECK-NEXT: ld r3, .LC0@toc@l(r3) 188; CHECK-NEXT: stw r4, 0(r3) 189; CHECK-NEXT: .LBB7_2: # %if.end 190; CHECK-NEXT: li r3, 1 191; CHECK-NEXT: blr 192entry: 193 %0 = tail call i32 @llvm.ppc.vsx.xvtsqrtdp(<2 x double> %input) 194 %1 = and i32 %0, 8 195 %cmp.not = icmp ne i32 %1, 0 196 br i1 %cmp.not, label %if.end, label %if.then 197 198if.then: ; preds = %entry 199 store i32 100, ptr @val, align 4 200 br label %if.end 201 202if.end: ; preds = %if.then, %entry 203 ret i32 1 204} 205