1; NOTE: This test ensures that, for both Big and Little Endian cases, a set of 2; NOTE: 4 floats is gathered into a v4f32 register using xxmrghw and xxmrgld 3; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ 4; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \ 5; RUN: | FileCheck %s -check-prefix=CHECK-LE 6; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ 7; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \ 8; RUN: | FileCheck %s -check-prefix=CHECK-BE 9; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ 10; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix-xcoff < %s \ 11; RUN: | FileCheck %s -check-prefix=CHECK-BE 12; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \ 13; RUN: -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix-xcoff < %s \ 14; RUN: | FileCheck %s -check-prefix=CHECK-BE-AIX-32 15define dso_local <4 x float> @vector_gatherf(ptr nocapture readonly %a, 16ptr nocapture readonly %b, ptr nocapture readonly %c, 17ptr nocapture readonly %d) { 18; C code from which this IR test case was generated: 19; vector float test(ptr a, ptr b, ptr c, ptr d) { 20; return (vector float) { *a, *b, *c, *d }; 21; } 22; CHECK-LE-LABEL: vector_gatherf: 23; CHECK-LE: # %bb.0: # %entry 24; CHECK-LE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r6 25; CHECK-LE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r5 26; CHECK-LE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r4 27; CHECK-LE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r3 28; CHECK-LE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]] 29; CHECK-LE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]] 30; CHECK-LE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]] 31; CHECK-LE-NEXT: blr 32 33; CHECK-BE-LABEL: vector_gatherf: 34; CHECK-BE: # %bb.0: # %entry 35; CHECK-BE-DAG: lfiwzx f[[REG0:[0-9]+]], 0, r3 36; CHECK-BE-DAG: lfiwzx f[[REG1:[0-9]+]], 0, r4 37; CHECK-BE-DAG: lfiwzx f[[REG2:[0-9]+]], 0, r5 38; CHECK-BE-DAG: lfiwzx f[[REG3:[0-9]+]], 0, r6 39; CHECK-BE-DAG: xxmrghw vs[[REG0]], vs[[REG0]], vs[[REG1]] 40; CHECK-BE-DAG: xxmrghw vs[[REG4:[0-9]+]], vs[[REG2]], vs[[REG3]] 41; CHECK-BE-NEXT: xxmrgld v[[REG:[0-9]+]], vs[[REG0]], vs[[REG4]] 42; CHECK-BE-NEXT: blr 43 44; CHECK-BE-AIX-32-LABEL: vector_gatherf: 45; CHECK-BE-AIX-32-LABEL: # %bb.0: # %entry 46; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG0:[0-9]+]] 47; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG1:[0-9]+]] 48; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG2:[0-9]+]] 49; CHECK-BE-AIX-32-DAG: lxsiwzx v[[REG3:[0-9]+]] 50; CHECK-BE-AIX-32-DAG: vmrgow v[[REG0]], v[[REG1]], v[[REG0]] 51; CHECK-BE-AIX-32-DAG: vmrgow v[[REG3]], v[[REG2]], v[[REG3]] 52; CHECK-BE-AIX-32-NEXT: xxmrghd v[[REG0]], v[[REG3]], v[[REG0]] 53; CHECK-BE-AIX-32-NEXT: blr 54entry: 55 %0 = load float, ptr %a, align 4 56 %vecinit = insertelement <4 x float> undef, float %0, i32 0 57 %1 = load float, ptr %b, align 4 58 %vecinit1 = insertelement <4 x float> %vecinit, float %1, i32 1 59 %2 = load float, ptr %c, align 4 60 %vecinit2 = insertelement <4 x float> %vecinit1, float %2, i32 2 61 %3 = load float, ptr %d, align 4 62 %vecinit3 = insertelement <4 x float> %vecinit2, float %3, i32 3 63 ret <4 x float> %vecinit3 64} 65 66