1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ 3; RUN: -ppc-asm-full-reg-names -verify-machineinstrs -O2 < %s | FileCheck %s 4 5define float @absf(float %a) { 6; CHECK-LABEL: absf: 7; CHECK: # %bb.0: # %entry 8; CHECK-NEXT: xsabsdp f1, f1 9; CHECK-NEXT: blr 10entry: 11 %conv = bitcast float %a to i32 12 %and = and i32 %conv, 2147483647 13 %conv1 = bitcast i32 %and to float 14 ret float %conv1 15} 16 17define double @absd(double %a) { 18; CHECK-LABEL: absd: 19; CHECK: # %bb.0: # %entry 20; CHECK-NEXT: xsabsdp f1, f1 21; CHECK-NEXT: blr 22entry: 23 %conv = bitcast double %a to i64 24 %and = and i64 %conv, 9223372036854775807 25 %conv1 = bitcast i64 %and to double 26 ret double %conv1 27} 28 29define <4 x float> @absv4f32(<4 x float> %a) { 30; CHECK-LABEL: absv4f32: 31; CHECK: # %bb.0: # %entry 32; CHECK-NEXT: xvabssp vs34, vs34 33; CHECK-NEXT: blr 34entry: 35 %conv = bitcast <4 x float> %a to <4 x i32> 36 %and = and <4 x i32> %conv, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> 37 %conv1 = bitcast <4 x i32> %and to <4 x float> 38 ret <4 x float> %conv1 39} 40 41define <4 x float> @absv4f32_wundef(<4 x float> %a) { 42; CHECK-LABEL: absv4f32_wundef: 43; CHECK: # %bb.0: # %entry 44; CHECK-NEXT: xvabssp vs34, vs34 45; CHECK-NEXT: blr 46entry: 47 %conv = bitcast <4 x float> %a to <4 x i32> 48 %and = and <4 x i32> %conv, <i32 2147483647, i32 undef, i32 undef, i32 2147483647> 49 %conv1 = bitcast <4 x i32> %and to <4 x float> 50 ret <4 x float> %conv1 51} 52 53define <4 x float> @absv4f32_invalid(<4 x float> %a) { 54; CHECK-LABEL: absv4f32_invalid: 55; CHECK: # %bb.0: # %entry 56; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha 57; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l 58; CHECK-NEXT: lxvd2x vs0, 0, r3 59; CHECK-NEXT: xxswapd vs35, vs0 60; CHECK-NEXT: xxland vs34, vs34, vs35 61; CHECK-NEXT: blr 62entry: 63 %conv = bitcast <4 x float> %a to <4 x i32> 64 %and = and <4 x i32> %conv, <i32 2147483646, i32 2147483647, i32 2147483647, i32 2147483647> 65 %conv1 = bitcast <4 x i32> %and to <4 x float> 66 ret <4 x float> %conv1 67} 68 69define <2 x double> @absv2f64(<2 x double> %a) { 70; CHECK-LABEL: absv2f64: 71; CHECK: # %bb.0: # %entry 72; CHECK-NEXT: xvabsdp vs34, vs34 73; CHECK-NEXT: blr 74entry: 75 %conv = bitcast <2 x double> %a to <2 x i64> 76 %and = and <2 x i64> %conv, <i64 9223372036854775807, i64 9223372036854775807> 77 %conv1 = bitcast <2 x i64> %and to <2 x double> 78 ret <2 x double> %conv1 79} 80 81define float @negf(float %a) { 82; CHECK-LABEL: negf: 83; CHECK: # %bb.0: # %entry 84; CHECK-NEXT: xsnegdp f1, f1 85; CHECK-NEXT: blr 86entry: 87 %conv = bitcast float %a to i32 88 %and = xor i32 %conv, -2147483648 89 %conv1 = bitcast i32 %and to float 90 ret float %conv1 91} 92 93define double @negd(double %a) { 94; CHECK-LABEL: negd: 95; CHECK: # %bb.0: # %entry 96; CHECK-NEXT: xsnegdp f1, f1 97; CHECK-NEXT: blr 98entry: 99 %conv = bitcast double %a to i64 100 %and = xor i64 %conv, -9223372036854775808 101 %conv1 = bitcast i64 %and to double 102 ret double %conv1 103} 104 105define <4 x float> @negv4f32(<4 x float> %a) { 106; CHECK-LABEL: negv4f32: 107; CHECK: # %bb.0: # %entry 108; CHECK-NEXT: xvnegsp vs34, vs34 109; CHECK-NEXT: blr 110entry: 111 %conv = bitcast <4 x float> %a to <4 x i32> 112 %and = xor <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 113 %conv1 = bitcast <4 x i32> %and to <4 x float> 114 ret <4 x float> %conv1 115} 116 117define <2 x double> @negv2d64(<2 x double> %a) { 118; CHECK-LABEL: negv2d64: 119; CHECK: # %bb.0: # %entry 120; CHECK-NEXT: xvnegdp vs34, vs34 121; CHECK-NEXT: blr 122entry: 123 %conv = bitcast <2 x double> %a to <2 x i64> 124 %and = xor <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808> 125 %conv1 = bitcast <2 x i64> %and to <2 x double> 126 ret <2 x double> %conv1 127} 128define float @nabsf(float %a) { 129; CHECK-LABEL: nabsf: 130; CHECK: # %bb.0: # %entry 131; CHECK-NEXT: xsnabsdp f1, f1 132; CHECK-NEXT: blr 133entry: 134 %conv = bitcast float %a to i32 135 %and = or i32 %conv, -2147483648 136 %conv1 = bitcast i32 %and to float 137 ret float %conv1 138} 139 140define double @nabsd(double %a) { 141; CHECK-LABEL: nabsd: 142; CHECK: # %bb.0: # %entry 143; CHECK-NEXT: xsnabsdp f1, f1 144; CHECK-NEXT: blr 145entry: 146 %conv = bitcast double %a to i64 147 %and = or i64 %conv, -9223372036854775808 148 %conv1 = bitcast i64 %and to double 149 ret double %conv1 150} 151 152define <4 x float> @nabsv4f32(<4 x float> %a) { 153; CHECK-LABEL: nabsv4f32: 154; CHECK: # %bb.0: # %entry 155; CHECK-NEXT: xvnabssp vs34, vs34 156; CHECK-NEXT: blr 157entry: 158 %conv = bitcast <4 x float> %a to <4 x i32> 159 %and = or <4 x i32> %conv, <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648> 160 %conv1 = bitcast <4 x i32> %and to <4 x float> 161 ret <4 x float> %conv1 162} 163 164define <2 x double> @nabsv2d64(<2 x double> %a) { 165; CHECK-LABEL: nabsv2d64: 166; CHECK: # %bb.0: # %entry 167; CHECK-NEXT: xvnabsdp vs34, vs34 168; CHECK-NEXT: blr 169entry: 170 %conv = bitcast <2 x double> %a to <2 x i64> 171 %and = or <2 x i64> %conv, <i64 -9223372036854775808, i64 -9223372036854775808> 172 %conv1 = bitcast <2 x i64> %and to <2 x double> 173 ret <2 x double> %conv1 174} 175 176