xref: /llvm-project/llvm/test/CodeGen/PowerPC/fast-isel-shifter.ll (revision d0f9553ef564de1ea0749ee3519d5505920dc29f) 
1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
3
4define i32 @shl() nounwind {
5entry:
6; PPC64: shl
7; PPC64: slw
8  %shl = shl i32 -1, 2
9  ret i32 %shl
10}
11
12define i32 @shl_reg(i32 %src1, i32 %src2) nounwind {
13entry:
14; PPC64: shl_reg
15; PPC64: slw
16  %shl = shl i32 %src1, %src2
17  ret i32 %shl
18}
19
20define i32 @lshr() nounwind {
21entry:
22; PPC64: lshr
23; PPC64: srw
24  %lshr = lshr i32 -1, 2
25  ret i32 %lshr
26}
27
28define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind {
29entry:
30; PPC64: lshr_reg
31; PPC64: srw
32  %lshr = lshr i32 %src1, %src2
33  ret i32 %lshr
34}
35
36define i32 @ashr() nounwind {
37entry:
38; PPC64: ashr
39; PPC64: srawi
40  %ashr = ashr i32 -1, 2
41  ret i32 %ashr
42}
43
44define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind {
45entry:
46; PPC64: ashr_reg
47; PPC64: sraw
48  %ashr = ashr i32 %src1, %src2
49  ret i32 %ashr
50}
51
52