1; FIXME: FastISel currently returns false if it hits code that uses VSX 2; registers and with -fast-isel-abort=1 turned on the test case will then fail. 3; When fastisel better supports VSX fix up this test case. 4; 5; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s 6; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s 7; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970 8; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE 9 10;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt 11;; to SelectionDAG in some cases. 12 13; Test sitofp 14 15define void @sitofp_single_i64(i64 %a, float %b) nounwind { 16entry: 17; CHECK: sitofp_single_i64 18; PPC970: sitofp_single_i64 19 %b.addr = alloca float, align 4 20 %conv = sitofp i64 %a to float 21; CHECK: std 22; CHECK: lfd 23; CHECK: fcfids 24; PPC970: std 25; PPC970: lfd 26; PPC970: fcfid 27; PPC970: frsp 28 store float %conv, ptr %b.addr, align 4 29 ret void 30} 31 32define void @sitofp_single_i32(i32 %a, float %b) nounwind { 33entry: 34; CHECK: sitofp_single_i32 35; PPC970: sitofp_single_i32 36 %b.addr = alloca float, align 4 37 %conv = sitofp i32 %a to float 38; CHECK: std 39; CHECK-NEXT: li 40; CHECK-NEXT: lfiwax 41; CHECK-NEXT: fcfids 42; PPC970: std 43; PPC970: lfd 44; PPC970: fcfid 45; PPC970: frsp 46; SPE: efscfsi 47 store float %conv, ptr %b.addr, align 4 48 ret void 49} 50 51define void @sitofp_single_i16(i16 %a, float %b) nounwind { 52entry: 53; CHECK: sitofp_single_i16 54; PPC970: sitofp_single_i16 55 %b.addr = alloca float, align 4 56 %conv = sitofp i16 %a to float 57; CHECK: extsh 58; CHECK: std 59; CHECK: lfd 60; CHECK: fcfids 61; PPC970: extsh 62; PPC970: std 63; PPC970: lfd 64; PPC970: fcfid 65; PPC970: frsp 66; SPE: extsh 67; SPE: efscfsi 68 store float %conv, ptr %b.addr, align 4 69 ret void 70} 71 72define void @sitofp_single_i8(i8 %a) nounwind { 73entry: 74; CHECK: sitofp_single_i8 75; PPC970: sitofp_single_i8 76 %b.addr = alloca float, align 4 77 %conv = sitofp i8 %a to float 78; CHECK: extsb 79; CHECK: std 80; CHECK: lfd 81; CHECK: fcfids 82; PPC970: extsb 83; PPC970: std 84; PPC970: lfd 85; PPC970: fcfid 86; PPC970: frsp 87; SPE: extsb 88; SPE: efscfsi 89 store float %conv, ptr %b.addr, align 4 90 ret void 91} 92 93define void @sitofp_double_i32(i32 %a, double %b) nounwind { 94entry: 95; CHECK: sitofp_double_i32 96; PPC970: sitofp_double_i32 97 %b.addr = alloca double, align 8 98 %conv = sitofp i32 %a to double 99; CHECK: std 100; CHECK-NOT: ori 101; CHECK: li 102; CHECK-NOT: ori 103; CHECK: lfiwax 104; CHECK: fcfid 105; PPC970: std 106; PPC970: lfd 107; PPC970: fcfid 108; SPE: efdcfsi 109 store double %conv, ptr %b.addr, align 8 110 ret void 111} 112 113define void @sitofp_double_i64(i64 %a, double %b) nounwind { 114entry: 115; CHECK: sitofp_double_i64 116; PPC970: sitofp_double_i64 117 %b.addr = alloca double, align 8 118 %conv = sitofp i64 %a to double 119; CHECK: std 120; CHECK: lfd 121; CHECK: fcfid 122; PPC970: std 123; PPC970: lfd 124; PPC970: fcfid 125 store double %conv, ptr %b.addr, align 8 126 ret void 127} 128 129define void @sitofp_double_i16(i16 %a, double %b) nounwind { 130entry: 131; CHECK: sitofp_double_i16 132; PPC970: sitofp_double_i16 133 %b.addr = alloca double, align 8 134 %conv = sitofp i16 %a to double 135; CHECK: extsh 136; CHECK: std 137; CHECK: lfd 138; CHECK: fcfid 139; PPC970: extsh 140; PPC970: std 141; PPC970: lfd 142; PPC970: fcfid 143; SPE: extsh 144; SPE: efdcfsi 145 store double %conv, ptr %b.addr, align 8 146 ret void 147} 148 149define void @sitofp_double_i8(i8 %a, double %b) nounwind { 150entry: 151; CHECK: sitofp_double_i8 152; PPC970: sitofp_double_i8 153 %b.addr = alloca double, align 8 154 %conv = sitofp i8 %a to double 155; CHECK: extsb 156; CHECK: std 157; CHECK: lfd 158; CHECK: fcfid 159; PPC970: extsb 160; PPC970: std 161; PPC970: lfd 162; PPC970: fcfid 163; SPE: extsb 164; SPE: efdcfsi 165 store double %conv, ptr %b.addr, align 8 166 ret void 167} 168 169; Test uitofp 170 171define void @uitofp_single_i64(i64 %a, float %b) nounwind { 172entry: 173; CHECK: uitofp_single_i64 174; PPC970: uitofp_single_i64 175 %b.addr = alloca float, align 4 176 %conv = uitofp i64 %a to float 177; CHECK: std 178; CHECK: lfd 179; CHECK: fcfidus 180; PPC970-NOT: fcfidus 181 store float %conv, ptr %b.addr, align 4 182 ret void 183} 184 185define void @uitofp_single_i32(i32 %a, float %b) nounwind { 186entry: 187; CHECK: uitofp_single_i32 188; PPC970: uitofp_single_i32 189 %b.addr = alloca float, align 4 190 %conv = uitofp i32 %a to float 191; CHECK: std 192; CHECK-NOT: ori 193; CHECK: li 194; CHECK-NOT: ori 195; CHECK: lfiwzx 196; CHECK: fcfidus 197; PPC970-NOT: lfiwzx 198; PPC970-NOT: fcfidus 199; SPE: efscfui 200 store float %conv, ptr %b.addr, align 4 201 ret void 202} 203 204define void @uitofp_single_i16(i16 %a, float %b) nounwind { 205entry: 206; CHECK: uitofp_single_i16 207; PPC970: uitofp_single_i16 208 %b.addr = alloca float, align 4 209 %conv = uitofp i16 %a to float 210; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 211; CHECK: std 212; CHECK: lfd 213; CHECK: fcfidus 214; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 215; PPC970: std 216; PPC970: lfd 217; PPC970: fcfid 218; PPC970: frsp 219; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 220; SPE: efscfui 221 store float %conv, ptr %b.addr, align 4 222 ret void 223} 224 225define void @uitofp_single_i8(i8 %a) nounwind { 226entry: 227; CHECK: uitofp_single_i8 228; PPC970: uitofp_single_i8 229 %b.addr = alloca float, align 4 230 %conv = uitofp i8 %a to float 231; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 232; CHECK: std 233; CHECK: lfd 234; CHECK: fcfidus 235; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 236; PPC970: std 237; PPC970: lfd 238; PPC970: fcfid 239; PPC970: frsp 240; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 241; SPE: efscfui 242 store float %conv, ptr %b.addr, align 4 243 ret void 244} 245 246define void @uitofp_double_i64(i64 %a, double %b) nounwind { 247entry: 248; CHECK: uitofp_double_i64 249; PPC970: uitofp_double_i64 250 %b.addr = alloca double, align 8 251 %conv = uitofp i64 %a to double 252; CHECK: std 253; CHECK: lfd 254; CHECK: fcfidu 255; PPC970-NOT: fcfidu 256 store double %conv, ptr %b.addr, align 8 257 ret void 258} 259 260define void @uitofp_double_i32(i32 %a, double %b) nounwind { 261entry: 262; CHECK: uitofp_double_i32 263; PPC970: uitofp_double_i32 264 %b.addr = alloca double, align 8 265 %conv = uitofp i32 %a to double 266; CHECK: std 267; CHECK-NEXT: li 268; CHECK-NEXT: lfiwzx 269; CHECK-NEXT: fcfidu 270; PPC970-NOT: lfiwzx 271; PPC970-NOT: fcfidu 272; SPE: efdcfui 273 store double %conv, ptr %b.addr, align 8 274 ret void 275} 276 277define void @uitofp_double_i16(i16 %a, double %b) nounwind { 278entry: 279; CHECK: uitofp_double_i16 280; PPC970: uitofp_double_i16 281 %b.addr = alloca double, align 8 282 %conv = uitofp i16 %a to double 283; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 48 284; CHECK: std 285; CHECK: lfd 286; CHECK: fcfidu 287; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 288; PPC970: std 289; PPC970: lfd 290; PPC970: fcfid 291; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 292; SPE: efdcfui 293 store double %conv, ptr %b.addr, align 8 294 ret void 295} 296 297define void @uitofp_double_i8(i8 %a, double %b) nounwind { 298entry: 299; CHECK: uitofp_double_i8 300; PPC970: uitofp_double_i8 301 %b.addr = alloca double, align 8 302 %conv = uitofp i8 %a to double 303; CHECK: clrldi {{[0-9]+}}, {{[0-9]+}}, 56 304; CHECK: std 305; CHECK: lfd 306; CHECK: fcfidu 307; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 308; PPC970: std 309; PPC970: lfd 310; PPC970: fcfid 311; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 312; SPE: efdcfui 313 store double %conv, ptr %b.addr, align 8 314 ret void 315} 316 317; Test fptosi 318 319define void @fptosi_float_i32(float %a) nounwind { 320entry: 321; CHECK: fptosi_float_i32 322; PPC970: fptosi_float_i32 323 %b.addr = alloca i32, align 4 324 %conv = fptosi float %a to i32 325; CHECK: fctiwz 326; CHECK: stfd 327; CHECK: lwa 328; PPC970: fctiwz 329; PPC970: stfd 330; PPC970: lwa 331; SPE: efsctsi 332 store i32 %conv, ptr %b.addr, align 4 333 ret void 334} 335 336define void @fptosi_float_i64(float %a) nounwind { 337entry: 338; CHECK: fptosi_float_i64 339; PPC970: fptosi_float_i64 340 %b.addr = alloca i64, align 4 341 %conv = fptosi float %a to i64 342; CHECK: fctidz 343; CHECK: stfd 344; CHECK: ld 345; PPC970: fctidz 346; PPC970: stfd 347; PPC970: ld 348 store i64 %conv, ptr %b.addr, align 4 349 ret void 350} 351 352define void @fptosi_double_i32(double %a) nounwind { 353entry: 354; CHECK: fptosi_double_i32 355; PPC970: fptosi_double_i32 356 %b.addr = alloca i32, align 8 357 %conv = fptosi double %a to i32 358; CHECK: fctiwz 359; CHECK: stfd 360; CHECK: lwa 361; PPC970: fctiwz 362; PPC970: stfd 363; PPC970: lwa 364; SPE: efdctsi 365 store i32 %conv, ptr %b.addr, align 8 366 ret void 367} 368 369define void @fptosi_double_i64(double %a) nounwind { 370entry: 371; CHECK: fptosi_double_i64 372; PPC970: fptosi_double_i64 373 %b.addr = alloca i64, align 8 374 %conv = fptosi double %a to i64 375; CHECK: fctidz 376; CHECK: stfd 377; CHECK: ld 378; PPC970: fctidz 379; PPC970: stfd 380; PPC970: ld 381 store i64 %conv, ptr %b.addr, align 8 382 ret void 383} 384 385; Test fptoui 386 387define void @fptoui_float_i32(float %a) nounwind { 388entry: 389; CHECK: fptoui_float_i32 390; PPC970: fptoui_float_i32 391 %b.addr = alloca i32, align 4 392 %conv = fptoui float %a to i32 393; CHECK: fctiwuz 394; CHECK: stfd 395; CHECK: lwz 396; PPC970: fctidz 397; PPC970: stfd 398; PPC970: lwz 399; SPE: efsctui 400 store i32 %conv, ptr %b.addr, align 4 401 ret void 402} 403 404define void @fptoui_float_i64(float %a) nounwind { 405entry: 406; CHECK: fptoui_float_i64 407; PPC970: fptoui_float_i64 408 %b.addr = alloca i64, align 4 409 %conv = fptoui float %a to i64 410; CHECK: fctiduz 411; CHECK: stfd 412; CHECK: ld 413; PPC970-NOT: fctiduz 414 store i64 %conv, ptr %b.addr, align 4 415 ret void 416} 417 418define void @fptoui_double_i32(double %a) nounwind { 419entry: 420; CHECK: fptoui_double_i32 421; PPC970: fptoui_double_i32 422 %b.addr = alloca i32, align 8 423 %conv = fptoui double %a to i32 424; CHECK: fctiwuz 425; CHECK: stfd 426; CHECK: lwz 427; PPC970: fctidz 428; PPC970: stfd 429; PPC970: lwz 430; SPE: efdctui 431 store i32 %conv, ptr %b.addr, align 8 432 ret void 433} 434 435define void @fptoui_double_i64(double %a) nounwind { 436entry: 437; CHECK: fptoui_double_i64 438; PPC970: fptoui_double_i64 439 %b.addr = alloca i64, align 8 440 %conv = fptoui double %a to i64 441; CHECK: fctiduz 442; CHECK: stfd 443; CHECK: ld 444; PPC970-NOT: fctiduz 445 store i64 %conv, ptr %b.addr, align 8 446 ret void 447} 448