xref: /llvm-project/llvm/test/CodeGen/PowerPC/fast-isel-binary.ll (revision 427fb35192f1f7bb694a5910b05abc5925a798b2) 
1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
3
4; Test add with non-legal types
5
6define void @add_i8(i8 %a, i8 %b) nounwind {
7entry:
8; PPC64: add_i8
9  %a.addr = alloca i8, align 4
10  %0 = add i8 %a, %b
11; PPC64: add
12  store i8 %0, ptr %a.addr, align 4
13  ret void
14}
15
16define void @add_i8_imm(i8 %a) nounwind {
17entry:
18; PPC64: add_i8_imm
19  %a.addr = alloca i8, align 4
20  %0 = add i8 %a, 22;
21; PPC64: addi
22  store i8 %0, ptr %a.addr, align 4
23  ret void
24}
25
26define void @add_i16(i16 %a, i16 %b) nounwind {
27entry:
28; PPC64: add_i16
29  %a.addr = alloca i16, align 4
30  %0 = add i16 %a, %b
31; PPC64: add
32  store i16 %0, ptr %a.addr, align 4
33  ret void
34}
35
36define void @add_i16_imm(i16 %a, i16 %b) nounwind {
37entry:
38; PPC64: add_i16_imm
39  %a.addr = alloca i16, align 4
40  %0 = add i16 %a, 243;
41; PPC64: addi
42  store i16 %0, ptr %a.addr, align 4
43  ret void
44}
45
46; Test or with non-legal types
47
48define void @or_i8(i8 %a, i8 %b) nounwind {
49entry:
50; PPC64: or_i8
51  %a.addr = alloca i8, align 4
52  %0 = or i8 %a, %b
53; PPC64: or
54  store i8 %0, ptr %a.addr, align 4
55  ret void
56}
57
58define void @or_i8_imm(i8 %a) nounwind {
59entry:
60; PPC64: or_i8_imm
61  %a.addr = alloca i8, align 4
62  %0 = or i8 %a, -13;
63; PPC64: ori
64  store i8 %0, ptr %a.addr, align 4
65  ret void
66}
67
68define void @or_i16(i16 %a, i16 %b) nounwind {
69entry:
70; PPC64: or_i16
71  %a.addr = alloca i16, align 4
72  %0 = or i16 %a, %b
73; PPC64: or
74  store i16 %0, ptr %a.addr, align 4
75  ret void
76}
77
78define void @or_i16_imm(i16 %a) nounwind {
79entry:
80; PPC64: or_i16_imm
81  %a.addr = alloca i16, align 4
82  %0 = or i16 %a, 273;
83; PPC64: ori
84  store i16 %0, ptr %a.addr, align 4
85  ret void
86}
87
88; Test sub with non-legal types
89
90define void @sub_i8(i8 %a, i8 %b) nounwind {
91entry:
92; PPC64: sub_i8
93  %a.addr = alloca i8, align 4
94  %0 = sub i8 %a, %b
95; PPC64: sub
96  store i8 %0, ptr %a.addr, align 4
97  ret void
98}
99
100define void @sub_i8_imm(i8 %a) nounwind {
101entry:
102; PPC64: sub_i8_imm
103  %a.addr = alloca i8, align 4
104  %0 = sub i8 %a, 22;
105; PPC64: addi
106  store i8 %0, ptr %a.addr, align 4
107  ret void
108}
109
110define void @sub_i16(i16 %a, i16 %b) nounwind {
111entry:
112; PPC64: sub_i16
113  %a.addr = alloca i16, align 4
114  %0 = sub i16 %a, %b
115; PPC64: sub
116  store i16 %0, ptr %a.addr, align 4
117  ret void
118}
119
120define void @sub_i16_imm(i16 %a) nounwind {
121entry:
122; PPC64: sub_i16_imm
123  %a.addr = alloca i16, align 4
124  %0 = sub i16 %a, 247;
125; PPC64: addi
126  store i16 %0, ptr %a.addr, align 4
127  ret void
128}
129
130define void @sub_i16_badimm(i16 %a) nounwind {
131entry:
132; PPC64: sub_i16_imm
133  %a.addr = alloca i16, align 4
134  %0 = sub i16 %a, -32768;
135; PPC64: sub
136  store i16 %0, ptr %a.addr, align 4
137  ret void
138}
139