xref: /llvm-project/llvm/test/CodeGen/PowerPC/dform-adjust.ll (revision 427fb35192f1f7bb694a5910b05abc5925a798b2)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3; RUN:   -mcpu=pwr9 < %s | FileCheck %s
4define dso_local i64 @test1(ptr nocapture readonly %p, i32 signext %count) local_unnamed_addr #0 {
5; CHECK-LABEL: test1:
6; CHECK:       # %bb.0: # %entry
7; CHECK-NEXT:    li 5, -13
8; CHECK-NEXT:    li 6, 7
9; CHECK-NEXT:    li 7, 11
10; CHECK-NEXT:    li 8, 15
11; CHECK-NEXT:    lxvx 0, 3, 5
12; CHECK-NEXT:    li 5, 19
13; CHECK-NEXT:    ldx 6, 3, 6
14; CHECK-NEXT:    ldx 7, 3, 7
15; CHECK-NEXT:    lxvx 1, 3, 5
16; CHECK-NEXT:    li 5, 3
17; CHECK-NEXT:    ldx 5, 3, 5
18; CHECK-NEXT:    ldx 3, 3, 8
19; CHECK-NEXT:    mfvsrld 9, 0
20; CHECK-NEXT:    mffprd 8, 0
21; CHECK-NEXT:    mfvsrld 10, 1
22; CHECK-NEXT:    mffprd 11, 1
23; CHECK-NEXT:    mulld 8, 9, 8
24; CHECK-NEXT:    mulld 5, 8, 5
25; CHECK-NEXT:    mulld 5, 5, 10
26; CHECK-NEXT:    mulld 5, 5, 11
27; CHECK-NEXT:    mulld 5, 5, 6
28; CHECK-NEXT:    mulld 5, 5, 7
29; CHECK-NEXT:    maddld 3, 5, 3, 4
30; CHECK-NEXT:    blr
31entry:
32  %add.ptr = getelementptr inbounds i8, ptr %p, i64 -13
33  %0 = load <2 x i64>, ptr %add.ptr, align 16
34  %add.ptr1 = getelementptr inbounds i8, ptr %p, i64 19
35  %1 = load <2 x i64>, ptr %add.ptr1, align 16
36  %add.ptr3 = getelementptr inbounds i8, ptr %p, i64 3
37  %2 = load i64, ptr %add.ptr3, align 8
38  %add.ptr5 = getelementptr inbounds i8, ptr %p, i64 7
39  %3 = load i64, ptr %add.ptr5, align 8
40  %add.ptr7 = getelementptr inbounds i8, ptr %p, i64 11
41  %4 = load i64, ptr %add.ptr7, align 8
42  %add.ptr9 = getelementptr inbounds i8, ptr %p, i64 15
43  %5 = load i64, ptr %add.ptr9, align 8
44  %vecext = extractelement <2 x i64> %0, i32 1
45  %vecext13 = extractelement <2 x i64> %0, i32 0
46  %vecext15 = extractelement <2 x i64> %1, i32 0
47  %vecext17 = extractelement <2 x i64> %1, i32 1
48  %mul = mul i64 %vecext13, %vecext
49  %mul10 = mul i64 %mul, %2
50  %mul11 = mul i64 %mul10, %vecext15
51  %mul12 = mul i64 %mul11, %vecext17
52  %mul14 = mul i64 %mul12, %3
53  %mul16 = mul i64 %mul14, %4
54  %mul18 = mul i64 %mul16, %5
55  %conv = sext i32 %count to i64
56  %add19 = add i64 %mul18, %conv
57  ret i64 %add19
58}
59
60define dso_local i64 @test2(ptr nocapture readonly %p, i32 signext %count) local_unnamed_addr #0 {
61; CHECK-LABEL: test2:
62; CHECK:       # %bb.0: # %entry
63; CHECK-NEXT:    li 5, 0
64; CHECK-NEXT:    ori 6, 5, 40009
65; CHECK-NEXT:    ori 7, 5, 40001
66; CHECK-NEXT:    ori 5, 5, 40005
67; CHECK-NEXT:    ldx 6, 3, 6
68; CHECK-NEXT:    ldx 7, 3, 7
69; CHECK-NEXT:    ldx 3, 3, 5
70; CHECK-NEXT:    mulld 5, 7, 6
71; CHECK-NEXT:    maddld 3, 5, 3, 4
72; CHECK-NEXT:    blr
73entry:
74  %add.ptr = getelementptr inbounds i8, ptr %p, i64 40009
75  %0 = load i64, ptr %add.ptr, align 8
76  %add.ptr2 = getelementptr inbounds i8, ptr %p, i64 40001
77  %1 = load i64, ptr %add.ptr2, align 8
78  %add.ptr4 = getelementptr inbounds i8, ptr %p, i64 40005
79  %2 = load i64, ptr %add.ptr4, align 8
80  %mul = mul i64 %1, %0
81  %mul5 = mul i64 %mul, %2
82  %conv = sext i32 %count to i64
83  %add6 = add i64 %mul5, %conv
84  ret i64 %add6
85}
86
87define dso_local i64 @test3(ptr nocapture readonly %p, i32 signext %count) local_unnamed_addr {
88; CHECK-LABEL: test3:
89; CHECK:       # %bb.0: # %entry
90; CHECK-NEXT:    lis 5, 1
91; CHECK-NEXT:    ori 6, 5, 14497
92; CHECK-NEXT:    ori 7, 5, 14465
93; CHECK-NEXT:    ori 5, 5, 14481
94; CHECK-NEXT:    ldx 6, 3, 6
95; CHECK-NEXT:    ldx 7, 3, 7
96; CHECK-NEXT:    ldx 3, 3, 5
97; CHECK-NEXT:    mulld 5, 7, 6
98; CHECK-NEXT:    maddld 3, 5, 3, 4
99; CHECK-NEXT:    blr
100entry:
101  %add.ptr = getelementptr inbounds i8, ptr %p, i64 80033
102  %0 = load i64, ptr %add.ptr, align 8
103  %add.ptr2 = getelementptr inbounds i8, ptr %p, i64 80001
104  %1 = load i64, ptr %add.ptr2, align 8
105  %add.ptr4 = getelementptr inbounds i8, ptr %p, i64 80017
106  %2 = load i64, ptr %add.ptr4, align 8
107  %mul = mul i64 %1, %0
108  %mul5 = mul i64 %mul, %2
109  %conv = sext i32 %count to i64
110  %add6 = add i64 %mul5, %conv
111  ret i64 %add6
112}
113
114