xref: /llvm-project/llvm/test/CodeGen/PowerPC/dcbt-sched.ll (revision 427fb35192f1f7bb694a5910b05abc5925a798b2)
1target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
2target triple = "powerpc64-unknown-linux-gnu"
3; RUN: llc -verify-machineinstrs -mcpu=a2 -enable-misched -enable-aa-sched-mi < %s | FileCheck %s
4
5define i8 @test1(ptr noalias %a, ptr noalias %b, ptr noalias %c) nounwind {
6entry:
7  %q = load i8, ptr %b
8  call void @llvm.prefetch(ptr %a, i32 0, i32 3, i32 1)
9  %r = load i8, ptr %c
10  %s = add i8 %q, %r
11  ret i8 %s
12}
13
14declare void @llvm.prefetch(ptr, i32, i32, i32)
15
16; Test that we've moved the second load to before the dcbt to better
17; hide its latency.
18; CHECK: @test1
19; CHECK: lbz
20; CHECK: lbz
21; CHECK: dcbt
22
23