1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck %s 3; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=ppc64 < %s | FileCheck %s 4 5; Function Attrs: nounwind readnone 6define i64 @cn1() #0 { 7; CHECK-LABEL: cn1: 8; CHECK: # %bb.0: # %entry 9; CHECK-NEXT: li 3, -1 10; CHECK-NEXT: rldic 3, 3, 0, 16 11; CHECK-NEXT: blr 12entry: 13 ret i64 281474976710655 14 15} 16 17; Function Attrs: nounwind readnone 18define i64 @cnb() #0 { 19; CHECK-LABEL: cnb: 20; CHECK: # %bb.0: # %entry 21; CHECK-NEXT: li 3, -81 22; CHECK-NEXT: rldic 3, 3, 0, 16 23; CHECK-NEXT: blr 24entry: 25 ret i64 281474976710575 26 27} 28 29; Function Attrs: nounwind readnone 30define i64 @f2(i64 %x) #0 { 31; CHECK-LABEL: f2: 32; CHECK: # %bb.0: # %entry 33; CHECK-NEXT: li 3, -1 34; CHECK-NEXT: rldic 3, 3, 36, 0 35; CHECK-NEXT: blr 36entry: 37 ret i64 -68719476736 38 39} 40 41; Function Attrs: nounwind readnone 42define i64 @f2a(i64 %x) #0 { 43; CHECK-LABEL: f2a: 44; CHECK: # %bb.0: # %entry 45; CHECK-NEXT: li 3, -337 46; CHECK-NEXT: rldic 3, 3, 30, 0 47; CHECK-NEXT: blr 48entry: 49 ret i64 -361850994688 50 51} 52 53; Function Attrs: nounwind readnone 54define i64 @f2n(i64 %x) #0 { 55; CHECK-LABEL: f2n: 56; CHECK: # %bb.0: # %entry 57; CHECK-NEXT: li 3, -1 58; CHECK-NEXT: rldic 3, 3, 0, 28 59; CHECK-NEXT: blr 60entry: 61 ret i64 68719476735 62 63} 64 65; Function Attrs: nounwind readnone 66define i64 @f3(i64 %x) #0 { 67; CHECK-LABEL: f3: 68; CHECK: # %bb.0: # %entry 69; CHECK-NEXT: li 3, -1 70; CHECK-NEXT: rldic 3, 3, 0, 31 71; CHECK-NEXT: blr 72entry: 73 ret i64 8589934591 74 75} 76 77; Function Attrs: nounwind readnone 78define i64 @cn2n() #0 { 79; CHECK-LABEL: cn2n: 80; CHECK: # %bb.0: # %entry 81; CHECK-NEXT: lis 3, -5121 82; CHECK-NEXT: ori 3, 3, 65534 83; CHECK-NEXT: rotldi 3, 3, 22 84; CHECK-NEXT: blr 85entry: 86 ret i64 -1407374887747585 87 88} 89 90define i64 @uint32_1() #0 { 91; CHECK-LABEL: uint32_1: 92; CHECK: # %bb.0: # %entry 93; CHECK-NEXT: li 3, 18176 94; CHECK-NEXT: oris 3, 3, 59509 95; CHECK-NEXT: blr 96entry: 97 ret i64 3900000000 98 99} 100 101define i32 @uint32_1_i32() #0 { 102; CHECK-LABEL: uint32_1_i32: 103; CHECK: # %bb.0: # %entry 104; CHECK-NEXT: li 3, 18176 105; CHECK-NEXT: oris 3, 3, 59509 106; CHECK-NEXT: blr 107entry: 108 ret i32 -394967296 109 110} 111 112define i64 @uint32_2() #0 { 113; CHECK-LABEL: uint32_2: 114; CHECK: # %bb.0: # %entry 115; CHECK-NEXT: li 3, -1 116; CHECK-NEXT: rldic 3, 3, 0, 32 117; CHECK-NEXT: blr 118entry: 119 ret i64 4294967295 120 121} 122 123define i32 @uint32_2_i32() #0 { 124; CHECK-LABEL: uint32_2_i32: 125; CHECK: # %bb.0: # %entry 126; CHECK-NEXT: li 3, -1 127; CHECK-NEXT: rldic 3, 3, 0, 32 128; CHECK-NEXT: blr 129entry: 130 ret i32 -1 131 132} 133 134define i64 @uint32_3() #0 { 135; CHECK-LABEL: uint32_3: 136; CHECK: # %bb.0: # %entry 137; CHECK-NEXT: li 3, 1 138; CHECK-NEXT: rldic 3, 3, 31, 32 139; CHECK-NEXT: blr 140entry: 141 ret i64 2147483648 142 143} 144 145define i64 @uint32_4() #0 { 146; CHECK-LABEL: uint32_4: 147; CHECK: # %bb.0: # %entry 148; CHECK-NEXT: lis 3, -6027 149; CHECK-NEXT: ori 3, 3, 18177 150; CHECK-NEXT: rldic 3, 3, 5, 27 151; CHECK-NEXT: blr 152entry: 153 ret i64 124800000032 154 155} 156 157define i64 @cn_ones_1() #0 { 158; CHECK-LABEL: cn_ones_1: 159; CHECK: # %bb.0: # %entry 160; CHECK-NEXT: li 3, -25633 161; CHECK-NEXT: rldicl 3, 3, 18, 30 162; CHECK-NEXT: blr 163entry: 164 ret i64 10460594175 165 166} 167 168define i64 @cn_ones_2() #0 { 169; CHECK-LABEL: cn_ones_2: 170; CHECK: # %bb.0: # %entry 171; CHECK-NEXT: lis 3, -25638 172; CHECK-NEXT: ori 3, 3, 24575 173; CHECK-NEXT: rldicl 3, 3, 2, 30 174; CHECK-NEXT: blr 175entry: 176 ret i64 10459119615 177 178} 179 180define i64 @imm1() #0 { 181; CHECK-LABEL: imm1: 182; CHECK: # %bb.0: # %entry 183; CHECK-NEXT: li 3, 8465 184; CHECK-NEXT: rldic 3, 3, 28, 22 185; CHECK-NEXT: blr 186entry: 187 ret i64 2272306135040 ;0x21110000000 188} 189 190define i64 @imm2() #0 { 191; CHECK-LABEL: imm2: 192; CHECK: # %bb.0: # %entry 193; CHECK-NEXT: li 3, -28536 194; CHECK-NEXT: rldicl 3, 3, 1, 32 195; CHECK-NEXT: blr 196entry: 197 ret i64 4294910225 ;0xFFFF2111 198} 199 200define i64 @imm3() #0 { 201; CHECK-LABEL: imm3: 202; CHECK: # %bb.0: # %entry 203; CHECK-NEXT: li 3, -32495 204; CHECK-NEXT: rldic 3, 3, 0, 32 205; CHECK-NEXT: blr 206entry: 207 ret i64 4294934801 ;0xFFFF8111 208} 209 210define i64 @imm4() #0 { 211; CHECK-LABEL: imm4: 212; CHECK: # %bb.0: # %entry 213; CHECK-NEXT: lis 3, 33 214; CHECK-NEXT: ori 3, 3, 4352 215; CHECK-NEXT: rldimi 3, 3, 32, 0 216; CHECK-NEXT: blr 217entry: 218 ret i64 9307365931290880 ;0x21110000211100 219} 220 221define i64 @imm5() #0 { 222; CHECK-LABEL: imm5: 223; CHECK: # %bb.0: # %entry 224; CHECK-NEXT: li 3, 28685 225; CHECK-NEXT: rotldi 3, 3, 52 226; CHECK-NEXT: blr 227entry: 228 ret i64 58546795155816455 ;0xd0000000000007 229} 230 231define i64 @imm6() #0 { 232; CHECK-LABEL: imm6: 233; CHECK: # %bb.0: # %entry 234; CHECK-NEXT: lis 3, -1 235; CHECK-NEXT: ori 3, 3, 28674 236; CHECK-NEXT: rotldi 3, 3, 52 237; CHECK-NEXT: blr 238entry: 239 ret i64 13510798882111479 ;0x2ffffffffffff7 240} 241 242define i64 @imm7() #0 { 243; CHECK-LABEL: imm7: 244; CHECK: # %bb.0: # %entry 245; CHECK-NEXT: li 3, -3823 246; CHECK-NEXT: rldic 3, 3, 28, 20 247; CHECK-NEXT: blr 248entry: 249 ret i64 16565957296128 ;0xf1110000000 250} 251 252define i64 @imm8() #0 { 253; CHECK-LABEL: imm8: 254; CHECK: # %bb.0: # %entry 255; CHECK-NEXT: li 3, -7919 256; CHECK-NEXT: rldic 3, 3, 22, 22 257; CHECK-NEXT: blr 258entry: 259 ret i64 4364831817728 ;0x3f844400000 260} 261 262define i64 @imm9() #0 { 263; CHECK-LABEL: imm9: 264; CHECK: # %bb.0: # %entry 265; CHECK-NEXT: lis 3, -1 266; CHECK-NEXT: ori 3, 3, 28674 267; CHECK-NEXT: rotldi 3, 3, 52 268; CHECK-NEXT: blr 269entry: 270 ret i64 13510798882111479 ;0x2ffffffffffff7 271} 272 273define i64 @imm10() #0 { 274; CHECK-LABEL: imm10: 275; CHECK: # %bb.0: # %entry 276; CHECK-NEXT: li 3, -3823 277; CHECK-NEXT: rldic 3, 3, 28, 20 278; CHECK-NEXT: blr 279entry: 280 ret i64 16565957296128 ;0xf1110000000 281} 282 283define i64 @imm11() #0 { 284; CHECK-LABEL: imm11: 285; CHECK: # %bb.0: # %entry 286; CHECK-NEXT: li 3, -7919 287; CHECK-NEXT: rldic 3, 3, 22, 22 288; CHECK-NEXT: blr 289entry: 290 ret i64 4364831817728 ;0x3f844400000 291} 292 293define i64 @imm12() #0 { 294; CHECK-LABEL: imm12: 295; CHECK: # %bb.0: # %entry 296; CHECK-NEXT: lis 3, -29 297; CHECK-NEXT: ori 3, 3, 64577 298; CHECK-NEXT: rldic 3, 3, 12, 20 299; CHECK-NEXT: blr 300entry: 301 ret i64 17584665923584 ;0xffe3fc41000 302} 303 304define i64 @imm13() #0 { 305; CHECK-LABEL: imm13: 306; CHECK: # %bb.0: # %entry 307; CHECK-NEXT: li 3, -24847 308; CHECK-NEXT: rldicl 3, 3, 21, 27 309; CHECK-NEXT: blr 310entry: 311 ret i64 85333114879 ;0x13de3fffff 312} 313 314define i64 @imm13_2() #0 { 315; CHECK-LABEL: imm13_2: 316; CHECK: # %bb.0: # %entry 317; CHECK-NEXT: li 3, -12424 318; CHECK-NEXT: rldicl 3, 3, 22, 26 319; CHECK-NEXT: blr 320entry: 321 ret i64 222772068351 ;0x33de3fffff 322} 323 324define i64 @imm14() #0 { 325; CHECK-LABEL: imm14: 326; CHECK: # %bb.0: # %entry 327; CHECK-NEXT: li 3, -3960 328; CHECK-NEXT: rldicl 3, 3, 21, 24 329; CHECK-NEXT: blr 330entry: 331 ret i64 1091209003007 ;0xfe111fffff 332} 333 334define i64 @imm15() #0 { 335; CHECK-LABEL: imm15: 336; CHECK: # %bb.0: # %entry 337; CHECK-NEXT: li 3, -8065 338; CHECK-NEXT: rldic 3, 3, 24, 0 339; CHECK-NEXT: blr 340entry: 341 ret i64 -135308247040 342} 343 344define i64 @imm16() #0 { 345; CHECK-LABEL: imm16: 346; CHECK: # %bb.0: # %entry 347; CHECK-NEXT: lis 3, -16392 348; CHECK-NEXT: ori 3, 3, 57217 349; CHECK-NEXT: rldic 3, 3, 16, 0 350; CHECK-NEXT: blr 351entry: 352 ret i64 -70399354142720 353} 354 355define i64 @imm17() #0 { 356; CHECK-LABEL: imm17: 357; CHECK: # %bb.0: # %entry 358; CHECK-NEXT: lis 3, 20344 359; CHECK-NEXT: ori 3, 3, 32847 360; CHECK-NEXT: rotldi 3, 3, 49 361; CHECK-NEXT: blr 362entry: 363 ret i64 44473046320324337 ;0x9e000000009ef1 364} 365 366define i64 @imm18() #0 { 367; CHECK-LABEL: imm18: 368; CHECK: # %bb.0: # %entry 369; CHECK-NEXT: li 3, 1 370; CHECK-NEXT: rldic 3, 3, 33, 30 371; CHECK-NEXT: oris 3, 3, 39436 372; CHECK-NEXT: ori 3, 3, 61633 373; CHECK-NEXT: blr 374entry: 375 ret i64 11174473921 376} 377 378define i64 @imm19() { 379; CHECK-LABEL: imm19: 380; CHECK: # %bb.0: # %entry 381; CHECK-NEXT: lis 3, -13105 382; CHECK-NEXT: ori 3, 3, 52479 383; CHECK-NEXT: rldic 3, 3, 32, 0 384; CHECK-NEXT: oris 3, 3, 52431 385; CHECK-NEXT: ori 3, 3, 291 386; CHECK-NEXT: blr 387entry: 388 ret i64 14758239902941249827 ;0xCCCFCCFFCCCF0123 389} 390 391define i64 @imm20() { 392; CHECK-LABEL: imm20: 393; CHECK: # %bb.0: # %entry 394; CHECK-NEXT: lis 3, 291 395; CHECK-NEXT: ori 3, 3, 52479 396; CHECK-NEXT: rldimi 3, 3, 32, 0 397; CHECK-NEXT: rldimi 3, 3, 48, 0 398; CHECK-NEXT: blr 399entry: 400 ret i64 14771750698406366463 ;0xCCFFCCFF0123CCFF 401} 402 403define i64 @imm21() { 404; CHECK-LABEL: imm21: 405; CHECK: # %bb.0: # %entry 406; CHECK-NEXT: lis 3, -13057 407; CHECK-NEXT: ori 3, 3, 291 408; CHECK-NEXT: rldimi 3, 3, 32, 0 409; CHECK-NEXT: rlwimi 3, 3, 16, 16, 31 410; CHECK-NEXT: blr 411entry: 412 ret i64 14771526556073315583 ;0xCCFF0123CCFFCCFF 413} 414 415define i64 @imm22() { 416; CHECK-LABEL: imm22: 417; CHECK: # %bb.0: # %entry 418; CHECK-NEXT: lis 3, 291 419; CHECK-NEXT: ori 3, 3, 52479 420; CHECK-NEXT: rldimi 3, 3, 32, 0 421; CHECK-NEXT: rlwimi 3, 3, 16, 0, 15 422; CHECK-NEXT: blr 423entry: 424 ret i64 82134617250843903 ;0x0123CCFFCCFFCCFF 425} 426 427define i64 @imm23() { 428; CHECK-LABEL: imm23: 429; CHECK: # %bb.0: # %entry 430; CHECK-NEXT: li 3, 32767 431; CHECK-NEXT: rldimi 3, 3, 32, 0 432; CHECK-NEXT: blr 433entry: 434 ret i64 140733193420799 ;0x00007FFF00007FFF 435} 436 437define i64 @imm24() { 438; CHECK-LABEL: imm24: 439; CHECK: # %bb.0: # %entry 440; CHECK-NEXT: lis 3, -9 441; CHECK-NEXT: rldimi 3, 3, 32, 0 442; CHECK-NEXT: blr 443entry: 444 ret i64 18444210803213533184 ;0xFFF70000FFF70000 445} 446 447attributes #0 = { nounwind readnone } 448