1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 2; RUN: llc -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -verify-machineinstrs \ 3; RUN: -mtriple=powerpc64-- -mcpu=pwr7 < %s | FileCheck \ 4; RUN: --check-prefix=PWR7-BE %s 5; RUN: llc -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -verify-machineinstrs \ 6; RUN: -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck \ 7; RUN: --check-prefix=PWR8-BE %s 8; RUN: llc -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -verify-machineinstrs \ 9; RUN: -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck \ 10; RUN: --check-prefix=PWR8-LE %s 11 12define <16 x i8> @i8(ptr nocapture noundef readonly %p) { 13; PWR7-BE-LABEL: i8: 14; PWR7-BE: # %bb.0: # %entry 15; PWR7-BE-NEXT: lxvw4x v3, 0, r3 16; PWR7-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha 17; PWR7-BE-NEXT: vspltisb v2, 10 18; PWR7-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l 19; PWR7-BE-NEXT: lxvw4x v4, 0, r3 20; PWR7-BE-NEXT: vperm v2, v3, v2, v4 21; PWR7-BE-NEXT: blr 22; 23; PWR8-BE-LABEL: i8: 24; PWR8-BE: # %bb.0: # %entry 25; PWR8-BE-NEXT: lxvw4x v2, 0, r3 26; PWR8-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha 27; PWR8-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l 28; PWR8-BE-NEXT: lxvw4x v3, 0, r3 29; PWR8-BE-NEXT: li r3, 10 30; PWR8-BE-NEXT: mtvsrwz v4, r3 31; PWR8-BE-NEXT: vperm v2, v2, v4, v3 32; PWR8-BE-NEXT: blr 33; 34; PWR8-LE-LABEL: i8: 35; PWR8-LE: # %bb.0: # %entry 36; PWR8-LE-NEXT: lxvd2x vs0, 0, r3 37; PWR8-LE-NEXT: addis r3, r2, .LCPI0_0@toc@ha 38; PWR8-LE-NEXT: addi r3, r3, .LCPI0_0@toc@l 39; PWR8-LE-NEXT: xxswapd v2, vs0 40; PWR8-LE-NEXT: lxvd2x vs0, 0, r3 41; PWR8-LE-NEXT: li r3, 10 42; PWR8-LE-NEXT: mtvsrd v4, r3 43; PWR8-LE-NEXT: xxswapd v3, vs0 44; PWR8-LE-NEXT: vperm v2, v4, v2, v3 45; PWR8-LE-NEXT: blr 46entry: 47 %0 = load <16 x i8>, ptr %p, align 16 48 %vecinit1 = insertelement <16 x i8> %0, i8 10, i64 1 49 ret <16 x i8> %vecinit1 50} 51 52define <8 x i16> @i16(ptr nocapture noundef readonly %p) { 53; PWR7-BE-LABEL: i16: 54; PWR7-BE: # %bb.0: # %entry 55; PWR7-BE-NEXT: lxvw4x v3, 0, r3 56; PWR7-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha 57; PWR7-BE-NEXT: vspltish v2, 9 58; PWR7-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l 59; PWR7-BE-NEXT: lxvw4x v4, 0, r3 60; PWR7-BE-NEXT: vperm v2, v3, v2, v4 61; PWR7-BE-NEXT: blr 62; 63; PWR8-BE-LABEL: i16: 64; PWR8-BE: # %bb.0: # %entry 65; PWR8-BE-NEXT: lxvw4x v2, 0, r3 66; PWR8-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha 67; PWR8-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l 68; PWR8-BE-NEXT: lxvw4x v3, 0, r3 69; PWR8-BE-NEXT: li r3, 9 70; PWR8-BE-NEXT: mtvsrwz v4, r3 71; PWR8-BE-NEXT: vperm v2, v2, v4, v3 72; PWR8-BE-NEXT: blr 73; 74; PWR8-LE-LABEL: i16: 75; PWR8-LE: # %bb.0: # %entry 76; PWR8-LE-NEXT: lxvd2x vs0, 0, r3 77; PWR8-LE-NEXT: addis r3, r2, .LCPI1_0@toc@ha 78; PWR8-LE-NEXT: addi r3, r3, .LCPI1_0@toc@l 79; PWR8-LE-NEXT: xxswapd v2, vs0 80; PWR8-LE-NEXT: lxvd2x vs0, 0, r3 81; PWR8-LE-NEXT: li r3, 9 82; PWR8-LE-NEXT: mtvsrd v4, r3 83; PWR8-LE-NEXT: xxswapd v3, vs0 84; PWR8-LE-NEXT: vperm v2, v4, v2, v3 85; PWR8-LE-NEXT: blr 86entry: 87 %0 = load <8 x i16>, ptr %p, align 16 88 %vecinit1 = insertelement <8 x i16> %0, i16 9, i64 1 89 ret <8 x i16> %vecinit1 90} 91 92define <4 x i32> @i32(ptr nocapture noundef readonly %p) { 93; PWR7-BE-LABEL: i32: 94; PWR7-BE: # %bb.0: # %entry 95; PWR7-BE-NEXT: lxvw4x v3, 0, r3 96; PWR7-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha 97; PWR7-BE-NEXT: vspltisw v2, 7 98; PWR7-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l 99; PWR7-BE-NEXT: lxvw4x v4, 0, r3 100; PWR7-BE-NEXT: vperm v2, v3, v2, v4 101; PWR7-BE-NEXT: blr 102; 103; PWR8-BE-LABEL: i32: 104; PWR8-BE: # %bb.0: # %entry 105; PWR8-BE-NEXT: lxvw4x v2, 0, r3 106; PWR8-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha 107; PWR8-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l 108; PWR8-BE-NEXT: lxvw4x v3, 0, r3 109; PWR8-BE-NEXT: li r3, 7 110; PWR8-BE-NEXT: mtvsrwz v4, r3 111; PWR8-BE-NEXT: vperm v2, v2, v4, v3 112; PWR8-BE-NEXT: blr 113; 114; PWR8-LE-LABEL: i32: 115; PWR8-LE: # %bb.0: # %entry 116; PWR8-LE-NEXT: lxvd2x vs0, 0, r3 117; PWR8-LE-NEXT: addis r3, r2, .LCPI2_0@toc@ha 118; PWR8-LE-NEXT: addi r3, r3, .LCPI2_0@toc@l 119; PWR8-LE-NEXT: xxswapd v2, vs0 120; PWR8-LE-NEXT: lxvd2x vs0, 0, r3 121; PWR8-LE-NEXT: li r3, 7 122; PWR8-LE-NEXT: mtvsrwz v4, r3 123; PWR8-LE-NEXT: xxswapd v3, vs0 124; PWR8-LE-NEXT: vperm v2, v4, v2, v3 125; PWR8-LE-NEXT: blr 126entry: 127 %0 = load <4 x i32>, ptr %p, align 16 128 %vecinit1 = insertelement <4 x i32> %0, i32 7, i64 1 129 ret <4 x i32> %vecinit1 130} 131 132define <2 x i64> @i64(ptr nocapture noundef readonly %p) { 133; PWR7-BE-LABEL: i64: 134; PWR7-BE: # %bb.0: # %entry 135; PWR7-BE-NEXT: lxvd2x v2, 0, r3 136; PWR7-BE-NEXT: li r3, 10 137; PWR7-BE-NEXT: std r3, -16(r1) 138; PWR7-BE-NEXT: std r3, -8(r1) 139; PWR7-BE-NEXT: addi r3, r1, -16 140; PWR7-BE-NEXT: lxvd2x v3, 0, r3 141; PWR7-BE-NEXT: xxmrghd v2, v2, v3 142; PWR7-BE-NEXT: blr 143; 144; PWR8-BE-LABEL: i64: 145; PWR8-BE: # %bb.0: # %entry 146; PWR8-BE-NEXT: lxvd2x v2, 0, r3 147; PWR8-BE-NEXT: li r3, 10 148; PWR8-BE-NEXT: mtfprd f0, r3 149; PWR8-BE-NEXT: xxmrghd v2, v2, vs0 150; PWR8-BE-NEXT: blr 151; 152; PWR8-LE-LABEL: i64: 153; PWR8-LE: # %bb.0: # %entry 154; PWR8-LE-NEXT: lxvd2x vs0, 0, r3 155; PWR8-LE-NEXT: li r3, 10 156; PWR8-LE-NEXT: xxswapd v2, vs0 157; PWR8-LE-NEXT: mtfprd f0, r3 158; PWR8-LE-NEXT: xxpermdi v2, vs0, v2, 1 159; PWR8-LE-NEXT: blr 160entry: 161 %0 = load <2 x i64>, ptr %p, align 16 162 %vecinit1 = insertelement <2 x i64> %0, i64 10, i64 1 163 ret <2 x i64> %vecinit1 164} 165