1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 3; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 4; RUN: -check-prefix=P9BE -implicit-check-not frsp 5; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 6; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 7; RUN: -check-prefix=P9LE -implicit-check-not frsp 8; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 9; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 10; RUN: -check-prefix=P8BE -implicit-check-not frsp 11; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ 12; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ 13; RUN: -check-prefix=P8LE -implicit-check-not frsp 14 15; This test case comes from the following C test case (included as it may be 16; slightly more readable than the LLVM IR. 17 18;/* This test case provides various ways of building vectors to ensure we 19; produce optimal code for all cases. The cases are (for each type): 20; - All zeros 21; - All ones - split to build-vector-allones.ll 22; - Splat of a constant 23; - From different values already in registers 24; - From different constants 25; - From different values in memory 26; - Splat of a value in register 27; - Splat of a value in memory 28; - Inserting element into existing vector 29; - Inserting element from existing vector into existing vector 30; 31; With conversions (float <-> int) 32; - Splat of a constant 33; - From different values already in registers 34; - From different constants 35; - From different values in memory 36; - Splat of a value in register 37; - Splat of a value in memory 38; - Inserting element into existing vector 39; - Inserting element from existing vector into existing vector 40;*/ 41; 42;/*=================================== int ===================================*/ 43;// P8: xxlxor // 44;// P9: xxlxor // 45;vector int allZeroi() { // 46; return (vector int)0; // 47;} // 48;// P8: vspltisb -1 // 49;// P9: xxspltisb 255 // 50;vector int spltConst1i() { // 51; return (vector int)1; // 52;} // 53;// P8: vspltisw -15; vsrw // 54;// P9: vspltisw -15; vsrw // 55;vector int spltConst16ki() { // 56; return (vector int)((1<<15) - 1); // 57;} // 58;// P8: vspltisw -16; vsrw // 59;// P9: vspltisw -16; vsrw // 60;vector int spltConst32ki() { // 61; return (vector int)((1<<16) - 1); // 62;} // 63;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow // 64;// P9: 2 x mtvsrdd, vmrgow // 65;vector int fromRegsi(int a, int b, int c, int d) { // 66; return (vector int){ a, b, c, d }; // 67;} // 68;// P8: lxvd2x, xxswapd // 69;// P9: lxvx (or even lxv) // 70;vector int fromDiffConstsi() { // 71; return (vector int) { 242, -113, 889, 19 }; // 72;} // 73;// P8: lxvd2x, xxswapd // 74;// P9: lxvx // 75;vector int fromDiffMemConsAi(int *arr) { // 76; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; // 77;} // 78;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 79;// P9: 2 x lxvx, vperm // 80;vector int fromDiffMemConsDi(int *arr) { // 81; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; // 82;} // 83;// P8: sldi 2, lxvd2x, xxswapd // 84;// P9: sldi 2, lxvx // 85;vector int fromDiffMemVarAi(int *arr, int elem) { // 86; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 87;} // 88;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 89;// P9: sldi 2, 2 x lxvx, vperm // 90;vector int fromDiffMemVarDi(int *arr, int elem) { // 91; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 92;} // 93;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 94;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 95;vector int fromRandMemConsi(int *arr) { // 96; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; // 97;} // 98;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 99;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 100;vector int fromRandMemVari(int *arr, int elem) { // 101; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };// 102;} // 103;// P8: mtvsrwz, xxspltw // 104;// P9: mtvsrws // 105;vector int spltRegVali(int val) { // 106; return (vector int) val; // 107;} // 108;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 109;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 110;vector int spltMemVali(int *ptr) { // 111; return (vector int)*ptr; // 112;} // 113;// P8: vspltisw // 114;// P9: vspltisw // 115;vector int spltCnstConvftoi() { // 116; return (vector int) 4.74f; // 117;} // 118;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 119;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 120;vector int fromRegsConvftoi(float a, float b, float c, float d) { // 121; return (vector int) { a, b, c, d }; // 122;} // 123;// P8: lxvd2x, xxswapd // 124;// P9: lxvx (even lxv) // 125;vector int fromDiffConstsConvftoi() { // 126; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; // 127;} // 128;// P8: lxvd2x, xxswapd, xvcvspsxws // 129;// P9: lxvx, xvcvspsxws // 130;vector int fromDiffMemConsAConvftoi(ptr ptr) { // 131; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 132;} // 133;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws // 134;// P9: 2 x lxvx, vperm, xvcvspsxws // 135;vector int fromDiffMemConsDConvftoi(ptr ptr) { // 136; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 137;} // 138;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 139;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 140;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 141;// sldi 2, load, xvcvspuxws // 142;vector int fromDiffMemVarAConvftoi(ptr arr, int elem) { // 143; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 144;} // 145;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 146;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 147;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 148;// sldi 2, 2 x load, vperm, xvcvspuxws // 149;vector int fromDiffMemVarDConvftoi(ptr arr, int elem) { // 150; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 151;} // 152;// P8: xscvdpsxws, xxspltw // 153;// P9: xscvdpsxws, xxspltw // 154;vector int spltRegValConvftoi(float val) { // 155; return (vector int) val; // 156;} // 157;// P8: lxsspx, xscvdpsxws, xxspltw // 158;// P9: lxvwsx, xvcvspsxws // 159;vector int spltMemValConvftoi(ptr ptr) { // 160; return (vector int)*ptr; // 161;} // 162;// P8: vspltisw // 163;// P9: vspltisw // 164;vector int spltCnstConvdtoi() { // 165; return (vector int) 4.74; // 166;} // 167;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 168;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 169;vector int fromRegsConvdtoi(double a, double b, double c, double d) { // 170; return (vector int) { a, b, c, d }; // 171;} // 172;// P8: lxvd2x, xxswapd // 173;// P9: lxvx (even lxv) // 174;vector int fromDiffConstsConvdtoi() { // 175; return (vector int) { 24.46, 234., 988.19, 422.39 }; // 176;} // 177;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 178;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew // 179;vector int fromDiffMemConsAConvdtoi(ptr ptr) { // 180; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 181;} // 182;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 183;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 184;vector int fromDiffMemConsDConvdtoi(ptr ptr) { // 185; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 186;} // 187;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 188;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 189;vector int fromDiffMemVarAConvdtoi(ptr arr, int elem) { // 190; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; // 191;} // 192;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 193;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew // 194;vector int fromDiffMemVarDConvdtoi(ptr arr, int elem) { // 195; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; // 196;} // 197;// P8: xscvdpsxws, xxspltw // 198;// P9: xscvdpsxws, xxspltw // 199;vector int spltRegValConvdtoi(double val) { // 200; return (vector int) val; // 201;} // 202;// P8: lxsdx, xscvdpsxws, xxspltw // 203;// P9: lxssp, xscvdpsxws, xxspltw // 204;vector int spltMemValConvdtoi(ptr ptr) { // 205; return (vector int)*ptr; // 206;} // 207;/*=================================== int ===================================*/ 208;/*=============================== unsigned int ==============================*/ 209;// P8: xxlxor // 210;// P9: xxlxor // 211;vector unsigned int allZeroui() { // 212; return (vector unsigned int)0; // 213;} // 214;// P8: vspltisb -1 // 215;// P9: xxspltisb 255 // 216;vector unsigned int spltConst1ui() { // 217; return (vector unsigned int)1; // 218;} // 219;// P8: vspltisw -15; vsrw // 220;// P9: vspltisw -15; vsrw // 221;vector unsigned int spltConst16kui() { // 222; return (vector unsigned int)((1<<15) - 1); // 223;} // 224;// P8: vspltisw -16; vsrw // 225;// P9: vspltisw -16; vsrw // 226;vector unsigned int spltConst32kui() { // 227; return (vector unsigned int)((1<<16) - 1); // 228;} // 229;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 230;// P9: 2 x mtvsrdd, vmrgow // 231;vector unsigned int fromRegsui(unsigned int a, unsigned int b, // 232; unsigned int c, unsigned int d) { // 233; return (vector unsigned int){ a, b, c, d }; // 234;} // 235;// P8: lxvd2x, xxswapd // 236;// P9: lxvx (or even lxv) // 237;vector unsigned int fromDiffConstsui() { // 238; return (vector unsigned int) { 242, -113, 889, 19 }; // 239;} // 240;// P8: lxvd2x, xxswapd // 241;// P9: lxvx // 242;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { // 243; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; // 244;} // 245;// P8: 2 x lxvd2x, 2 x xxswapd, vperm // 246;// P9: 2 x lxvx, vperm // 247;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { // 248; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; // 249;} // 250;// P8: sldi 2, lxvd2x, xxswapd // 251;// P9: sldi 2, lxvx // 252;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { // 253; return (vector unsigned int) { arr[elem], arr[elem+1], // 254; arr[elem+2], arr[elem+3] }; // 255;} // 256;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm // 257;// P9: sldi 2, 2 x lxvx, vperm // 258;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { // 259; return (vector unsigned int) { arr[elem], arr[elem-1], // 260; arr[elem-2], arr[elem-3] }; // 261;} // 262;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 263;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow // 264;vector unsigned int fromRandMemConsui(unsigned int *arr) { // 265; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; // 266;} // 267;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow // 268;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow // 269;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { // 270; return (vector unsigned int) { arr[elem+4], arr[elem+1], // 271; arr[elem+2], arr[elem+8] }; // 272;} // 273;// P8: mtvsrwz, xxspltw // 274;// P9: mtvsrws // 275;vector unsigned int spltRegValui(unsigned int val) { // 276; return (vector unsigned int) val; // 277;} // 278;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 279;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw // 280;vector unsigned int spltMemValui(unsigned int *ptr) { // 281; return (vector unsigned int)*ptr; // 282;} // 283;// P8: vspltisw // 284;// P9: vspltisw // 285;vector unsigned int spltCnstConvftoui() { // 286; return (vector unsigned int) 4.74f; // 287;} // 288;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 289;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 290;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { // 291; return (vector unsigned int) { a, b, c, d }; // 292;} // 293;// P8: lxvd2x, xxswapd // 294;// P9: lxvx (even lxv) // 295;vector unsigned int fromDiffConstsConvftoui() { // 296; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; // 297;} // 298;// P8: lxvd2x, xxswapd, xvcvspuxws // 299;// P9: lxvx, xvcvspuxws // 300;vector unsigned int fromDiffMemConsAConvftoui(ptr ptr) { // 301; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 302;} // 303;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws // 304;// P9: 2 x lxvx, vperm, xvcvspuxws // 305;vector unsigned int fromDiffMemConsDConvftoui(ptr ptr) { // 306; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 307;} // 308;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 309;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 310;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 311;// sldi 2, load, xvcvspuxws // 312;vector unsigned int fromDiffMemVarAConvftoui(ptr arr, int elem) { // 313; return (vector unsigned int) { arr[elem], arr[elem+1], // 314; arr[elem+2], arr[elem+3] }; // 315;} // 316;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 317;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 318;// Note: if the consecutive loads learns to handle pre-inc, this can be: // 319;// sldi 2, 2 x load, vperm, xvcvspuxws // 320;vector unsigned int fromDiffMemVarDConvftoui(ptr arr, int elem) { // 321; return (vector unsigned int) { arr[elem], arr[elem-1], // 322; arr[elem-2], arr[elem-3] }; // 323;} // 324;// P8: xscvdpuxws, xxspltw // 325;// P9: xscvdpuxws, xxspltw // 326;vector unsigned int spltRegValConvftoui(float val) { // 327; return (vector unsigned int) val; // 328;} // 329;// P8: lxsspx, xscvdpuxws, xxspltw // 330;// P9: lxvwsx, xvcvspuxws // 331;vector unsigned int spltMemValConvftoui(ptr ptr) { // 332; return (vector unsigned int)*ptr; // 333;} // 334;// P8: vspltisw // 335;// P9: vspltisw // 336;vector unsigned int spltCnstConvdtoui() { // 337; return (vector unsigned int) 4.74; // 338;} // 339;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 340;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 341;vector unsigned int fromRegsConvdtoui(double a, double b, // 342; double c, double d) { // 343; return (vector unsigned int) { a, b, c, d }; // 344;} // 345;// P8: lxvd2x, xxswapd // 346;// P9: lxvx (even lxv) // 347;vector unsigned int fromDiffConstsConvdtoui() { // 348; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; // 349;} // 350;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 351;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew // 352;vector unsigned int fromDiffMemConsAConvdtoui(ptr ptr) { // 353; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; // 354;} // 355;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 356;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 357;vector unsigned int fromDiffMemConsDConvdtoui(ptr ptr) { // 358; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; // 359;} // 360;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 361;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 362;vector unsigned int fromDiffMemVarAConvdtoui(ptr arr, int elem) { // 363; return (vector unsigned int) { arr[elem], arr[elem+1], // 364; arr[elem+2], arr[elem+3] }; // 365;} // 366;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 367;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew // 368;vector unsigned int fromDiffMemVarDConvdtoui(ptr arr, int elem) { // 369; return (vector unsigned int) { arr[elem], arr[elem-1], // 370; arr[elem-2], arr[elem-3] }; // 371;} // 372;// P8: xscvdpuxws, xxspltw // 373;// P9: xscvdpuxws, xxspltw // 374;vector unsigned int spltRegValConvdtoui(double val) { // 375; return (vector unsigned int) val; // 376;} // 377;// P8: lxsspx, xscvdpuxws, xxspltw // 378;// P9: lfd, xscvdpuxws, xxspltw // 379;vector unsigned int spltMemValConvdtoui(ptr ptr) { // 380; return (vector unsigned int)*ptr; // 381;} // 382;/*=============================== unsigned int ==============================*/ 383;/*=============================== long long =================================*/ 384;// P8: xxlxor // 385;// P9: xxlxor // 386;vector long long allZeroll() { // 387; return (vector long long)0; // 388;} // 389;// P8: vspltisb -1 // 390;// P9: xxspltisb 255 // 391;vector long long spltConst1ll() { // 392; return (vector long long)1; // 393;} // 394;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 395;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 396;vector long long spltConst16kll() { // 397; return (vector long long)((1<<15) - 1); // 398;} // 399;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 400;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 401;vector long long spltConst32kll() { // 402; return (vector long long)((1<<16) - 1); // 403;} // 404;// P8: 2 x mtvsrd, xxmrghd // 405;// P9: mtvsrdd // 406;vector long long fromRegsll(long long a, long long b) { // 407; return (vector long long){ a, b }; // 408;} // 409;// P8: lxvd2x, xxswapd // 410;// P9: lxvx (or even lxv) // 411;vector long long fromDiffConstsll() { // 412; return (vector long long) { 242, -113 }; // 413;} // 414;// P8: lxvd2x, xxswapd // 415;// P9: lxvx // 416;vector long long fromDiffMemConsAll(long long *arr) { // 417; return (vector long long) { arr[0], arr[1] }; // 418;} // 419;// P8: lxvd2x // 420;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 421;vector long long fromDiffMemConsDll(long long *arr) { // 422; return (vector long long) { arr[3], arr[2] }; // 423;} // 424;// P8: sldi 3, lxvd2x, xxswapd // 425;// P9: sldi 3, lxvx // 426;vector long long fromDiffMemVarAll(long long *arr, int elem) { // 427; return (vector long long) { arr[elem], arr[elem+1] }; // 428;} // 429;// P8: sldi 3, lxvd2x // 430;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 431;vector long long fromDiffMemVarDll(long long *arr, int elem) { // 432; return (vector long long) { arr[elem], arr[elem-1] }; // 433;} // 434;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 435;// P9: 2 x ld, mtvsrdd // 436;vector long long fromRandMemConsll(long long *arr) { // 437; return (vector long long) { arr[4], arr[18] }; // 438;} // 439;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 440;// P9: sldi 3, add, 2 x ld, mtvsrdd // 441;vector long long fromRandMemVarll(long long *arr, int elem) { // 442; return (vector long long) { arr[elem+4], arr[elem+1] }; // 443;} // 444;// P8: mtvsrd, xxspltd // 445;// P9: mtvsrdd // 446;vector long long spltRegValll(long long val) { // 447; return (vector long long) val; // 448;} // 449;// P8: lxvdsx // 450;// P9: lxvdsx // 451;vector long long spltMemValll(long long *ptr) { // 452; return (vector long long)*ptr; // 453;} // 454;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 455;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 456;vector long long spltCnstConvftoll() { // 457; return (vector long long) 4.74f; // 458;} // 459;// P8: xxmrghd, xvcvdpsxds // 460;// P9: xxmrghd, xvcvdpsxds // 461;vector long long fromRegsConvftoll(float a, float b) { // 462; return (vector long long) { a, b }; // 463;} // 464;// P8: lxvd2x, xxswapd // 465;// P9: lxvx (even lxv) // 466;vector long long fromDiffConstsConvftoll() { // 467; return (vector long long) { 24.46f, 234.f }; // 468;} // 469;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 470;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 471;vector long long fromDiffMemConsAConvftoll(ptr ptr) { // 472; return (vector long long) { ptr[0], ptr[1] }; // 473;} // 474;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds // 475;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds // 476;vector long long fromDiffMemConsDConvftoll(ptr ptr) { // 477; return (vector long long) { ptr[3], ptr[2] }; // 478;} // 479;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 480;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 481;vector long long fromDiffMemVarAConvftoll(ptr arr, int elem) { // 482; return (vector long long) { arr[elem], arr[elem+1] }; // 483;} // 484;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds // 485;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds // 486;vector long long fromDiffMemVarDConvftoll(ptr arr, int elem) { // 487; return (vector long long) { arr[elem], arr[elem-1] }; // 488;} // 489;// P8: xscvdpsxds, xxspltd // 490;// P9: xscvdpsxds, xxspltd // 491;vector long long spltRegValConvftoll(float val) { // 492; return (vector long long) val; // 493;} // 494;// P8: lxsspx, xscvdpsxds, xxspltd // 495;// P9: lfs, xscvdpsxds, xxspltd // 496;vector long long spltMemValConvftoll(ptr ptr) { // 497; return (vector long long)*ptr; // 498;} // 499;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 500;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 501;vector long long spltCnstConvdtoll() { // 502; return (vector long long) 4.74; // 503;} // 504;// P8: xxmrghd, xvcvdpsxds // 505;// P9: xxmrghd, xvcvdpsxds // 506;vector long long fromRegsConvdtoll(double a, double b) { // 507; return (vector long long) { a, b }; // 508;} // 509;// P8: lxvd2x, xxswapd // 510;// P9: lxvx (even lxv) // 511;vector long long fromDiffConstsConvdtoll() { // 512; return (vector long long) { 24.46, 234. }; // 513;} // 514;// P8: lxvd2x, xxswapd, xvcvdpsxds // 515;// P9: lxvx, xvcvdpsxds // 516;vector long long fromDiffMemConsAConvdtoll(ptr ptr) { // 517; return (vector long long) { ptr[0], ptr[1] }; // 518;} // 519;// P8: lxvd2x, xvcvdpsxds // 520;// P9: lxvx, xxswapd, xvcvdpsxds // 521;vector long long fromDiffMemConsDConvdtoll(ptr ptr) { // 522; return (vector long long) { ptr[3], ptr[2] }; // 523;} // 524;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds // 525;// P9: sldi 3, lxvx, xvcvdpsxds // 526;vector long long fromDiffMemVarAConvdtoll(ptr arr, int elem) { // 527; return (vector long long) { arr[elem], arr[elem+1] }; // 528;} // 529;// P8: sldi 3, lxvd2x, xvcvdpsxds // 530;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds // 531;vector long long fromDiffMemVarDConvdtoll(ptr arr, int elem) { // 532; return (vector long long) { arr[elem], arr[elem-1] }; // 533;} // 534;// P8: xscvdpsxds, xxspltd // 535;// P9: xscvdpsxds, xxspltd // 536;vector long long spltRegValConvdtoll(double val) { // 537; return (vector long long) val; // 538;} // 539;// P8: lxvdsx, xvcvdpsxds // 540;// P9: lxvdsx, xvcvdpsxds // 541;vector long long spltMemValConvdtoll(ptr ptr) { // 542; return (vector long long)*ptr; // 543;} // 544;/*=============================== long long =================================*/ 545;/*========================== unsigned long long =============================*/ 546;// P8: xxlxor // 547;// P9: xxlxor // 548;vector unsigned long long allZeroull() { // 549; return (vector unsigned long long)0; // 550;} // 551;// P8: vspltisb -1 // 552;// P9: xxspltisb 255 // 553;vector unsigned long long spltConst1ull() { // 554; return (vector unsigned long long)1; // 555;} // 556;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 557;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 558;vector unsigned long long spltConst16kull() { // 559; return (vector unsigned long long)((1<<15) - 1); // 560;} // 561;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 562;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) // 563;vector unsigned long long spltConst32kull() { // 564; return (vector unsigned long long)((1<<16) - 1); // 565;} // 566;// P8: 2 x mtvsrd, xxmrghd // 567;// P9: mtvsrdd // 568;vector unsigned long long fromRegsull(unsigned long long a, // 569; unsigned long long b) { // 570; return (vector unsigned long long){ a, b }; // 571;} // 572;// P8: lxvd2x, xxswapd // 573;// P9: lxvx (or even lxv) // 574;vector unsigned long long fromDiffConstsull() { // 575; return (vector unsigned long long) { 242, -113 }; // 576;} // 577;// P8: lxvd2x, xxswapd // 578;// P9: lxvx // 579;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { // 580; return (vector unsigned long long) { arr[0], arr[1] }; // 581;} // 582;// P8: lxvd2x // 583;// P9: lxvx, xxswapd (maybe just use lxvd2x) // 584;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { // 585; return (vector unsigned long long) { arr[3], arr[2] }; // 586;} // 587;// P8: sldi 3, lxvd2x, xxswapd // 588;// P9: sldi 3, lxvx // 589;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, // 590; int elem) { // 591; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 592;} // 593;// P8: sldi 3, lxvd2x // 594;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) // 595;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, // 596; int elem) { // 597; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 598;} // 599;// P8: 2 x ld, 2 x mtvsrd, xxmrghd // 600;// P9: 2 x ld, mtvsrdd // 601;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { // 602; return (vector unsigned long long) { arr[4], arr[18] }; // 603;} // 604;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd // 605;// P9: sldi 3, add, 2 x ld, mtvsrdd // 606;vector unsigned long long fromRandMemVarull(unsigned long long *arr, // 607; int elem) { // 608; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; // 609;} // 610;// P8: mtvsrd, xxspltd // 611;// P9: mtvsrdd // 612;vector unsigned long long spltRegValull(unsigned long long val) { // 613; return (vector unsigned long long) val; // 614;} // 615;// P8: lxvdsx // 616;// P9: lxvdsx // 617;vector unsigned long long spltMemValull(unsigned long long *ptr) { // 618; return (vector unsigned long long)*ptr; // 619;} // 620;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 621;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 622;vector unsigned long long spltCnstConvftoull() { // 623; return (vector unsigned long long) 4.74f; // 624;} // 625;// P8: xxmrghd, xvcvdpuxds // 626;// P9: xxmrghd, xvcvdpuxds // 627;vector unsigned long long fromRegsConvftoull(float a, float b) { // 628; return (vector unsigned long long) { a, b }; // 629;} // 630;// P8: lxvd2x, xxswapd // 631;// P9: lxvx (even lxv) // 632;vector unsigned long long fromDiffConstsConvftoull() { // 633; return (vector unsigned long long) { 24.46f, 234.f }; // 634;} // 635;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 636;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 637;vector unsigned long long fromDiffMemConsAConvftoull(ptr ptr) { // 638; return (vector unsigned long long) { ptr[0], ptr[1] }; // 639;} // 640;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds // 641;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds // 642;vector unsigned long long fromDiffMemConsDConvftoull(ptr ptr) { // 643; return (vector unsigned long long) { ptr[3], ptr[2] }; // 644;} // 645;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 646;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 647;vector unsigned long long fromDiffMemVarAConvftoull(ptr arr, int elem) { // 648; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 649;} // 650;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds // 651;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds // 652;vector unsigned long long fromDiffMemVarDConvftoull(ptr arr, int elem) { // 653; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 654;} // 655;// P8: xscvdpuxds, xxspltd // 656;// P9: xscvdpuxds, xxspltd // 657;vector unsigned long long spltRegValConvftoull(float val) { // 658; return (vector unsigned long long) val; // 659;} // 660;// P8: lxsspx, xscvdpuxds, xxspltd // 661;// P9: lfs, xscvdpuxds, xxspltd // 662;vector unsigned long long spltMemValConvftoull(ptr ptr) { // 663; return (vector unsigned long long)*ptr; // 664;} // 665;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 666;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) // 667;vector unsigned long long spltCnstConvdtoull() { // 668; return (vector unsigned long long) 4.74; // 669;} // 670;// P8: xxmrghd, xvcvdpuxds // 671;// P9: xxmrghd, xvcvdpuxds // 672;vector unsigned long long fromRegsConvdtoull(double a, double b) { // 673; return (vector unsigned long long) { a, b }; // 674;} // 675;// P8: lxvd2x, xxswapd // 676;// P9: lxvx (even lxv) // 677;vector unsigned long long fromDiffConstsConvdtoull() { // 678; return (vector unsigned long long) { 24.46, 234. }; // 679;} // 680;// P8: lxvd2x, xxswapd, xvcvdpuxds // 681;// P9: lxvx, xvcvdpuxds // 682;vector unsigned long long fromDiffMemConsAConvdtoull(ptr ptr) { // 683; return (vector unsigned long long) { ptr[0], ptr[1] }; // 684;} // 685;// P8: lxvd2x, xvcvdpuxds // 686;// P9: lxvx, xxswapd, xvcvdpuxds // 687;vector unsigned long long fromDiffMemConsDConvdtoull(ptr ptr) { // 688; return (vector unsigned long long) { ptr[3], ptr[2] }; // 689;} // 690;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds // 691;// P9: sldi 3, lxvx, xvcvdpuxds // 692;vector unsigned long long fromDiffMemVarAConvdtoull(ptr arr, int elem) { // 693; return (vector unsigned long long) { arr[elem], arr[elem+1] }; // 694;} // 695;// P8: sldi 3, lxvd2x, xvcvdpuxds // 696;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds // 697;vector unsigned long long fromDiffMemVarDConvdtoull(ptr arr, int elem) { // 698; return (vector unsigned long long) { arr[elem], arr[elem-1] }; // 699;} // 700;// P8: xscvdpuxds, xxspltd // 701;// P9: xscvdpuxds, xxspltd // 702;vector unsigned long long spltRegValConvdtoull(double val) { // 703; return (vector unsigned long long) val; // 704;} // 705;// P8: lxvdsx, xvcvdpuxds // 706;// P9: lxvdsx, xvcvdpuxds // 707;vector unsigned long long spltMemValConvdtoull(ptr ptr) { // 708; return (vector unsigned long long)*ptr; // 709;} // 710;/*========================== unsigned long long ==============================*/ 711 712define <4 x i32> @allZeroi() { 713; P9BE-LABEL: allZeroi: 714; P9BE: # %bb.0: # %entry 715; P9BE-NEXT: xxlxor v2, v2, v2 716; P9BE-NEXT: blr 717; 718; P9LE-LABEL: allZeroi: 719; P9LE: # %bb.0: # %entry 720; P9LE-NEXT: xxlxor v2, v2, v2 721; P9LE-NEXT: blr 722; 723; P8BE-LABEL: allZeroi: 724; P8BE: # %bb.0: # %entry 725; P8BE-NEXT: xxlxor v2, v2, v2 726; P8BE-NEXT: blr 727; 728; P8LE-LABEL: allZeroi: 729; P8LE: # %bb.0: # %entry 730; P8LE-NEXT: xxlxor v2, v2, v2 731; P8LE-NEXT: blr 732entry: 733 ret <4 x i32> zeroinitializer 734} 735 736define <4 x i32> @spltConst1i() { 737; P9BE-LABEL: spltConst1i: 738; P9BE: # %bb.0: # %entry 739; P9BE-NEXT: vspltisw v2, 1 740; P9BE-NEXT: blr 741; 742; P9LE-LABEL: spltConst1i: 743; P9LE: # %bb.0: # %entry 744; P9LE-NEXT: vspltisw v2, 1 745; P9LE-NEXT: blr 746; 747; P8BE-LABEL: spltConst1i: 748; P8BE: # %bb.0: # %entry 749; P8BE-NEXT: vspltisw v2, 1 750; P8BE-NEXT: blr 751; 752; P8LE-LABEL: spltConst1i: 753; P8LE: # %bb.0: # %entry 754; P8LE-NEXT: vspltisw v2, 1 755; P8LE-NEXT: blr 756entry: 757 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 758} 759 760define <4 x i32> @spltConst16ki() { 761; P9BE-LABEL: spltConst16ki: 762; P9BE: # %bb.0: # %entry 763; P9BE-NEXT: vspltisw v2, -15 764; P9BE-NEXT: vsrw v2, v2, v2 765; P9BE-NEXT: blr 766; 767; P9LE-LABEL: spltConst16ki: 768; P9LE: # %bb.0: # %entry 769; P9LE-NEXT: vspltisw v2, -15 770; P9LE-NEXT: vsrw v2, v2, v2 771; P9LE-NEXT: blr 772; 773; P8BE-LABEL: spltConst16ki: 774; P8BE: # %bb.0: # %entry 775; P8BE-NEXT: vspltisw v2, -15 776; P8BE-NEXT: vsrw v2, v2, v2 777; P8BE-NEXT: blr 778; 779; P8LE-LABEL: spltConst16ki: 780; P8LE: # %bb.0: # %entry 781; P8LE-NEXT: vspltisw v2, -15 782; P8LE-NEXT: vsrw v2, v2, v2 783; P8LE-NEXT: blr 784entry: 785 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 786} 787 788define <4 x i32> @spltConst32ki() { 789; P9BE-LABEL: spltConst32ki: 790; P9BE: # %bb.0: # %entry 791; P9BE-NEXT: vspltisw v2, -16 792; P9BE-NEXT: vsrw v2, v2, v2 793; P9BE-NEXT: blr 794; 795; P9LE-LABEL: spltConst32ki: 796; P9LE: # %bb.0: # %entry 797; P9LE-NEXT: vspltisw v2, -16 798; P9LE-NEXT: vsrw v2, v2, v2 799; P9LE-NEXT: blr 800; 801; P8BE-LABEL: spltConst32ki: 802; P8BE: # %bb.0: # %entry 803; P8BE-NEXT: vspltisw v2, -16 804; P8BE-NEXT: vsrw v2, v2, v2 805; P8BE-NEXT: blr 806; 807; P8LE-LABEL: spltConst32ki: 808; P8LE: # %bb.0: # %entry 809; P8LE-NEXT: vspltisw v2, -16 810; P8LE-NEXT: vsrw v2, v2, v2 811; P8LE-NEXT: blr 812entry: 813 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 814} 815 816define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) { 817; P9BE-LABEL: fromRegsi: 818; P9BE: # %bb.0: # %entry 819; P9BE-NEXT: rldimi r6, r5, 32, 0 820; P9BE-NEXT: rldimi r4, r3, 32, 0 821; P9BE-NEXT: mtvsrdd v2, r4, r6 822; P9BE-NEXT: blr 823; 824; P9LE-LABEL: fromRegsi: 825; P9LE: # %bb.0: # %entry 826; P9LE-NEXT: rldimi r3, r4, 32, 0 827; P9LE-NEXT: rldimi r5, r6, 32, 0 828; P9LE-NEXT: mtvsrdd v2, r5, r3 829; P9LE-NEXT: blr 830; 831; P8BE-LABEL: fromRegsi: 832; P8BE: # %bb.0: # %entry 833; P8BE-NEXT: rldimi r6, r5, 32, 0 834; P8BE-NEXT: rldimi r4, r3, 32, 0 835; P8BE-NEXT: mtfprd f0, r6 836; P8BE-NEXT: mtfprd f1, r4 837; P8BE-NEXT: xxmrghd v2, vs1, vs0 838; P8BE-NEXT: blr 839; 840; P8LE-LABEL: fromRegsi: 841; P8LE: # %bb.0: # %entry 842; P8LE-NEXT: rldimi r3, r4, 32, 0 843; P8LE-NEXT: rldimi r5, r6, 32, 0 844; P8LE-NEXT: mtfprd f0, r3 845; P8LE-NEXT: mtfprd f1, r5 846; P8LE-NEXT: xxmrghd v2, vs1, vs0 847; P8LE-NEXT: blr 848entry: 849 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 850 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 851 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 852 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 853 ret <4 x i32> %vecinit3 854} 855 856define <4 x i32> @fromDiffConstsi() { 857; P9BE-LABEL: fromDiffConstsi: 858; P9BE: # %bb.0: # %entry 859; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 860; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 861; P9BE-NEXT: lxv v2, 0(r3) 862; P9BE-NEXT: blr 863; 864; P9LE-LABEL: fromDiffConstsi: 865; P9LE: # %bb.0: # %entry 866; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 867; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 868; P9LE-NEXT: lxv v2, 0(r3) 869; P9LE-NEXT: blr 870; 871; P8BE-LABEL: fromDiffConstsi: 872; P8BE: # %bb.0: # %entry 873; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 874; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l 875; P8BE-NEXT: lxvw4x v2, 0, r3 876; P8BE-NEXT: blr 877; 878; P8LE-LABEL: fromDiffConstsi: 879; P8LE: # %bb.0: # %entry 880; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha 881; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l 882; P8LE-NEXT: lxvd2x vs0, 0, r3 883; P8LE-NEXT: xxswapd v2, vs0 884; P8LE-NEXT: blr 885entry: 886 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 887} 888 889define <4 x i32> @fromDiffMemConsAi(ptr nocapture readonly %arr) { 890; P9BE-LABEL: fromDiffMemConsAi: 891; P9BE: # %bb.0: # %entry 892; P9BE-NEXT: lxv v2, 0(r3) 893; P9BE-NEXT: blr 894; 895; P9LE-LABEL: fromDiffMemConsAi: 896; P9LE: # %bb.0: # %entry 897; P9LE-NEXT: lxv v2, 0(r3) 898; P9LE-NEXT: blr 899; 900; P8BE-LABEL: fromDiffMemConsAi: 901; P8BE: # %bb.0: # %entry 902; P8BE-NEXT: lxvw4x v2, 0, r3 903; P8BE-NEXT: blr 904; 905; P8LE-LABEL: fromDiffMemConsAi: 906; P8LE: # %bb.0: # %entry 907; P8LE-NEXT: lxvd2x vs0, 0, r3 908; P8LE-NEXT: xxswapd v2, vs0 909; P8LE-NEXT: blr 910entry: 911 %0 = load i32, ptr %arr, align 4 912 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 913 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 1 914 %1 = load i32, ptr %arrayidx1, align 4 915 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 916 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2 917 %2 = load i32, ptr %arrayidx3, align 4 918 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 919 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 3 920 %3 = load i32, ptr %arrayidx5, align 4 921 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 922 ret <4 x i32> %vecinit6 923} 924 925define <4 x i32> @fromDiffMemConsDi(ptr nocapture readonly %arr) { 926; P9BE-LABEL: fromDiffMemConsDi: 927; P9BE: # %bb.0: # %entry 928; P9BE-NEXT: lxv v2, 0(r3) 929; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha 930; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l 931; P9BE-NEXT: lxv vs0, 0(r3) 932; P9BE-NEXT: xxperm v2, v2, vs0 933; P9BE-NEXT: blr 934; 935; P9LE-LABEL: fromDiffMemConsDi: 936; P9LE: # %bb.0: # %entry 937; P9LE-NEXT: lxvw4x v2, 0, r3 938; P9LE-NEXT: blr 939; 940; P8BE-LABEL: fromDiffMemConsDi: 941; P8BE: # %bb.0: # %entry 942; P8BE-NEXT: lxvw4x v2, 0, r3 943; P8BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha 944; P8BE-NEXT: addi r3, r3, .LCPI7_0@toc@l 945; P8BE-NEXT: lxvw4x v3, 0, r3 946; P8BE-NEXT: vperm v2, v2, v2, v3 947; P8BE-NEXT: blr 948; 949; P8LE-LABEL: fromDiffMemConsDi: 950; P8LE: # %bb.0: # %entry 951; P8LE-NEXT: lxvd2x vs0, 0, r3 952; P8LE-NEXT: addis r3, r2, .LCPI7_0@toc@ha 953; P8LE-NEXT: addi r3, r3, .LCPI7_0@toc@l 954; P8LE-NEXT: xxswapd v2, vs0 955; P8LE-NEXT: lxvd2x vs0, 0, r3 956; P8LE-NEXT: xxswapd v3, vs0 957; P8LE-NEXT: vperm v2, v2, v2, v3 958; P8LE-NEXT: blr 959entry: 960 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 3 961 %0 = load i32, ptr %arrayidx, align 4 962 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 963 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 2 964 %1 = load i32, ptr %arrayidx1, align 4 965 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 966 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 1 967 %2 = load i32, ptr %arrayidx3, align 4 968 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 969 %3 = load i32, ptr %arr, align 4 970 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 971 ret <4 x i32> %vecinit6 972} 973 974define <4 x i32> @fromDiffMemVarAi(ptr nocapture readonly %arr, i32 signext %elem) { 975; P9BE-LABEL: fromDiffMemVarAi: 976; P9BE: # %bb.0: # %entry 977; P9BE-NEXT: sldi r4, r4, 2 978; P9BE-NEXT: lxvx v2, r3, r4 979; P9BE-NEXT: blr 980; 981; P9LE-LABEL: fromDiffMemVarAi: 982; P9LE: # %bb.0: # %entry 983; P9LE-NEXT: sldi r4, r4, 2 984; P9LE-NEXT: lxvx v2, r3, r4 985; P9LE-NEXT: blr 986; 987; P8BE-LABEL: fromDiffMemVarAi: 988; P8BE: # %bb.0: # %entry 989; P8BE-NEXT: sldi r4, r4, 2 990; P8BE-NEXT: lxvw4x v2, r3, r4 991; P8BE-NEXT: blr 992; 993; P8LE-LABEL: fromDiffMemVarAi: 994; P8LE: # %bb.0: # %entry 995; P8LE-NEXT: sldi r4, r4, 2 996; P8LE-NEXT: lxvd2x vs0, r3, r4 997; P8LE-NEXT: xxswapd v2, vs0 998; P8LE-NEXT: blr 999entry: 1000 %idxprom = sext i32 %elem to i64 1001 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom 1002 %0 = load i32, ptr %arrayidx, align 4 1003 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1004 %add = add nsw i32 %elem, 1 1005 %idxprom1 = sext i32 %add to i64 1006 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1 1007 %1 = load i32, ptr %arrayidx2, align 4 1008 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1009 %add4 = add nsw i32 %elem, 2 1010 %idxprom5 = sext i32 %add4 to i64 1011 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5 1012 %2 = load i32, ptr %arrayidx6, align 4 1013 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1014 %add8 = add nsw i32 %elem, 3 1015 %idxprom9 = sext i32 %add8 to i64 1016 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9 1017 %3 = load i32, ptr %arrayidx10, align 4 1018 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1019 ret <4 x i32> %vecinit11 1020} 1021 1022define <4 x i32> @fromDiffMemVarDi(ptr nocapture readonly %arr, i32 signext %elem) { 1023; P9BE-LABEL: fromDiffMemVarDi: 1024; P9BE: # %bb.0: # %entry 1025; P9BE-NEXT: sldi r4, r4, 2 1026; P9BE-NEXT: add r3, r3, r4 1027; P9BE-NEXT: li r4, -12 1028; P9BE-NEXT: lxvx v2, r3, r4 1029; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1030; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1031; P9BE-NEXT: lxv vs0, 0(r3) 1032; P9BE-NEXT: xxperm v2, v2, vs0 1033; P9BE-NEXT: blr 1034; 1035; P9LE-LABEL: fromDiffMemVarDi: 1036; P9LE: # %bb.0: # %entry 1037; P9LE-NEXT: sldi r4, r4, 2 1038; P9LE-NEXT: add r3, r3, r4 1039; P9LE-NEXT: li r4, -12 1040; P9LE-NEXT: lxvx v2, r3, r4 1041; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1042; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1043; P9LE-NEXT: lxv vs0, 0(r3) 1044; P9LE-NEXT: xxperm v2, v2, vs0 1045; P9LE-NEXT: blr 1046; 1047; P8BE-LABEL: fromDiffMemVarDi: 1048; P8BE: # %bb.0: # %entry 1049; P8BE-NEXT: sldi r4, r4, 2 1050; P8BE-NEXT: add r3, r3, r4 1051; P8BE-NEXT: addi r3, r3, -12 1052; P8BE-NEXT: lxvw4x v2, 0, r3 1053; P8BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha 1054; P8BE-NEXT: addi r3, r3, .LCPI9_0@toc@l 1055; P8BE-NEXT: lxvw4x v3, 0, r3 1056; P8BE-NEXT: vperm v2, v2, v2, v3 1057; P8BE-NEXT: blr 1058; 1059; P8LE-LABEL: fromDiffMemVarDi: 1060; P8LE: # %bb.0: # %entry 1061; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha 1062; P8LE-NEXT: sldi r4, r4, 2 1063; P8LE-NEXT: addi r5, r5, .LCPI9_0@toc@l 1064; P8LE-NEXT: add r3, r3, r4 1065; P8LE-NEXT: lxvd2x vs0, 0, r5 1066; P8LE-NEXT: addi r3, r3, -12 1067; P8LE-NEXT: lxvd2x v3, 0, r3 1068; P8LE-NEXT: xxswapd v2, vs0 1069; P8LE-NEXT: vperm v2, v3, v3, v2 1070; P8LE-NEXT: blr 1071entry: 1072 %idxprom = sext i32 %elem to i64 1073 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom 1074 %0 = load i32, ptr %arrayidx, align 4 1075 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1076 %sub = add nsw i32 %elem, -1 1077 %idxprom1 = sext i32 %sub to i64 1078 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1 1079 %1 = load i32, ptr %arrayidx2, align 4 1080 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1081 %sub4 = add nsw i32 %elem, -2 1082 %idxprom5 = sext i32 %sub4 to i64 1083 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5 1084 %2 = load i32, ptr %arrayidx6, align 4 1085 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 1086 %sub8 = add nsw i32 %elem, -3 1087 %idxprom9 = sext i32 %sub8 to i64 1088 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9 1089 %3 = load i32, ptr %arrayidx10, align 4 1090 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 1091 ret <4 x i32> %vecinit11 1092} 1093 1094define <4 x i32> @fromRandMemConsi(ptr nocapture readonly %arr) { 1095; P9BE-LABEL: fromRandMemConsi: 1096; P9BE: # %bb.0: # %entry 1097; P9BE-NEXT: lwz r4, 16(r3) 1098; P9BE-NEXT: lwz r5, 72(r3) 1099; P9BE-NEXT: lwz r6, 8(r3) 1100; P9BE-NEXT: lwz r3, 352(r3) 1101; P9BE-NEXT: rldimi r3, r6, 32, 0 1102; P9BE-NEXT: rldimi r5, r4, 32, 0 1103; P9BE-NEXT: mtvsrdd v2, r5, r3 1104; P9BE-NEXT: blr 1105; 1106; P9LE-LABEL: fromRandMemConsi: 1107; P9LE: # %bb.0: # %entry 1108; P9LE-NEXT: lwz r4, 16(r3) 1109; P9LE-NEXT: lwz r5, 72(r3) 1110; P9LE-NEXT: lwz r6, 8(r3) 1111; P9LE-NEXT: lwz r3, 352(r3) 1112; P9LE-NEXT: rldimi r4, r5, 32, 0 1113; P9LE-NEXT: rldimi r6, r3, 32, 0 1114; P9LE-NEXT: mtvsrdd v2, r6, r4 1115; P9LE-NEXT: blr 1116; 1117; P8BE-LABEL: fromRandMemConsi: 1118; P8BE: # %bb.0: # %entry 1119; P8BE-NEXT: lwz r4, 16(r3) 1120; P8BE-NEXT: lwz r5, 72(r3) 1121; P8BE-NEXT: lwz r6, 8(r3) 1122; P8BE-NEXT: lwz r3, 352(r3) 1123; P8BE-NEXT: rldimi r3, r6, 32, 0 1124; P8BE-NEXT: rldimi r5, r4, 32, 0 1125; P8BE-NEXT: mtfprd f0, r3 1126; P8BE-NEXT: mtfprd f1, r5 1127; P8BE-NEXT: xxmrghd v2, vs1, vs0 1128; P8BE-NEXT: blr 1129; 1130; P8LE-LABEL: fromRandMemConsi: 1131; P8LE: # %bb.0: # %entry 1132; P8LE-NEXT: lwz r4, 16(r3) 1133; P8LE-NEXT: lwz r5, 72(r3) 1134; P8LE-NEXT: lwz r6, 8(r3) 1135; P8LE-NEXT: lwz r3, 352(r3) 1136; P8LE-NEXT: rldimi r4, r5, 32, 0 1137; P8LE-NEXT: rldimi r6, r3, 32, 0 1138; P8LE-NEXT: mtfprd f0, r4 1139; P8LE-NEXT: mtfprd f1, r6 1140; P8LE-NEXT: xxmrghd v2, vs1, vs0 1141; P8LE-NEXT: blr 1142entry: 1143 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 4 1144 %0 = load i32, ptr %arrayidx, align 4 1145 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1146 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 18 1147 %1 = load i32, ptr %arrayidx1, align 4 1148 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1149 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2 1150 %2 = load i32, ptr %arrayidx3, align 4 1151 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 1152 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 88 1153 %3 = load i32, ptr %arrayidx5, align 4 1154 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 1155 ret <4 x i32> %vecinit6 1156} 1157 1158define <4 x i32> @fromRandMemVari(ptr nocapture readonly %arr, i32 signext %elem) { 1159; P9BE-LABEL: fromRandMemVari: 1160; P9BE: # %bb.0: # %entry 1161; P9BE-NEXT: sldi r4, r4, 2 1162; P9BE-NEXT: add r3, r3, r4 1163; P9BE-NEXT: lwz r4, 16(r3) 1164; P9BE-NEXT: lwz r5, 4(r3) 1165; P9BE-NEXT: lwz r6, 8(r3) 1166; P9BE-NEXT: lwz r3, 32(r3) 1167; P9BE-NEXT: rldimi r3, r6, 32, 0 1168; P9BE-NEXT: rldimi r5, r4, 32, 0 1169; P9BE-NEXT: mtvsrdd v2, r5, r3 1170; P9BE-NEXT: blr 1171; 1172; P9LE-LABEL: fromRandMemVari: 1173; P9LE: # %bb.0: # %entry 1174; P9LE-NEXT: sldi r4, r4, 2 1175; P9LE-NEXT: add r3, r3, r4 1176; P9LE-NEXT: lwz r4, 16(r3) 1177; P9LE-NEXT: lwz r5, 4(r3) 1178; P9LE-NEXT: lwz r6, 8(r3) 1179; P9LE-NEXT: lwz r3, 32(r3) 1180; P9LE-NEXT: rldimi r4, r5, 32, 0 1181; P9LE-NEXT: rldimi r6, r3, 32, 0 1182; P9LE-NEXT: mtvsrdd v2, r6, r4 1183; P9LE-NEXT: blr 1184; 1185; P8BE-LABEL: fromRandMemVari: 1186; P8BE: # %bb.0: # %entry 1187; P8BE-NEXT: sldi r4, r4, 2 1188; P8BE-NEXT: add r3, r3, r4 1189; P8BE-NEXT: lwz r4, 16(r3) 1190; P8BE-NEXT: lwz r5, 4(r3) 1191; P8BE-NEXT: lwz r6, 8(r3) 1192; P8BE-NEXT: lwz r3, 32(r3) 1193; P8BE-NEXT: rldimi r3, r6, 32, 0 1194; P8BE-NEXT: rldimi r5, r4, 32, 0 1195; P8BE-NEXT: mtfprd f0, r3 1196; P8BE-NEXT: mtfprd f1, r5 1197; P8BE-NEXT: xxmrghd v2, vs1, vs0 1198; P8BE-NEXT: blr 1199; 1200; P8LE-LABEL: fromRandMemVari: 1201; P8LE: # %bb.0: # %entry 1202; P8LE-NEXT: sldi r4, r4, 2 1203; P8LE-NEXT: add r3, r3, r4 1204; P8LE-NEXT: lwz r4, 16(r3) 1205; P8LE-NEXT: lwz r5, 4(r3) 1206; P8LE-NEXT: lwz r6, 8(r3) 1207; P8LE-NEXT: lwz r3, 32(r3) 1208; P8LE-NEXT: rldimi r4, r5, 32, 0 1209; P8LE-NEXT: rldimi r6, r3, 32, 0 1210; P8LE-NEXT: mtfprd f0, r4 1211; P8LE-NEXT: mtfprd f1, r6 1212; P8LE-NEXT: xxmrghd v2, vs1, vs0 1213; P8LE-NEXT: blr 1214entry: 1215 %add = add nsw i32 %elem, 4 1216 %idxprom = sext i32 %add to i64 1217 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom 1218 %0 = load i32, ptr %arrayidx, align 4 1219 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 1220 %add1 = add nsw i32 %elem, 1 1221 %idxprom2 = sext i32 %add1 to i64 1222 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 %idxprom2 1223 %1 = load i32, ptr %arrayidx3, align 4 1224 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 1225 %add5 = add nsw i32 %elem, 2 1226 %idxprom6 = sext i32 %add5 to i64 1227 %arrayidx7 = getelementptr inbounds i32, ptr %arr, i64 %idxprom6 1228 %2 = load i32, ptr %arrayidx7, align 4 1229 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 1230 %add9 = add nsw i32 %elem, 8 1231 %idxprom10 = sext i32 %add9 to i64 1232 %arrayidx11 = getelementptr inbounds i32, ptr %arr, i64 %idxprom10 1233 %3 = load i32, ptr %arrayidx11, align 4 1234 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 1235 ret <4 x i32> %vecinit12 1236} 1237 1238define <4 x i32> @spltRegVali(i32 signext %val) { 1239; P9BE-LABEL: spltRegVali: 1240; P9BE: # %bb.0: # %entry 1241; P9BE-NEXT: mtvsrws v2, r3 1242; P9BE-NEXT: blr 1243; 1244; P9LE-LABEL: spltRegVali: 1245; P9LE: # %bb.0: # %entry 1246; P9LE-NEXT: mtvsrws v2, r3 1247; P9LE-NEXT: blr 1248; 1249; P8BE-LABEL: spltRegVali: 1250; P8BE: # %bb.0: # %entry 1251; P8BE-NEXT: mtfprwz f0, r3 1252; P8BE-NEXT: xxspltw v2, vs0, 1 1253; P8BE-NEXT: blr 1254; 1255; P8LE-LABEL: spltRegVali: 1256; P8LE: # %bb.0: # %entry 1257; P8LE-NEXT: mtfprwz f0, r3 1258; P8LE-NEXT: xxspltw v2, vs0, 1 1259; P8LE-NEXT: blr 1260entry: 1261 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 1262 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1263 ret <4 x i32> %splat.splat 1264} 1265 1266define <4 x i32> @spltMemVali(ptr nocapture readonly %ptr) { 1267; P9BE-LABEL: spltMemVali: 1268; P9BE: # %bb.0: # %entry 1269; P9BE-NEXT: lxvwsx v2, 0, r3 1270; P9BE-NEXT: blr 1271; 1272; P9LE-LABEL: spltMemVali: 1273; P9LE: # %bb.0: # %entry 1274; P9LE-NEXT: lxvwsx v2, 0, r3 1275; P9LE-NEXT: blr 1276; 1277; P8BE-LABEL: spltMemVali: 1278; P8BE: # %bb.0: # %entry 1279; P8BE-NEXT: lfiwzx f0, 0, r3 1280; P8BE-NEXT: xxspltw v2, vs0, 1 1281; P8BE-NEXT: blr 1282; 1283; P8LE-LABEL: spltMemVali: 1284; P8LE: # %bb.0: # %entry 1285; P8LE-NEXT: lfiwzx f0, 0, r3 1286; P8LE-NEXT: xxspltw v2, vs0, 1 1287; P8LE-NEXT: blr 1288entry: 1289 %0 = load i32, ptr %ptr, align 4 1290 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 1291 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1292 ret <4 x i32> %splat.splat 1293} 1294 1295define <4 x i32> @spltCnstConvftoi() { 1296; P9BE-LABEL: spltCnstConvftoi: 1297; P9BE: # %bb.0: # %entry 1298; P9BE-NEXT: vspltisw v2, 4 1299; P9BE-NEXT: blr 1300; 1301; P9LE-LABEL: spltCnstConvftoi: 1302; P9LE: # %bb.0: # %entry 1303; P9LE-NEXT: vspltisw v2, 4 1304; P9LE-NEXT: blr 1305; 1306; P8BE-LABEL: spltCnstConvftoi: 1307; P8BE: # %bb.0: # %entry 1308; P8BE-NEXT: vspltisw v2, 4 1309; P8BE-NEXT: blr 1310; 1311; P8LE-LABEL: spltCnstConvftoi: 1312; P8LE: # %bb.0: # %entry 1313; P8LE-NEXT: vspltisw v2, 4 1314; P8LE-NEXT: blr 1315entry: 1316 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1317} 1318 1319define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) { 1320; P9BE-LABEL: fromRegsConvftoi: 1321; P9BE: # %bb.0: # %entry 1322; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1323; P9BE-NEXT: xvcvdpsxws v2, vs0 1324; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1325; P9BE-NEXT: xvcvdpsxws v3, vs0 1326; P9BE-NEXT: vmrgew v2, v3, v2 1327; P9BE-NEXT: blr 1328; 1329; P9LE-LABEL: fromRegsConvftoi: 1330; P9LE: # %bb.0: # %entry 1331; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1332; P9LE-NEXT: xvcvdpsxws v2, vs0 1333; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1334; P9LE-NEXT: xvcvdpsxws v3, vs0 1335; P9LE-NEXT: vmrgew v2, v3, v2 1336; P9LE-NEXT: blr 1337; 1338; P8BE-LABEL: fromRegsConvftoi: 1339; P8BE: # %bb.0: # %entry 1340; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1341; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1342; P8BE-NEXT: xvcvdpsxws v2, vs0 1343; P8BE-NEXT: xvcvdpsxws v3, vs1 1344; P8BE-NEXT: vmrgew v2, v3, v2 1345; P8BE-NEXT: blr 1346; 1347; P8LE-LABEL: fromRegsConvftoi: 1348; P8LE: # %bb.0: # %entry 1349; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1350; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1351; P8LE-NEXT: xvcvdpsxws v2, vs0 1352; P8LE-NEXT: xvcvdpsxws v3, vs1 1353; P8LE-NEXT: vmrgew v2, v3, v2 1354; P8LE-NEXT: blr 1355entry: 1356 %conv = fptosi float %a to i32 1357 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1358 %conv1 = fptosi float %b to i32 1359 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1360 %conv3 = fptosi float %c to i32 1361 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1362 %conv5 = fptosi float %d to i32 1363 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1364 ret <4 x i32> %vecinit6 1365} 1366 1367define <4 x i32> @fromDiffConstsConvftoi() { 1368; P9BE-LABEL: fromDiffConstsConvftoi: 1369; P9BE: # %bb.0: # %entry 1370; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1371; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1372; P9BE-NEXT: lxv v2, 0(r3) 1373; P9BE-NEXT: blr 1374; 1375; P9LE-LABEL: fromDiffConstsConvftoi: 1376; P9LE: # %bb.0: # %entry 1377; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1378; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1379; P9LE-NEXT: lxv v2, 0(r3) 1380; P9LE-NEXT: blr 1381; 1382; P8BE-LABEL: fromDiffConstsConvftoi: 1383; P8BE: # %bb.0: # %entry 1384; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1385; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1386; P8BE-NEXT: lxvw4x v2, 0, r3 1387; P8BE-NEXT: blr 1388; 1389; P8LE-LABEL: fromDiffConstsConvftoi: 1390; P8LE: # %bb.0: # %entry 1391; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha 1392; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l 1393; P8LE-NEXT: lxvd2x vs0, 0, r3 1394; P8LE-NEXT: xxswapd v2, vs0 1395; P8LE-NEXT: blr 1396entry: 1397 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1398} 1399 1400define <4 x i32> @fromDiffMemConsAConvftoi(ptr nocapture readonly %ptr) { 1401; P9BE-LABEL: fromDiffMemConsAConvftoi: 1402; P9BE: # %bb.0: # %entry 1403; P9BE-NEXT: lxv vs0, 0(r3) 1404; P9BE-NEXT: xvcvspsxws v2, vs0 1405; P9BE-NEXT: blr 1406; 1407; P9LE-LABEL: fromDiffMemConsAConvftoi: 1408; P9LE: # %bb.0: # %entry 1409; P9LE-NEXT: lxv vs0, 0(r3) 1410; P9LE-NEXT: xvcvspsxws v2, vs0 1411; P9LE-NEXT: blr 1412; 1413; P8BE-LABEL: fromDiffMemConsAConvftoi: 1414; P8BE: # %bb.0: # %entry 1415; P8BE-NEXT: lxvw4x vs0, 0, r3 1416; P8BE-NEXT: xvcvspsxws v2, vs0 1417; P8BE-NEXT: blr 1418; 1419; P8LE-LABEL: fromDiffMemConsAConvftoi: 1420; P8LE: # %bb.0: # %entry 1421; P8LE-NEXT: lxvd2x vs0, 0, r3 1422; P8LE-NEXT: xxswapd v2, vs0 1423; P8LE-NEXT: xvcvspsxws v2, v2 1424; P8LE-NEXT: blr 1425entry: 1426 %0 = load <4 x float>, ptr %ptr, align 4 1427 %1 = fptosi <4 x float> %0 to <4 x i32> 1428 ret <4 x i32> %1 1429} 1430 1431define <4 x i32> @fromDiffMemConsDConvftoi(ptr nocapture readonly %ptr) { 1432; P9BE-LABEL: fromDiffMemConsDConvftoi: 1433; P9BE: # %bb.0: # %entry 1434; P9BE-NEXT: lxv vs0, 0(r3) 1435; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1436; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1437; P9BE-NEXT: lxv vs1, 0(r3) 1438; P9BE-NEXT: xxperm vs0, vs0, vs1 1439; P9BE-NEXT: xvcvspsxws v2, vs0 1440; P9BE-NEXT: blr 1441; 1442; P9LE-LABEL: fromDiffMemConsDConvftoi: 1443; P9LE: # %bb.0: # %entry 1444; P9LE-NEXT: lxv vs0, 0(r3) 1445; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1446; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1447; P9LE-NEXT: lxv vs1, 0(r3) 1448; P9LE-NEXT: xxperm vs0, vs0, vs1 1449; P9LE-NEXT: xvcvspsxws v2, vs0 1450; P9LE-NEXT: blr 1451; 1452; P8BE-LABEL: fromDiffMemConsDConvftoi: 1453; P8BE: # %bb.0: # %entry 1454; P8BE-NEXT: lxvw4x v2, 0, r3 1455; P8BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha 1456; P8BE-NEXT: addi r3, r3, .LCPI18_0@toc@l 1457; P8BE-NEXT: lxvw4x v3, 0, r3 1458; P8BE-NEXT: vperm v2, v2, v2, v3 1459; P8BE-NEXT: xvcvspsxws v2, v2 1460; P8BE-NEXT: blr 1461; 1462; P8LE-LABEL: fromDiffMemConsDConvftoi: 1463; P8LE: # %bb.0: # %entry 1464; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha 1465; P8LE-NEXT: lxvd2x v3, 0, r3 1466; P8LE-NEXT: addi r4, r4, .LCPI18_0@toc@l 1467; P8LE-NEXT: lxvd2x vs0, 0, r4 1468; P8LE-NEXT: xxswapd v2, vs0 1469; P8LE-NEXT: vperm v2, v3, v3, v2 1470; P8LE-NEXT: xvcvspsxws v2, v2 1471; P8LE-NEXT: blr 1472entry: 1473 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3 1474 %0 = load float, ptr %arrayidx, align 4 1475 %conv = fptosi float %0 to i32 1476 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1477 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2 1478 %1 = load float, ptr %arrayidx1, align 4 1479 %conv2 = fptosi float %1 to i32 1480 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1481 %arrayidx4 = getelementptr inbounds float, ptr %ptr, i64 1 1482 %2 = load float, ptr %arrayidx4, align 4 1483 %conv5 = fptosi float %2 to i32 1484 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1485 %3 = load float, ptr %ptr, align 4 1486 %conv8 = fptosi float %3 to i32 1487 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1488 ret <4 x i32> %vecinit9 1489} 1490 1491define <4 x i32> @fromDiffMemVarAConvftoi(ptr nocapture readonly %arr, i32 signext %elem) { 1492; P9BE-LABEL: fromDiffMemVarAConvftoi: 1493; P9BE: # %bb.0: # %entry 1494; P9BE-NEXT: sldi r4, r4, 2 1495; P9BE-NEXT: lfsux f0, r3, r4 1496; P9BE-NEXT: lfs f1, 12(r3) 1497; P9BE-NEXT: lfs f2, 4(r3) 1498; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1499; P9BE-NEXT: xvcvdpsp v2, vs1 1500; P9BE-NEXT: lfs f1, 8(r3) 1501; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1502; P9BE-NEXT: xvcvdpsp v3, vs0 1503; P9BE-NEXT: vmrgew v2, v3, v2 1504; P9BE-NEXT: xvcvspsxws v2, v2 1505; P9BE-NEXT: blr 1506; 1507; P9LE-LABEL: fromDiffMemVarAConvftoi: 1508; P9LE: # %bb.0: # %entry 1509; P9LE-NEXT: sldi r4, r4, 2 1510; P9LE-NEXT: lfsux f0, r3, r4 1511; P9LE-NEXT: lfs f1, 8(r3) 1512; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1513; P9LE-NEXT: lfs f1, 12(r3) 1514; P9LE-NEXT: xvcvdpsp v2, vs0 1515; P9LE-NEXT: lfs f0, 4(r3) 1516; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1517; P9LE-NEXT: xvcvdpsp v3, vs0 1518; P9LE-NEXT: vmrgew v2, v3, v2 1519; P9LE-NEXT: xvcvspsxws v2, v2 1520; P9LE-NEXT: blr 1521; 1522; P8BE-LABEL: fromDiffMemVarAConvftoi: 1523; P8BE: # %bb.0: # %entry 1524; P8BE-NEXT: sldi r4, r4, 2 1525; P8BE-NEXT: lfsux f0, r3, r4 1526; P8BE-NEXT: lfs f1, 12(r3) 1527; P8BE-NEXT: lfs f2, 4(r3) 1528; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1529; P8BE-NEXT: lfs f2, 8(r3) 1530; P8BE-NEXT: xvcvdpsp v2, vs1 1531; P8BE-NEXT: xxmrghd vs0, vs0, vs2 1532; P8BE-NEXT: xvcvdpsp v3, vs0 1533; P8BE-NEXT: vmrgew v2, v3, v2 1534; P8BE-NEXT: xvcvspsxws v2, v2 1535; P8BE-NEXT: blr 1536; 1537; P8LE-LABEL: fromDiffMemVarAConvftoi: 1538; P8LE: # %bb.0: # %entry 1539; P8LE-NEXT: sldi r4, r4, 2 1540; P8LE-NEXT: lfsux f0, r3, r4 1541; P8LE-NEXT: lfs f1, 8(r3) 1542; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1543; P8LE-NEXT: lfs f1, 4(r3) 1544; P8LE-NEXT: lfs f2, 12(r3) 1545; P8LE-NEXT: xvcvdpsp v2, vs0 1546; P8LE-NEXT: xxmrghd vs1, vs2, vs1 1547; P8LE-NEXT: xvcvdpsp v3, vs1 1548; P8LE-NEXT: vmrgew v2, v3, v2 1549; P8LE-NEXT: xvcvspsxws v2, v2 1550; P8LE-NEXT: blr 1551entry: 1552 %idxprom = sext i32 %elem to i64 1553 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom 1554 %0 = load float, ptr %arrayidx, align 4 1555 %conv = fptosi float %0 to i32 1556 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1557 %add = add nsw i32 %elem, 1 1558 %idxprom1 = sext i32 %add to i64 1559 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1 1560 %1 = load float, ptr %arrayidx2, align 4 1561 %conv3 = fptosi float %1 to i32 1562 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1563 %add5 = add nsw i32 %elem, 2 1564 %idxprom6 = sext i32 %add5 to i64 1565 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6 1566 %2 = load float, ptr %arrayidx7, align 4 1567 %conv8 = fptosi float %2 to i32 1568 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1569 %add10 = add nsw i32 %elem, 3 1570 %idxprom11 = sext i32 %add10 to i64 1571 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11 1572 %3 = load float, ptr %arrayidx12, align 4 1573 %conv13 = fptosi float %3 to i32 1574 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1575 ret <4 x i32> %vecinit14 1576} 1577 1578define <4 x i32> @fromDiffMemVarDConvftoi(ptr nocapture readonly %arr, i32 signext %elem) { 1579; P9BE-LABEL: fromDiffMemVarDConvftoi: 1580; P9BE: # %bb.0: # %entry 1581; P9BE-NEXT: sldi r4, r4, 2 1582; P9BE-NEXT: lfsux f0, r3, r4 1583; P9BE-NEXT: lfs f1, -12(r3) 1584; P9BE-NEXT: lfs f2, -4(r3) 1585; P9BE-NEXT: xxmrghd vs1, vs2, vs1 1586; P9BE-NEXT: xvcvdpsp v2, vs1 1587; P9BE-NEXT: lfs f1, -8(r3) 1588; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1589; P9BE-NEXT: xvcvdpsp v3, vs0 1590; P9BE-NEXT: vmrgew v2, v3, v2 1591; P9BE-NEXT: xvcvspsxws v2, v2 1592; P9BE-NEXT: blr 1593; 1594; P9LE-LABEL: fromDiffMemVarDConvftoi: 1595; P9LE: # %bb.0: # %entry 1596; P9LE-NEXT: sldi r4, r4, 2 1597; P9LE-NEXT: lfsux f0, r3, r4 1598; P9LE-NEXT: lfs f1, -8(r3) 1599; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1600; P9LE-NEXT: lfs f1, -12(r3) 1601; P9LE-NEXT: xvcvdpsp v2, vs0 1602; P9LE-NEXT: lfs f0, -4(r3) 1603; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1604; P9LE-NEXT: xvcvdpsp v3, vs0 1605; P9LE-NEXT: vmrgew v2, v3, v2 1606; P9LE-NEXT: xvcvspsxws v2, v2 1607; P9LE-NEXT: blr 1608; 1609; P8BE-LABEL: fromDiffMemVarDConvftoi: 1610; P8BE: # %bb.0: # %entry 1611; P8BE-NEXT: sldi r4, r4, 2 1612; P8BE-NEXT: lfsux f0, r3, r4 1613; P8BE-NEXT: lfs f1, -12(r3) 1614; P8BE-NEXT: lfs f2, -4(r3) 1615; P8BE-NEXT: xxmrghd vs1, vs2, vs1 1616; P8BE-NEXT: lfs f2, -8(r3) 1617; P8BE-NEXT: xvcvdpsp v2, vs1 1618; P8BE-NEXT: xxmrghd vs0, vs0, vs2 1619; P8BE-NEXT: xvcvdpsp v3, vs0 1620; P8BE-NEXT: vmrgew v2, v3, v2 1621; P8BE-NEXT: xvcvspsxws v2, v2 1622; P8BE-NEXT: blr 1623; 1624; P8LE-LABEL: fromDiffMemVarDConvftoi: 1625; P8LE: # %bb.0: # %entry 1626; P8LE-NEXT: sldi r4, r4, 2 1627; P8LE-NEXT: lfsux f0, r3, r4 1628; P8LE-NEXT: lfs f1, -8(r3) 1629; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1630; P8LE-NEXT: lfs f1, -4(r3) 1631; P8LE-NEXT: lfs f2, -12(r3) 1632; P8LE-NEXT: xvcvdpsp v2, vs0 1633; P8LE-NEXT: xxmrghd vs1, vs2, vs1 1634; P8LE-NEXT: xvcvdpsp v3, vs1 1635; P8LE-NEXT: vmrgew v2, v3, v2 1636; P8LE-NEXT: xvcvspsxws v2, v2 1637; P8LE-NEXT: blr 1638entry: 1639 %idxprom = sext i32 %elem to i64 1640 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom 1641 %0 = load float, ptr %arrayidx, align 4 1642 %conv = fptosi float %0 to i32 1643 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1644 %sub = add nsw i32 %elem, -1 1645 %idxprom1 = sext i32 %sub to i64 1646 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1 1647 %1 = load float, ptr %arrayidx2, align 4 1648 %conv3 = fptosi float %1 to i32 1649 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 1650 %sub5 = add nsw i32 %elem, -2 1651 %idxprom6 = sext i32 %sub5 to i64 1652 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6 1653 %2 = load float, ptr %arrayidx7, align 4 1654 %conv8 = fptosi float %2 to i32 1655 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 1656 %sub10 = add nsw i32 %elem, -3 1657 %idxprom11 = sext i32 %sub10 to i64 1658 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11 1659 %3 = load float, ptr %arrayidx12, align 4 1660 %conv13 = fptosi float %3 to i32 1661 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 1662 ret <4 x i32> %vecinit14 1663; FIXME: implement finding consecutive loads with pre-inc 1664} 1665 1666define <4 x i32> @spltRegValConvftoi(float %val) { 1667; P9BE-LABEL: spltRegValConvftoi: 1668; P9BE: # %bb.0: # %entry 1669; P9BE-NEXT: xscvdpsxws f0, f1 1670; P9BE-NEXT: xxspltw v2, vs0, 1 1671; P9BE-NEXT: blr 1672; 1673; P9LE-LABEL: spltRegValConvftoi: 1674; P9LE: # %bb.0: # %entry 1675; P9LE-NEXT: xscvdpsxws f0, f1 1676; P9LE-NEXT: xxspltw v2, vs0, 1 1677; P9LE-NEXT: blr 1678; 1679; P8BE-LABEL: spltRegValConvftoi: 1680; P8BE: # %bb.0: # %entry 1681; P8BE-NEXT: xscvdpsxws f0, f1 1682; P8BE-NEXT: xxspltw v2, vs0, 1 1683; P8BE-NEXT: blr 1684; 1685; P8LE-LABEL: spltRegValConvftoi: 1686; P8LE: # %bb.0: # %entry 1687; P8LE-NEXT: xscvdpsxws f0, f1 1688; P8LE-NEXT: xxspltw v2, vs0, 1 1689; P8LE-NEXT: blr 1690entry: 1691 %conv = fptosi float %val to i32 1692 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1693 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1694 ret <4 x i32> %splat.splat 1695} 1696 1697define <4 x i32> @spltMemValConvftoi(ptr nocapture readonly %ptr) { 1698; P9BE-LABEL: spltMemValConvftoi: 1699; P9BE: # %bb.0: # %entry 1700; P9BE-NEXT: lfiwzx f0, 0, r3 1701; P9BE-NEXT: xvcvspsxws vs0, vs0 1702; P9BE-NEXT: xxspltw v2, vs0, 1 1703; P9BE-NEXT: blr 1704; 1705; P9LE-LABEL: spltMemValConvftoi: 1706; P9LE: # %bb.0: # %entry 1707; P9LE-NEXT: lfiwzx f0, 0, r3 1708; P9LE-NEXT: xvcvspsxws vs0, vs0 1709; P9LE-NEXT: xxspltw v2, vs0, 1 1710; P9LE-NEXT: blr 1711; 1712; P8BE-LABEL: spltMemValConvftoi: 1713; P8BE: # %bb.0: # %entry 1714; P8BE-NEXT: lfsx f0, 0, r3 1715; P8BE-NEXT: xscvdpsxws f0, f0 1716; P8BE-NEXT: xxspltw v2, vs0, 1 1717; P8BE-NEXT: blr 1718; 1719; P8LE-LABEL: spltMemValConvftoi: 1720; P8LE: # %bb.0: # %entry 1721; P8LE-NEXT: lfsx f0, 0, r3 1722; P8LE-NEXT: xscvdpsxws f0, f0 1723; P8LE-NEXT: xxspltw v2, vs0, 1 1724; P8LE-NEXT: blr 1725entry: 1726 %0 = load float, ptr %ptr, align 4 1727 %conv = fptosi float %0 to i32 1728 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 1729 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 1730 ret <4 x i32> %splat.splat 1731} 1732 1733define <4 x i32> @spltCnstConvdtoi() { 1734; P9BE-LABEL: spltCnstConvdtoi: 1735; P9BE: # %bb.0: # %entry 1736; P9BE-NEXT: vspltisw v2, 4 1737; P9BE-NEXT: blr 1738; 1739; P9LE-LABEL: spltCnstConvdtoi: 1740; P9LE: # %bb.0: # %entry 1741; P9LE-NEXT: vspltisw v2, 4 1742; P9LE-NEXT: blr 1743; 1744; P8BE-LABEL: spltCnstConvdtoi: 1745; P8BE: # %bb.0: # %entry 1746; P8BE-NEXT: vspltisw v2, 4 1747; P8BE-NEXT: blr 1748; 1749; P8LE-LABEL: spltCnstConvdtoi: 1750; P8LE: # %bb.0: # %entry 1751; P8LE-NEXT: vspltisw v2, 4 1752; P8LE-NEXT: blr 1753entry: 1754 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 1755} 1756 1757define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) { 1758; P9BE-LABEL: fromRegsConvdtoi: 1759; P9BE: # %bb.0: # %entry 1760; P9BE-NEXT: xxmrghd vs0, vs2, vs4 1761; P9BE-NEXT: xvcvdpsxws v2, vs0 1762; P9BE-NEXT: xxmrghd vs0, vs1, vs3 1763; P9BE-NEXT: xvcvdpsxws v3, vs0 1764; P9BE-NEXT: vmrgew v2, v3, v2 1765; P9BE-NEXT: blr 1766; 1767; P9LE-LABEL: fromRegsConvdtoi: 1768; P9LE: # %bb.0: # %entry 1769; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1770; P9LE-NEXT: xvcvdpsxws v2, vs0 1771; P9LE-NEXT: xxmrghd vs0, vs4, vs2 1772; P9LE-NEXT: xvcvdpsxws v3, vs0 1773; P9LE-NEXT: vmrgew v2, v3, v2 1774; P9LE-NEXT: blr 1775; 1776; P8BE-LABEL: fromRegsConvdtoi: 1777; P8BE: # %bb.0: # %entry 1778; P8BE-NEXT: xxmrghd vs0, vs2, vs4 1779; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1780; P8BE-NEXT: xvcvdpsxws v2, vs0 1781; P8BE-NEXT: xvcvdpsxws v3, vs1 1782; P8BE-NEXT: vmrgew v2, v3, v2 1783; P8BE-NEXT: blr 1784; 1785; P8LE-LABEL: fromRegsConvdtoi: 1786; P8LE: # %bb.0: # %entry 1787; P8LE-NEXT: xxmrghd vs0, vs3, vs1 1788; P8LE-NEXT: xxmrghd vs1, vs4, vs2 1789; P8LE-NEXT: xvcvdpsxws v2, vs0 1790; P8LE-NEXT: xvcvdpsxws v3, vs1 1791; P8LE-NEXT: vmrgew v2, v3, v2 1792; P8LE-NEXT: blr 1793entry: 1794 %conv = fptosi double %a to i32 1795 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1796 %conv1 = fptosi double %b to i32 1797 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 1798 %conv3 = fptosi double %c to i32 1799 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 1800 %conv5 = fptosi double %d to i32 1801 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 1802 ret <4 x i32> %vecinit6 1803} 1804 1805define <4 x i32> @fromDiffConstsConvdtoi() { 1806; P9BE-LABEL: fromDiffConstsConvdtoi: 1807; P9BE: # %bb.0: # %entry 1808; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1809; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1810; P9BE-NEXT: lxv v2, 0(r3) 1811; P9BE-NEXT: blr 1812; 1813; P9LE-LABEL: fromDiffConstsConvdtoi: 1814; P9LE: # %bb.0: # %entry 1815; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1816; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1817; P9LE-NEXT: lxv v2, 0(r3) 1818; P9LE-NEXT: blr 1819; 1820; P8BE-LABEL: fromDiffConstsConvdtoi: 1821; P8BE: # %bb.0: # %entry 1822; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1823; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1824; P8BE-NEXT: lxvw4x v2, 0, r3 1825; P8BE-NEXT: blr 1826; 1827; P8LE-LABEL: fromDiffConstsConvdtoi: 1828; P8LE: # %bb.0: # %entry 1829; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha 1830; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l 1831; P8LE-NEXT: lxvd2x vs0, 0, r3 1832; P8LE-NEXT: xxswapd v2, vs0 1833; P8LE-NEXT: blr 1834entry: 1835 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 1836} 1837 1838define <4 x i32> @fromDiffMemConsAConvdtoi(ptr nocapture readonly %ptr) { 1839; P9BE-LABEL: fromDiffMemConsAConvdtoi: 1840; P9BE: # %bb.0: # %entry 1841; P9BE-NEXT: lxv vs0, 0(r3) 1842; P9BE-NEXT: lxv vs1, 16(r3) 1843; P9BE-NEXT: xxmrgld vs2, vs0, vs1 1844; P9BE-NEXT: xxmrghd vs0, vs0, vs1 1845; P9BE-NEXT: xvcvdpsxws v2, vs2 1846; P9BE-NEXT: xvcvdpsxws v3, vs0 1847; P9BE-NEXT: vmrgew v2, v3, v2 1848; P9BE-NEXT: blr 1849; 1850; P9LE-LABEL: fromDiffMemConsAConvdtoi: 1851; P9LE: # %bb.0: # %entry 1852; P9LE-NEXT: lxv vs0, 0(r3) 1853; P9LE-NEXT: lxv vs1, 16(r3) 1854; P9LE-NEXT: xxmrgld vs2, vs1, vs0 1855; P9LE-NEXT: xxmrghd vs0, vs1, vs0 1856; P9LE-NEXT: xvcvdpsxws v2, vs2 1857; P9LE-NEXT: xvcvdpsxws v3, vs0 1858; P9LE-NEXT: vmrgew v2, v3, v2 1859; P9LE-NEXT: blr 1860; 1861; P8BE-LABEL: fromDiffMemConsAConvdtoi: 1862; P8BE: # %bb.0: # %entry 1863; P8BE-NEXT: li r4, 16 1864; P8BE-NEXT: lxvd2x vs0, 0, r3 1865; P8BE-NEXT: lxvd2x vs1, r3, r4 1866; P8BE-NEXT: xxmrgld vs2, vs0, vs1 1867; P8BE-NEXT: xxmrghd vs0, vs0, vs1 1868; P8BE-NEXT: xvcvdpsxws v2, vs2 1869; P8BE-NEXT: xvcvdpsxws v3, vs0 1870; P8BE-NEXT: vmrgew v2, v3, v2 1871; P8BE-NEXT: blr 1872; 1873; P8LE-LABEL: fromDiffMemConsAConvdtoi: 1874; P8LE: # %bb.0: # %entry 1875; P8LE-NEXT: li r4, 16 1876; P8LE-NEXT: lxvd2x vs0, 0, r3 1877; P8LE-NEXT: lxvd2x vs1, r3, r4 1878; P8LE-NEXT: xxswapd vs0, vs0 1879; P8LE-NEXT: xxswapd vs1, vs1 1880; P8LE-NEXT: xxmrgld vs2, vs1, vs0 1881; P8LE-NEXT: xxmrghd vs0, vs1, vs0 1882; P8LE-NEXT: xvcvdpsxws v2, vs2 1883; P8LE-NEXT: xvcvdpsxws v3, vs0 1884; P8LE-NEXT: vmrgew v2, v3, v2 1885; P8LE-NEXT: blr 1886entry: 1887 %0 = load <2 x double>, ptr %ptr, align 8 1888 %1 = fptosi <2 x double> %0 to <2 x i32> 1889 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 2 1890 %2 = load <2 x double>, ptr %arrayidx4, align 8 1891 %3 = fptosi <2 x double> %2 to <2 x i32> 1892 %vecinit9 = shufflevector <2 x i32> %1, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 1893 ret <4 x i32> %vecinit9 1894} 1895 1896define <4 x i32> @fromDiffMemConsDConvdtoi(ptr nocapture readonly %ptr) { 1897; P9BE-LABEL: fromDiffMemConsDConvdtoi: 1898; P9BE: # %bb.0: # %entry 1899; P9BE-NEXT: lfd f0, 24(r3) 1900; P9BE-NEXT: lfd f1, 16(r3) 1901; P9BE-NEXT: lfd f2, 8(r3) 1902; P9BE-NEXT: xxmrghd vs0, vs0, vs2 1903; P9BE-NEXT: lfd f3, 0(r3) 1904; P9BE-NEXT: xxmrghd vs1, vs1, vs3 1905; P9BE-NEXT: xvcvdpsxws v2, vs1 1906; P9BE-NEXT: xvcvdpsxws v3, vs0 1907; P9BE-NEXT: vmrgew v2, v3, v2 1908; P9BE-NEXT: blr 1909; 1910; P9LE-LABEL: fromDiffMemConsDConvdtoi: 1911; P9LE: # %bb.0: # %entry 1912; P9LE-NEXT: lfd f0, 24(r3) 1913; P9LE-NEXT: lfd f2, 8(r3) 1914; P9LE-NEXT: xxmrghd vs0, vs2, vs0 1915; P9LE-NEXT: lfd f1, 16(r3) 1916; P9LE-NEXT: lfd f3, 0(r3) 1917; P9LE-NEXT: xvcvdpsxws v2, vs0 1918; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1919; P9LE-NEXT: xvcvdpsxws v3, vs0 1920; P9LE-NEXT: vmrgew v2, v3, v2 1921; P9LE-NEXT: blr 1922; 1923; P8BE-LABEL: fromDiffMemConsDConvdtoi: 1924; P8BE: # %bb.0: # %entry 1925; P8BE-NEXT: lfd f0, 24(r3) 1926; P8BE-NEXT: lfd f1, 16(r3) 1927; P8BE-NEXT: lfd f2, 8(r3) 1928; P8BE-NEXT: lfd f3, 0(r3) 1929; P8BE-NEXT: xxmrghd vs1, vs1, vs3 1930; P8BE-NEXT: xxmrghd vs0, vs0, vs2 1931; P8BE-NEXT: xvcvdpsxws v2, vs1 1932; P8BE-NEXT: xvcvdpsxws v3, vs0 1933; P8BE-NEXT: vmrgew v2, v3, v2 1934; P8BE-NEXT: blr 1935; 1936; P8LE-LABEL: fromDiffMemConsDConvdtoi: 1937; P8LE: # %bb.0: # %entry 1938; P8LE-NEXT: lfd f0, 24(r3) 1939; P8LE-NEXT: lfd f1, 16(r3) 1940; P8LE-NEXT: lfd f2, 8(r3) 1941; P8LE-NEXT: lfd f3, 0(r3) 1942; P8LE-NEXT: xxmrghd vs0, vs2, vs0 1943; P8LE-NEXT: xxmrghd vs1, vs3, vs1 1944; P8LE-NEXT: xvcvdpsxws v2, vs0 1945; P8LE-NEXT: xvcvdpsxws v3, vs1 1946; P8LE-NEXT: vmrgew v2, v3, v2 1947; P8LE-NEXT: blr 1948entry: 1949 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3 1950 %0 = load double, ptr %arrayidx, align 8 1951 %conv = fptosi double %0 to i32 1952 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 1953 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2 1954 %1 = load double, ptr %arrayidx1, align 8 1955 %conv2 = fptosi double %1 to i32 1956 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 1957 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 1 1958 %2 = load double, ptr %arrayidx4, align 8 1959 %conv5 = fptosi double %2 to i32 1960 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 1961 %3 = load double, ptr %ptr, align 8 1962 %conv8 = fptosi double %3 to i32 1963 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 1964 ret <4 x i32> %vecinit9 1965} 1966 1967define <4 x i32> @fromDiffMemVarAConvdtoi(ptr nocapture readonly %arr, i32 signext %elem) { 1968; P9BE-LABEL: fromDiffMemVarAConvdtoi: 1969; P9BE: # %bb.0: # %entry 1970; P9BE-NEXT: sldi r4, r4, 3 1971; P9BE-NEXT: lfdux f0, r3, r4 1972; P9BE-NEXT: lfd f1, 8(r3) 1973; P9BE-NEXT: lfd f2, 16(r3) 1974; P9BE-NEXT: lfd f3, 24(r3) 1975; P9BE-NEXT: xxmrghd vs1, vs1, vs3 1976; P9BE-NEXT: xxmrghd vs0, vs0, vs2 1977; P9BE-NEXT: xvcvdpsxws v2, vs1 1978; P9BE-NEXT: xvcvdpsxws v3, vs0 1979; P9BE-NEXT: vmrgew v2, v3, v2 1980; P9BE-NEXT: blr 1981; 1982; P9LE-LABEL: fromDiffMemVarAConvdtoi: 1983; P9LE: # %bb.0: # %entry 1984; P9LE-NEXT: sldi r4, r4, 3 1985; P9LE-NEXT: lfdux f0, r3, r4 1986; P9LE-NEXT: lfd f2, 16(r3) 1987; P9LE-NEXT: lfd f1, 8(r3) 1988; P9LE-NEXT: lfd f3, 24(r3) 1989; P9LE-NEXT: xxmrghd vs0, vs2, vs0 1990; P9LE-NEXT: xvcvdpsxws v2, vs0 1991; P9LE-NEXT: xxmrghd vs0, vs3, vs1 1992; P9LE-NEXT: xvcvdpsxws v3, vs0 1993; P9LE-NEXT: vmrgew v2, v3, v2 1994; P9LE-NEXT: blr 1995; 1996; P8BE-LABEL: fromDiffMemVarAConvdtoi: 1997; P8BE: # %bb.0: # %entry 1998; P8BE-NEXT: sldi r4, r4, 3 1999; P8BE-NEXT: lfdux f0, r3, r4 2000; P8BE-NEXT: lfd f1, 8(r3) 2001; P8BE-NEXT: lfd f2, 16(r3) 2002; P8BE-NEXT: lfd f3, 24(r3) 2003; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2004; P8BE-NEXT: xxmrghd vs0, vs0, vs2 2005; P8BE-NEXT: xvcvdpsxws v2, vs1 2006; P8BE-NEXT: xvcvdpsxws v3, vs0 2007; P8BE-NEXT: vmrgew v2, v3, v2 2008; P8BE-NEXT: blr 2009; 2010; P8LE-LABEL: fromDiffMemVarAConvdtoi: 2011; P8LE: # %bb.0: # %entry 2012; P8LE-NEXT: sldi r4, r4, 3 2013; P8LE-NEXT: lfdux f0, r3, r4 2014; P8LE-NEXT: lfd f1, 8(r3) 2015; P8LE-NEXT: lfd f2, 16(r3) 2016; P8LE-NEXT: lfd f3, 24(r3) 2017; P8LE-NEXT: xxmrghd vs0, vs2, vs0 2018; P8LE-NEXT: xxmrghd vs1, vs3, vs1 2019; P8LE-NEXT: xvcvdpsxws v2, vs0 2020; P8LE-NEXT: xvcvdpsxws v3, vs1 2021; P8LE-NEXT: vmrgew v2, v3, v2 2022; P8LE-NEXT: blr 2023entry: 2024 %idxprom = sext i32 %elem to i64 2025 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom 2026 %0 = load double, ptr %arrayidx, align 8 2027 %conv = fptosi double %0 to i32 2028 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2029 %add = add nsw i32 %elem, 1 2030 %idxprom1 = sext i32 %add to i64 2031 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1 2032 %1 = load double, ptr %arrayidx2, align 8 2033 %conv3 = fptosi double %1 to i32 2034 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2035 %add5 = add nsw i32 %elem, 2 2036 %idxprom6 = sext i32 %add5 to i64 2037 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6 2038 %2 = load double, ptr %arrayidx7, align 8 2039 %conv8 = fptosi double %2 to i32 2040 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2041 %add10 = add nsw i32 %elem, 3 2042 %idxprom11 = sext i32 %add10 to i64 2043 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11 2044 %3 = load double, ptr %arrayidx12, align 8 2045 %conv13 = fptosi double %3 to i32 2046 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2047 ret <4 x i32> %vecinit14 2048} 2049 2050define <4 x i32> @fromDiffMemVarDConvdtoi(ptr nocapture readonly %arr, i32 signext %elem) { 2051; P9BE-LABEL: fromDiffMemVarDConvdtoi: 2052; P9BE: # %bb.0: # %entry 2053; P9BE-NEXT: sldi r4, r4, 3 2054; P9BE-NEXT: lfdux f0, r3, r4 2055; P9BE-NEXT: lfd f1, -8(r3) 2056; P9BE-NEXT: lfd f2, -16(r3) 2057; P9BE-NEXT: lfd f3, -24(r3) 2058; P9BE-NEXT: xxmrghd vs1, vs1, vs3 2059; P9BE-NEXT: xxmrghd vs0, vs0, vs2 2060; P9BE-NEXT: xvcvdpsxws v2, vs1 2061; P9BE-NEXT: xvcvdpsxws v3, vs0 2062; P9BE-NEXT: vmrgew v2, v3, v2 2063; P9BE-NEXT: blr 2064; 2065; P9LE-LABEL: fromDiffMemVarDConvdtoi: 2066; P9LE: # %bb.0: # %entry 2067; P9LE-NEXT: sldi r4, r4, 3 2068; P9LE-NEXT: lfdux f0, r3, r4 2069; P9LE-NEXT: lfd f2, -16(r3) 2070; P9LE-NEXT: lfd f1, -8(r3) 2071; P9LE-NEXT: lfd f3, -24(r3) 2072; P9LE-NEXT: xxmrghd vs0, vs2, vs0 2073; P9LE-NEXT: xvcvdpsxws v2, vs0 2074; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2075; P9LE-NEXT: xvcvdpsxws v3, vs0 2076; P9LE-NEXT: vmrgew v2, v3, v2 2077; P9LE-NEXT: blr 2078; 2079; P8BE-LABEL: fromDiffMemVarDConvdtoi: 2080; P8BE: # %bb.0: # %entry 2081; P8BE-NEXT: sldi r4, r4, 3 2082; P8BE-NEXT: lfdux f0, r3, r4 2083; P8BE-NEXT: lfd f1, -8(r3) 2084; P8BE-NEXT: lfd f2, -16(r3) 2085; P8BE-NEXT: lfd f3, -24(r3) 2086; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2087; P8BE-NEXT: xxmrghd vs0, vs0, vs2 2088; P8BE-NEXT: xvcvdpsxws v2, vs1 2089; P8BE-NEXT: xvcvdpsxws v3, vs0 2090; P8BE-NEXT: vmrgew v2, v3, v2 2091; P8BE-NEXT: blr 2092; 2093; P8LE-LABEL: fromDiffMemVarDConvdtoi: 2094; P8LE: # %bb.0: # %entry 2095; P8LE-NEXT: sldi r4, r4, 3 2096; P8LE-NEXT: lfdux f0, r3, r4 2097; P8LE-NEXT: lfd f1, -8(r3) 2098; P8LE-NEXT: lfd f2, -16(r3) 2099; P8LE-NEXT: lfd f3, -24(r3) 2100; P8LE-NEXT: xxmrghd vs0, vs2, vs0 2101; P8LE-NEXT: xxmrghd vs1, vs3, vs1 2102; P8LE-NEXT: xvcvdpsxws v2, vs0 2103; P8LE-NEXT: xvcvdpsxws v3, vs1 2104; P8LE-NEXT: vmrgew v2, v3, v2 2105; P8LE-NEXT: blr 2106entry: 2107 %idxprom = sext i32 %elem to i64 2108 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom 2109 %0 = load double, ptr %arrayidx, align 8 2110 %conv = fptosi double %0 to i32 2111 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2112 %sub = add nsw i32 %elem, -1 2113 %idxprom1 = sext i32 %sub to i64 2114 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1 2115 %1 = load double, ptr %arrayidx2, align 8 2116 %conv3 = fptosi double %1 to i32 2117 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 2118 %sub5 = add nsw i32 %elem, -2 2119 %idxprom6 = sext i32 %sub5 to i64 2120 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6 2121 %2 = load double, ptr %arrayidx7, align 8 2122 %conv8 = fptosi double %2 to i32 2123 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 2124 %sub10 = add nsw i32 %elem, -3 2125 %idxprom11 = sext i32 %sub10 to i64 2126 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11 2127 %3 = load double, ptr %arrayidx12, align 8 2128 %conv13 = fptosi double %3 to i32 2129 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 2130 ret <4 x i32> %vecinit14 2131} 2132 2133define <4 x i32> @spltRegValConvdtoi(double %val) { 2134; P9BE-LABEL: spltRegValConvdtoi: 2135; P9BE: # %bb.0: # %entry 2136; P9BE-NEXT: xscvdpsxws f0, f1 2137; P9BE-NEXT: xxspltw v2, vs0, 1 2138; P9BE-NEXT: blr 2139; 2140; P9LE-LABEL: spltRegValConvdtoi: 2141; P9LE: # %bb.0: # %entry 2142; P9LE-NEXT: xscvdpsxws f0, f1 2143; P9LE-NEXT: xxspltw v2, vs0, 1 2144; P9LE-NEXT: blr 2145; 2146; P8BE-LABEL: spltRegValConvdtoi: 2147; P8BE: # %bb.0: # %entry 2148; P8BE-NEXT: xscvdpsxws f0, f1 2149; P8BE-NEXT: xxspltw v2, vs0, 1 2150; P8BE-NEXT: blr 2151; 2152; P8LE-LABEL: spltRegValConvdtoi: 2153; P8LE: # %bb.0: # %entry 2154; P8LE-NEXT: xscvdpsxws f0, f1 2155; P8LE-NEXT: xxspltw v2, vs0, 1 2156; P8LE-NEXT: blr 2157entry: 2158 %conv = fptosi double %val to i32 2159 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2160 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2161 ret <4 x i32> %splat.splat 2162} 2163 2164define <4 x i32> @spltMemValConvdtoi(ptr nocapture readonly %ptr) { 2165; P9BE-LABEL: spltMemValConvdtoi: 2166; P9BE: # %bb.0: # %entry 2167; P9BE-NEXT: lfd f0, 0(r3) 2168; P9BE-NEXT: xscvdpsxws f0, f0 2169; P9BE-NEXT: xxspltw v2, vs0, 1 2170; P9BE-NEXT: blr 2171; 2172; P9LE-LABEL: spltMemValConvdtoi: 2173; P9LE: # %bb.0: # %entry 2174; P9LE-NEXT: lfd f0, 0(r3) 2175; P9LE-NEXT: xscvdpsxws f0, f0 2176; P9LE-NEXT: xxspltw v2, vs0, 1 2177; P9LE-NEXT: blr 2178; 2179; P8BE-LABEL: spltMemValConvdtoi: 2180; P8BE: # %bb.0: # %entry 2181; P8BE-NEXT: lfdx f0, 0, r3 2182; P8BE-NEXT: xscvdpsxws f0, f0 2183; P8BE-NEXT: xxspltw v2, vs0, 1 2184; P8BE-NEXT: blr 2185; 2186; P8LE-LABEL: spltMemValConvdtoi: 2187; P8LE: # %bb.0: # %entry 2188; P8LE-NEXT: lfdx f0, 0, r3 2189; P8LE-NEXT: xscvdpsxws f0, f0 2190; P8LE-NEXT: xxspltw v2, vs0, 1 2191; P8LE-NEXT: blr 2192entry: 2193 %0 = load double, ptr %ptr, align 8 2194 %conv = fptosi double %0 to i32 2195 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 2196 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2197 ret <4 x i32> %splat.splat 2198} 2199 2200define <4 x i32> @allZeroui() { 2201; P9BE-LABEL: allZeroui: 2202; P9BE: # %bb.0: # %entry 2203; P9BE-NEXT: xxlxor v2, v2, v2 2204; P9BE-NEXT: blr 2205; 2206; P9LE-LABEL: allZeroui: 2207; P9LE: # %bb.0: # %entry 2208; P9LE-NEXT: xxlxor v2, v2, v2 2209; P9LE-NEXT: blr 2210; 2211; P8BE-LABEL: allZeroui: 2212; P8BE: # %bb.0: # %entry 2213; P8BE-NEXT: xxlxor v2, v2, v2 2214; P8BE-NEXT: blr 2215; 2216; P8LE-LABEL: allZeroui: 2217; P8LE: # %bb.0: # %entry 2218; P8LE-NEXT: xxlxor v2, v2, v2 2219; P8LE-NEXT: blr 2220entry: 2221 ret <4 x i32> zeroinitializer 2222} 2223 2224define <4 x i32> @spltConst1ui() { 2225; P9BE-LABEL: spltConst1ui: 2226; P9BE: # %bb.0: # %entry 2227; P9BE-NEXT: vspltisw v2, 1 2228; P9BE-NEXT: blr 2229; 2230; P9LE-LABEL: spltConst1ui: 2231; P9LE: # %bb.0: # %entry 2232; P9LE-NEXT: vspltisw v2, 1 2233; P9LE-NEXT: blr 2234; 2235; P8BE-LABEL: spltConst1ui: 2236; P8BE: # %bb.0: # %entry 2237; P8BE-NEXT: vspltisw v2, 1 2238; P8BE-NEXT: blr 2239; 2240; P8LE-LABEL: spltConst1ui: 2241; P8LE: # %bb.0: # %entry 2242; P8LE-NEXT: vspltisw v2, 1 2243; P8LE-NEXT: blr 2244entry: 2245 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1> 2246} 2247 2248define <4 x i32> @spltConst16kui() { 2249; P9BE-LABEL: spltConst16kui: 2250; P9BE: # %bb.0: # %entry 2251; P9BE-NEXT: vspltisw v2, -15 2252; P9BE-NEXT: vsrw v2, v2, v2 2253; P9BE-NEXT: blr 2254; 2255; P9LE-LABEL: spltConst16kui: 2256; P9LE: # %bb.0: # %entry 2257; P9LE-NEXT: vspltisw v2, -15 2258; P9LE-NEXT: vsrw v2, v2, v2 2259; P9LE-NEXT: blr 2260; 2261; P8BE-LABEL: spltConst16kui: 2262; P8BE: # %bb.0: # %entry 2263; P8BE-NEXT: vspltisw v2, -15 2264; P8BE-NEXT: vsrw v2, v2, v2 2265; P8BE-NEXT: blr 2266; 2267; P8LE-LABEL: spltConst16kui: 2268; P8LE: # %bb.0: # %entry 2269; P8LE-NEXT: vspltisw v2, -15 2270; P8LE-NEXT: vsrw v2, v2, v2 2271; P8LE-NEXT: blr 2272entry: 2273 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> 2274} 2275 2276define <4 x i32> @spltConst32kui() { 2277; P9BE-LABEL: spltConst32kui: 2278; P9BE: # %bb.0: # %entry 2279; P9BE-NEXT: vspltisw v2, -16 2280; P9BE-NEXT: vsrw v2, v2, v2 2281; P9BE-NEXT: blr 2282; 2283; P9LE-LABEL: spltConst32kui: 2284; P9LE: # %bb.0: # %entry 2285; P9LE-NEXT: vspltisw v2, -16 2286; P9LE-NEXT: vsrw v2, v2, v2 2287; P9LE-NEXT: blr 2288; 2289; P8BE-LABEL: spltConst32kui: 2290; P8BE: # %bb.0: # %entry 2291; P8BE-NEXT: vspltisw v2, -16 2292; P8BE-NEXT: vsrw v2, v2, v2 2293; P8BE-NEXT: blr 2294; 2295; P8LE-LABEL: spltConst32kui: 2296; P8LE: # %bb.0: # %entry 2297; P8LE-NEXT: vspltisw v2, -16 2298; P8LE-NEXT: vsrw v2, v2, v2 2299; P8LE-NEXT: blr 2300entry: 2301 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> 2302} 2303 2304define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) { 2305; P9BE-LABEL: fromRegsui: 2306; P9BE: # %bb.0: # %entry 2307; P9BE-NEXT: rldimi r6, r5, 32, 0 2308; P9BE-NEXT: rldimi r4, r3, 32, 0 2309; P9BE-NEXT: mtvsrdd v2, r4, r6 2310; P9BE-NEXT: blr 2311; 2312; P9LE-LABEL: fromRegsui: 2313; P9LE: # %bb.0: # %entry 2314; P9LE-NEXT: rldimi r3, r4, 32, 0 2315; P9LE-NEXT: rldimi r5, r6, 32, 0 2316; P9LE-NEXT: mtvsrdd v2, r5, r3 2317; P9LE-NEXT: blr 2318; 2319; P8BE-LABEL: fromRegsui: 2320; P8BE: # %bb.0: # %entry 2321; P8BE-NEXT: rldimi r6, r5, 32, 0 2322; P8BE-NEXT: rldimi r4, r3, 32, 0 2323; P8BE-NEXT: mtfprd f0, r6 2324; P8BE-NEXT: mtfprd f1, r4 2325; P8BE-NEXT: xxmrghd v2, vs1, vs0 2326; P8BE-NEXT: blr 2327; 2328; P8LE-LABEL: fromRegsui: 2329; P8LE: # %bb.0: # %entry 2330; P8LE-NEXT: rldimi r3, r4, 32, 0 2331; P8LE-NEXT: rldimi r5, r6, 32, 0 2332; P8LE-NEXT: mtfprd f0, r3 2333; P8LE-NEXT: mtfprd f1, r5 2334; P8LE-NEXT: xxmrghd v2, vs1, vs0 2335; P8LE-NEXT: blr 2336entry: 2337 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 2338 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 2339 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 2340 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 2341 ret <4 x i32> %vecinit3 2342} 2343 2344define <4 x i32> @fromDiffConstsui() { 2345; P9BE-LABEL: fromDiffConstsui: 2346; P9BE: # %bb.0: # %entry 2347; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2348; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2349; P9BE-NEXT: lxv v2, 0(r3) 2350; P9BE-NEXT: blr 2351; 2352; P9LE-LABEL: fromDiffConstsui: 2353; P9LE: # %bb.0: # %entry 2354; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2355; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2356; P9LE-NEXT: lxv v2, 0(r3) 2357; P9LE-NEXT: blr 2358; 2359; P8BE-LABEL: fromDiffConstsui: 2360; P8BE: # %bb.0: # %entry 2361; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2362; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2363; P8BE-NEXT: lxvw4x v2, 0, r3 2364; P8BE-NEXT: blr 2365; 2366; P8LE-LABEL: fromDiffConstsui: 2367; P8LE: # %bb.0: # %entry 2368; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha 2369; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l 2370; P8LE-NEXT: lxvd2x vs0, 0, r3 2371; P8LE-NEXT: xxswapd v2, vs0 2372; P8LE-NEXT: blr 2373entry: 2374 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19> 2375} 2376 2377define <4 x i32> @fromDiffMemConsAui(ptr nocapture readonly %arr) { 2378; P9BE-LABEL: fromDiffMemConsAui: 2379; P9BE: # %bb.0: # %entry 2380; P9BE-NEXT: lxv v2, 0(r3) 2381; P9BE-NEXT: blr 2382; 2383; P9LE-LABEL: fromDiffMemConsAui: 2384; P9LE: # %bb.0: # %entry 2385; P9LE-NEXT: lxv v2, 0(r3) 2386; P9LE-NEXT: blr 2387; 2388; P8BE-LABEL: fromDiffMemConsAui: 2389; P8BE: # %bb.0: # %entry 2390; P8BE-NEXT: lxvw4x v2, 0, r3 2391; P8BE-NEXT: blr 2392; 2393; P8LE-LABEL: fromDiffMemConsAui: 2394; P8LE: # %bb.0: # %entry 2395; P8LE-NEXT: lxvd2x vs0, 0, r3 2396; P8LE-NEXT: xxswapd v2, vs0 2397; P8LE-NEXT: blr 2398entry: 2399 %0 = load i32, ptr %arr, align 4 2400 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2401 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 1 2402 %1 = load i32, ptr %arrayidx1, align 4 2403 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2404 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2 2405 %2 = load i32, ptr %arrayidx3, align 4 2406 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2407 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 3 2408 %3 = load i32, ptr %arrayidx5, align 4 2409 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2410 ret <4 x i32> %vecinit6 2411} 2412 2413define <4 x i32> @fromDiffMemConsDui(ptr nocapture readonly %arr) { 2414; P9BE-LABEL: fromDiffMemConsDui: 2415; P9BE: # %bb.0: # %entry 2416; P9BE-NEXT: lxv v2, 0(r3) 2417; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2418; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2419; P9BE-NEXT: lxv vs0, 0(r3) 2420; P9BE-NEXT: xxperm v2, v2, vs0 2421; P9BE-NEXT: blr 2422; 2423; P9LE-LABEL: fromDiffMemConsDui: 2424; P9LE: # %bb.0: # %entry 2425; P9LE-NEXT: lxvw4x v2, 0, r3 2426; P9LE-NEXT: blr 2427; 2428; P8BE-LABEL: fromDiffMemConsDui: 2429; P8BE: # %bb.0: # %entry 2430; P8BE-NEXT: lxvw4x v2, 0, r3 2431; P8BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2432; P8BE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2433; P8BE-NEXT: lxvw4x v3, 0, r3 2434; P8BE-NEXT: vperm v2, v2, v2, v3 2435; P8BE-NEXT: blr 2436; 2437; P8LE-LABEL: fromDiffMemConsDui: 2438; P8LE: # %bb.0: # %entry 2439; P8LE-NEXT: lxvd2x vs0, 0, r3 2440; P8LE-NEXT: addis r3, r2, .LCPI39_0@toc@ha 2441; P8LE-NEXT: addi r3, r3, .LCPI39_0@toc@l 2442; P8LE-NEXT: xxswapd v2, vs0 2443; P8LE-NEXT: lxvd2x vs0, 0, r3 2444; P8LE-NEXT: xxswapd v3, vs0 2445; P8LE-NEXT: vperm v2, v2, v2, v3 2446; P8LE-NEXT: blr 2447entry: 2448 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 3 2449 %0 = load i32, ptr %arrayidx, align 4 2450 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2451 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 2 2452 %1 = load i32, ptr %arrayidx1, align 4 2453 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2454 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 1 2455 %2 = load i32, ptr %arrayidx3, align 4 2456 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2457 %3 = load i32, ptr %arr, align 4 2458 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2459 ret <4 x i32> %vecinit6 2460} 2461 2462define <4 x i32> @fromDiffMemVarAui(ptr nocapture readonly %arr, i32 signext %elem) { 2463; P9BE-LABEL: fromDiffMemVarAui: 2464; P9BE: # %bb.0: # %entry 2465; P9BE-NEXT: sldi r4, r4, 2 2466; P9BE-NEXT: lxvx v2, r3, r4 2467; P9BE-NEXT: blr 2468; 2469; P9LE-LABEL: fromDiffMemVarAui: 2470; P9LE: # %bb.0: # %entry 2471; P9LE-NEXT: sldi r4, r4, 2 2472; P9LE-NEXT: lxvx v2, r3, r4 2473; P9LE-NEXT: blr 2474; 2475; P8BE-LABEL: fromDiffMemVarAui: 2476; P8BE: # %bb.0: # %entry 2477; P8BE-NEXT: sldi r4, r4, 2 2478; P8BE-NEXT: lxvw4x v2, r3, r4 2479; P8BE-NEXT: blr 2480; 2481; P8LE-LABEL: fromDiffMemVarAui: 2482; P8LE: # %bb.0: # %entry 2483; P8LE-NEXT: sldi r4, r4, 2 2484; P8LE-NEXT: lxvd2x vs0, r3, r4 2485; P8LE-NEXT: xxswapd v2, vs0 2486; P8LE-NEXT: blr 2487entry: 2488 %idxprom = sext i32 %elem to i64 2489 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom 2490 %0 = load i32, ptr %arrayidx, align 4 2491 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2492 %add = add nsw i32 %elem, 1 2493 %idxprom1 = sext i32 %add to i64 2494 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1 2495 %1 = load i32, ptr %arrayidx2, align 4 2496 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2497 %add4 = add nsw i32 %elem, 2 2498 %idxprom5 = sext i32 %add4 to i64 2499 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5 2500 %2 = load i32, ptr %arrayidx6, align 4 2501 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2502 %add8 = add nsw i32 %elem, 3 2503 %idxprom9 = sext i32 %add8 to i64 2504 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9 2505 %3 = load i32, ptr %arrayidx10, align 4 2506 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2507 ret <4 x i32> %vecinit11 2508} 2509 2510define <4 x i32> @fromDiffMemVarDui(ptr nocapture readonly %arr, i32 signext %elem) { 2511; P9BE-LABEL: fromDiffMemVarDui: 2512; P9BE: # %bb.0: # %entry 2513; P9BE-NEXT: sldi r4, r4, 2 2514; P9BE-NEXT: add r3, r3, r4 2515; P9BE-NEXT: li r4, -12 2516; P9BE-NEXT: lxvx v2, r3, r4 2517; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2518; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2519; P9BE-NEXT: lxv vs0, 0(r3) 2520; P9BE-NEXT: xxperm v2, v2, vs0 2521; P9BE-NEXT: blr 2522; 2523; P9LE-LABEL: fromDiffMemVarDui: 2524; P9LE: # %bb.0: # %entry 2525; P9LE-NEXT: sldi r4, r4, 2 2526; P9LE-NEXT: add r3, r3, r4 2527; P9LE-NEXT: li r4, -12 2528; P9LE-NEXT: lxvx v2, r3, r4 2529; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2530; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2531; P9LE-NEXT: lxv vs0, 0(r3) 2532; P9LE-NEXT: xxperm v2, v2, vs0 2533; P9LE-NEXT: blr 2534; 2535; P8BE-LABEL: fromDiffMemVarDui: 2536; P8BE: # %bb.0: # %entry 2537; P8BE-NEXT: sldi r4, r4, 2 2538; P8BE-NEXT: add r3, r3, r4 2539; P8BE-NEXT: addi r3, r3, -12 2540; P8BE-NEXT: lxvw4x v2, 0, r3 2541; P8BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha 2542; P8BE-NEXT: addi r3, r3, .LCPI41_0@toc@l 2543; P8BE-NEXT: lxvw4x v3, 0, r3 2544; P8BE-NEXT: vperm v2, v2, v2, v3 2545; P8BE-NEXT: blr 2546; 2547; P8LE-LABEL: fromDiffMemVarDui: 2548; P8LE: # %bb.0: # %entry 2549; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha 2550; P8LE-NEXT: sldi r4, r4, 2 2551; P8LE-NEXT: addi r5, r5, .LCPI41_0@toc@l 2552; P8LE-NEXT: add r3, r3, r4 2553; P8LE-NEXT: lxvd2x vs0, 0, r5 2554; P8LE-NEXT: addi r3, r3, -12 2555; P8LE-NEXT: lxvd2x v3, 0, r3 2556; P8LE-NEXT: xxswapd v2, vs0 2557; P8LE-NEXT: vperm v2, v3, v3, v2 2558; P8LE-NEXT: blr 2559entry: 2560 %idxprom = sext i32 %elem to i64 2561 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom 2562 %0 = load i32, ptr %arrayidx, align 4 2563 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2564 %sub = add nsw i32 %elem, -1 2565 %idxprom1 = sext i32 %sub to i64 2566 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1 2567 %1 = load i32, ptr %arrayidx2, align 4 2568 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2569 %sub4 = add nsw i32 %elem, -2 2570 %idxprom5 = sext i32 %sub4 to i64 2571 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5 2572 %2 = load i32, ptr %arrayidx6, align 4 2573 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2 2574 %sub8 = add nsw i32 %elem, -3 2575 %idxprom9 = sext i32 %sub8 to i64 2576 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9 2577 %3 = load i32, ptr %arrayidx10, align 4 2578 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3 2579 ret <4 x i32> %vecinit11 2580} 2581 2582define <4 x i32> @fromRandMemConsui(ptr nocapture readonly %arr) { 2583; P9BE-LABEL: fromRandMemConsui: 2584; P9BE: # %bb.0: # %entry 2585; P9BE-NEXT: lwz r4, 16(r3) 2586; P9BE-NEXT: lwz r5, 72(r3) 2587; P9BE-NEXT: lwz r6, 8(r3) 2588; P9BE-NEXT: lwz r3, 352(r3) 2589; P9BE-NEXT: rldimi r3, r6, 32, 0 2590; P9BE-NEXT: rldimi r5, r4, 32, 0 2591; P9BE-NEXT: mtvsrdd v2, r5, r3 2592; P9BE-NEXT: blr 2593; 2594; P9LE-LABEL: fromRandMemConsui: 2595; P9LE: # %bb.0: # %entry 2596; P9LE-NEXT: lwz r4, 16(r3) 2597; P9LE-NEXT: lwz r5, 72(r3) 2598; P9LE-NEXT: lwz r6, 8(r3) 2599; P9LE-NEXT: lwz r3, 352(r3) 2600; P9LE-NEXT: rldimi r4, r5, 32, 0 2601; P9LE-NEXT: rldimi r6, r3, 32, 0 2602; P9LE-NEXT: mtvsrdd v2, r6, r4 2603; P9LE-NEXT: blr 2604; 2605; P8BE-LABEL: fromRandMemConsui: 2606; P8BE: # %bb.0: # %entry 2607; P8BE-NEXT: lwz r4, 16(r3) 2608; P8BE-NEXT: lwz r5, 72(r3) 2609; P8BE-NEXT: lwz r6, 8(r3) 2610; P8BE-NEXT: lwz r3, 352(r3) 2611; P8BE-NEXT: rldimi r3, r6, 32, 0 2612; P8BE-NEXT: rldimi r5, r4, 32, 0 2613; P8BE-NEXT: mtfprd f0, r3 2614; P8BE-NEXT: mtfprd f1, r5 2615; P8BE-NEXT: xxmrghd v2, vs1, vs0 2616; P8BE-NEXT: blr 2617; 2618; P8LE-LABEL: fromRandMemConsui: 2619; P8LE: # %bb.0: # %entry 2620; P8LE-NEXT: lwz r4, 16(r3) 2621; P8LE-NEXT: lwz r5, 72(r3) 2622; P8LE-NEXT: lwz r6, 8(r3) 2623; P8LE-NEXT: lwz r3, 352(r3) 2624; P8LE-NEXT: rldimi r4, r5, 32, 0 2625; P8LE-NEXT: rldimi r6, r3, 32, 0 2626; P8LE-NEXT: mtfprd f0, r4 2627; P8LE-NEXT: mtfprd f1, r6 2628; P8LE-NEXT: xxmrghd v2, vs1, vs0 2629; P8LE-NEXT: blr 2630entry: 2631 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 4 2632 %0 = load i32, ptr %arrayidx, align 4 2633 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2634 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 18 2635 %1 = load i32, ptr %arrayidx1, align 4 2636 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2637 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2 2638 %2 = load i32, ptr %arrayidx3, align 4 2639 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2 2640 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 88 2641 %3 = load i32, ptr %arrayidx5, align 4 2642 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3 2643 ret <4 x i32> %vecinit6 2644} 2645 2646define <4 x i32> @fromRandMemVarui(ptr nocapture readonly %arr, i32 signext %elem) { 2647; P9BE-LABEL: fromRandMemVarui: 2648; P9BE: # %bb.0: # %entry 2649; P9BE-NEXT: sldi r4, r4, 2 2650; P9BE-NEXT: add r3, r3, r4 2651; P9BE-NEXT: lwz r4, 16(r3) 2652; P9BE-NEXT: lwz r5, 4(r3) 2653; P9BE-NEXT: lwz r6, 8(r3) 2654; P9BE-NEXT: lwz r3, 32(r3) 2655; P9BE-NEXT: rldimi r3, r6, 32, 0 2656; P9BE-NEXT: rldimi r5, r4, 32, 0 2657; P9BE-NEXT: mtvsrdd v2, r5, r3 2658; P9BE-NEXT: blr 2659; 2660; P9LE-LABEL: fromRandMemVarui: 2661; P9LE: # %bb.0: # %entry 2662; P9LE-NEXT: sldi r4, r4, 2 2663; P9LE-NEXT: add r3, r3, r4 2664; P9LE-NEXT: lwz r4, 16(r3) 2665; P9LE-NEXT: lwz r5, 4(r3) 2666; P9LE-NEXT: lwz r6, 8(r3) 2667; P9LE-NEXT: lwz r3, 32(r3) 2668; P9LE-NEXT: rldimi r4, r5, 32, 0 2669; P9LE-NEXT: rldimi r6, r3, 32, 0 2670; P9LE-NEXT: mtvsrdd v2, r6, r4 2671; P9LE-NEXT: blr 2672; 2673; P8BE-LABEL: fromRandMemVarui: 2674; P8BE: # %bb.0: # %entry 2675; P8BE-NEXT: sldi r4, r4, 2 2676; P8BE-NEXT: add r3, r3, r4 2677; P8BE-NEXT: lwz r4, 16(r3) 2678; P8BE-NEXT: lwz r5, 4(r3) 2679; P8BE-NEXT: lwz r6, 8(r3) 2680; P8BE-NEXT: lwz r3, 32(r3) 2681; P8BE-NEXT: rldimi r3, r6, 32, 0 2682; P8BE-NEXT: rldimi r5, r4, 32, 0 2683; P8BE-NEXT: mtfprd f0, r3 2684; P8BE-NEXT: mtfprd f1, r5 2685; P8BE-NEXT: xxmrghd v2, vs1, vs0 2686; P8BE-NEXT: blr 2687; 2688; P8LE-LABEL: fromRandMemVarui: 2689; P8LE: # %bb.0: # %entry 2690; P8LE-NEXT: sldi r4, r4, 2 2691; P8LE-NEXT: add r3, r3, r4 2692; P8LE-NEXT: lwz r4, 16(r3) 2693; P8LE-NEXT: lwz r5, 4(r3) 2694; P8LE-NEXT: lwz r6, 8(r3) 2695; P8LE-NEXT: lwz r3, 32(r3) 2696; P8LE-NEXT: rldimi r4, r5, 32, 0 2697; P8LE-NEXT: rldimi r6, r3, 32, 0 2698; P8LE-NEXT: mtfprd f0, r4 2699; P8LE-NEXT: mtfprd f1, r6 2700; P8LE-NEXT: xxmrghd v2, vs1, vs0 2701; P8LE-NEXT: blr 2702entry: 2703 %add = add nsw i32 %elem, 4 2704 %idxprom = sext i32 %add to i64 2705 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom 2706 %0 = load i32, ptr %arrayidx, align 4 2707 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 2708 %add1 = add nsw i32 %elem, 1 2709 %idxprom2 = sext i32 %add1 to i64 2710 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 %idxprom2 2711 %1 = load i32, ptr %arrayidx3, align 4 2712 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1 2713 %add5 = add nsw i32 %elem, 2 2714 %idxprom6 = sext i32 %add5 to i64 2715 %arrayidx7 = getelementptr inbounds i32, ptr %arr, i64 %idxprom6 2716 %2 = load i32, ptr %arrayidx7, align 4 2717 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2 2718 %add9 = add nsw i32 %elem, 8 2719 %idxprom10 = sext i32 %add9 to i64 2720 %arrayidx11 = getelementptr inbounds i32, ptr %arr, i64 %idxprom10 2721 %3 = load i32, ptr %arrayidx11, align 4 2722 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3 2723 ret <4 x i32> %vecinit12 2724} 2725 2726define <4 x i32> @spltRegValui(i32 zeroext %val) { 2727; P9BE-LABEL: spltRegValui: 2728; P9BE: # %bb.0: # %entry 2729; P9BE-NEXT: mtvsrws v2, r3 2730; P9BE-NEXT: blr 2731; 2732; P9LE-LABEL: spltRegValui: 2733; P9LE: # %bb.0: # %entry 2734; P9LE-NEXT: mtvsrws v2, r3 2735; P9LE-NEXT: blr 2736; 2737; P8BE-LABEL: spltRegValui: 2738; P8BE: # %bb.0: # %entry 2739; P8BE-NEXT: mtfprwz f0, r3 2740; P8BE-NEXT: xxspltw v2, vs0, 1 2741; P8BE-NEXT: blr 2742; 2743; P8LE-LABEL: spltRegValui: 2744; P8LE: # %bb.0: # %entry 2745; P8LE-NEXT: mtfprwz f0, r3 2746; P8LE-NEXT: xxspltw v2, vs0, 1 2747; P8LE-NEXT: blr 2748entry: 2749 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 2750 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2751 ret <4 x i32> %splat.splat 2752} 2753 2754define <4 x i32> @spltMemValui(ptr nocapture readonly %ptr) { 2755; P9BE-LABEL: spltMemValui: 2756; P9BE: # %bb.0: # %entry 2757; P9BE-NEXT: lxvwsx v2, 0, r3 2758; P9BE-NEXT: blr 2759; 2760; P9LE-LABEL: spltMemValui: 2761; P9LE: # %bb.0: # %entry 2762; P9LE-NEXT: lxvwsx v2, 0, r3 2763; P9LE-NEXT: blr 2764; 2765; P8BE-LABEL: spltMemValui: 2766; P8BE: # %bb.0: # %entry 2767; P8BE-NEXT: lfiwzx f0, 0, r3 2768; P8BE-NEXT: xxspltw v2, vs0, 1 2769; P8BE-NEXT: blr 2770; 2771; P8LE-LABEL: spltMemValui: 2772; P8LE: # %bb.0: # %entry 2773; P8LE-NEXT: lfiwzx f0, 0, r3 2774; P8LE-NEXT: xxspltw v2, vs0, 1 2775; P8LE-NEXT: blr 2776entry: 2777 %0 = load i32, ptr %ptr, align 4 2778 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 2779 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 2780 ret <4 x i32> %splat.splat 2781} 2782 2783define <4 x i32> @spltCnstConvftoui() { 2784; P9BE-LABEL: spltCnstConvftoui: 2785; P9BE: # %bb.0: # %entry 2786; P9BE-NEXT: vspltisw v2, 4 2787; P9BE-NEXT: blr 2788; 2789; P9LE-LABEL: spltCnstConvftoui: 2790; P9LE: # %bb.0: # %entry 2791; P9LE-NEXT: vspltisw v2, 4 2792; P9LE-NEXT: blr 2793; 2794; P8BE-LABEL: spltCnstConvftoui: 2795; P8BE: # %bb.0: # %entry 2796; P8BE-NEXT: vspltisw v2, 4 2797; P8BE-NEXT: blr 2798; 2799; P8LE-LABEL: spltCnstConvftoui: 2800; P8LE: # %bb.0: # %entry 2801; P8LE-NEXT: vspltisw v2, 4 2802; P8LE-NEXT: blr 2803entry: 2804 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 2805} 2806 2807define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) { 2808; P9BE-LABEL: fromRegsConvftoui: 2809; P9BE: # %bb.0: # %entry 2810; P9BE-NEXT: xxmrghd vs0, vs2, vs4 2811; P9BE-NEXT: xvcvdpuxws v2, vs0 2812; P9BE-NEXT: xxmrghd vs0, vs1, vs3 2813; P9BE-NEXT: xvcvdpuxws v3, vs0 2814; P9BE-NEXT: vmrgew v2, v3, v2 2815; P9BE-NEXT: blr 2816; 2817; P9LE-LABEL: fromRegsConvftoui: 2818; P9LE: # %bb.0: # %entry 2819; P9LE-NEXT: xxmrghd vs0, vs3, vs1 2820; P9LE-NEXT: xvcvdpuxws v2, vs0 2821; P9LE-NEXT: xxmrghd vs0, vs4, vs2 2822; P9LE-NEXT: xvcvdpuxws v3, vs0 2823; P9LE-NEXT: vmrgew v2, v3, v2 2824; P9LE-NEXT: blr 2825; 2826; P8BE-LABEL: fromRegsConvftoui: 2827; P8BE: # %bb.0: # %entry 2828; P8BE-NEXT: xxmrghd vs0, vs2, vs4 2829; P8BE-NEXT: xxmrghd vs1, vs1, vs3 2830; P8BE-NEXT: xvcvdpuxws v2, vs0 2831; P8BE-NEXT: xvcvdpuxws v3, vs1 2832; P8BE-NEXT: vmrgew v2, v3, v2 2833; P8BE-NEXT: blr 2834; 2835; P8LE-LABEL: fromRegsConvftoui: 2836; P8LE: # %bb.0: # %entry 2837; P8LE-NEXT: xxmrghd vs0, vs3, vs1 2838; P8LE-NEXT: xxmrghd vs1, vs4, vs2 2839; P8LE-NEXT: xvcvdpuxws v2, vs0 2840; P8LE-NEXT: xvcvdpuxws v3, vs1 2841; P8LE-NEXT: vmrgew v2, v3, v2 2842; P8LE-NEXT: blr 2843entry: 2844 %conv = fptoui float %a to i32 2845 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2846 %conv1 = fptoui float %b to i32 2847 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 2848 %conv3 = fptoui float %c to i32 2849 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 2850 %conv5 = fptoui float %d to i32 2851 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 2852 ret <4 x i32> %vecinit6 2853} 2854 2855define <4 x i32> @fromDiffConstsConvftoui() { 2856; P9BE-LABEL: fromDiffConstsConvftoui: 2857; P9BE: # %bb.0: # %entry 2858; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2859; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2860; P9BE-NEXT: lxv v2, 0(r3) 2861; P9BE-NEXT: blr 2862; 2863; P9LE-LABEL: fromDiffConstsConvftoui: 2864; P9LE: # %bb.0: # %entry 2865; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2866; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2867; P9LE-NEXT: lxv v2, 0(r3) 2868; P9LE-NEXT: blr 2869; 2870; P8BE-LABEL: fromDiffConstsConvftoui: 2871; P8BE: # %bb.0: # %entry 2872; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2873; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2874; P8BE-NEXT: lxvw4x v2, 0, r3 2875; P8BE-NEXT: blr 2876; 2877; P8LE-LABEL: fromDiffConstsConvftoui: 2878; P8LE: # %bb.0: # %entry 2879; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha 2880; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l 2881; P8LE-NEXT: lxvd2x vs0, 0, r3 2882; P8LE-NEXT: xxswapd v2, vs0 2883; P8LE-NEXT: blr 2884entry: 2885 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 2886} 2887 2888define <4 x i32> @fromDiffMemConsAConvftoui(ptr nocapture readonly %ptr) { 2889; P9BE-LABEL: fromDiffMemConsAConvftoui: 2890; P9BE: # %bb.0: # %entry 2891; P9BE-NEXT: lxv vs0, 0(r3) 2892; P9BE-NEXT: xvcvspuxws v2, vs0 2893; P9BE-NEXT: blr 2894; 2895; P9LE-LABEL: fromDiffMemConsAConvftoui: 2896; P9LE: # %bb.0: # %entry 2897; P9LE-NEXT: lxv vs0, 0(r3) 2898; P9LE-NEXT: xvcvspuxws v2, vs0 2899; P9LE-NEXT: blr 2900; 2901; P8BE-LABEL: fromDiffMemConsAConvftoui: 2902; P8BE: # %bb.0: # %entry 2903; P8BE-NEXT: lxvw4x vs0, 0, r3 2904; P8BE-NEXT: xvcvspuxws v2, vs0 2905; P8BE-NEXT: blr 2906; 2907; P8LE-LABEL: fromDiffMemConsAConvftoui: 2908; P8LE: # %bb.0: # %entry 2909; P8LE-NEXT: lxvd2x vs0, 0, r3 2910; P8LE-NEXT: xxswapd v2, vs0 2911; P8LE-NEXT: xvcvspuxws v2, v2 2912; P8LE-NEXT: blr 2913entry: 2914 %0 = load <4 x float>, ptr %ptr, align 4 2915 %1 = fptoui <4 x float> %0 to <4 x i32> 2916 ret <4 x i32> %1 2917} 2918 2919define <4 x i32> @fromDiffMemConsDConvftoui(ptr nocapture readonly %ptr) { 2920; P9BE-LABEL: fromDiffMemConsDConvftoui: 2921; P9BE: # %bb.0: # %entry 2922; P9BE-NEXT: lxv vs0, 0(r3) 2923; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 2924; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 2925; P9BE-NEXT: lxv vs1, 0(r3) 2926; P9BE-NEXT: xxperm vs0, vs0, vs1 2927; P9BE-NEXT: xvcvspuxws v2, vs0 2928; P9BE-NEXT: blr 2929; 2930; P9LE-LABEL: fromDiffMemConsDConvftoui: 2931; P9LE: # %bb.0: # %entry 2932; P9LE-NEXT: lxv vs0, 0(r3) 2933; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 2934; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l 2935; P9LE-NEXT: lxv vs1, 0(r3) 2936; P9LE-NEXT: xxperm vs0, vs0, vs1 2937; P9LE-NEXT: xvcvspuxws v2, vs0 2938; P9LE-NEXT: blr 2939; 2940; P8BE-LABEL: fromDiffMemConsDConvftoui: 2941; P8BE: # %bb.0: # %entry 2942; P8BE-NEXT: lxvw4x v2, 0, r3 2943; P8BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha 2944; P8BE-NEXT: addi r3, r3, .LCPI50_0@toc@l 2945; P8BE-NEXT: lxvw4x v3, 0, r3 2946; P8BE-NEXT: vperm v2, v2, v2, v3 2947; P8BE-NEXT: xvcvspuxws v2, v2 2948; P8BE-NEXT: blr 2949; 2950; P8LE-LABEL: fromDiffMemConsDConvftoui: 2951; P8LE: # %bb.0: # %entry 2952; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha 2953; P8LE-NEXT: lxvd2x v3, 0, r3 2954; P8LE-NEXT: addi r4, r4, .LCPI50_0@toc@l 2955; P8LE-NEXT: lxvd2x vs0, 0, r4 2956; P8LE-NEXT: xxswapd v2, vs0 2957; P8LE-NEXT: vperm v2, v3, v3, v2 2958; P8LE-NEXT: xvcvspuxws v2, v2 2959; P8LE-NEXT: blr 2960entry: 2961 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3 2962 %0 = load float, ptr %arrayidx, align 4 2963 %conv = fptoui float %0 to i32 2964 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 2965 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2 2966 %1 = load float, ptr %arrayidx1, align 4 2967 %conv2 = fptoui float %1 to i32 2968 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 2969 %arrayidx4 = getelementptr inbounds float, ptr %ptr, i64 1 2970 %2 = load float, ptr %arrayidx4, align 4 2971 %conv5 = fptoui float %2 to i32 2972 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 2973 %3 = load float, ptr %ptr, align 4 2974 %conv8 = fptoui float %3 to i32 2975 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 2976 ret <4 x i32> %vecinit9 2977} 2978 2979define <4 x i32> @fromDiffMemVarAConvftoui(ptr nocapture readonly %arr, i32 signext %elem) { 2980; P9BE-LABEL: fromDiffMemVarAConvftoui: 2981; P9BE: # %bb.0: # %entry 2982; P9BE-NEXT: sldi r4, r4, 2 2983; P9BE-NEXT: lfsux f0, r3, r4 2984; P9BE-NEXT: lfs f1, 12(r3) 2985; P9BE-NEXT: lfs f2, 4(r3) 2986; P9BE-NEXT: xxmrghd vs1, vs2, vs1 2987; P9BE-NEXT: xvcvdpsp v2, vs1 2988; P9BE-NEXT: lfs f1, 8(r3) 2989; P9BE-NEXT: xxmrghd vs0, vs0, vs1 2990; P9BE-NEXT: xvcvdpsp v3, vs0 2991; P9BE-NEXT: vmrgew v2, v3, v2 2992; P9BE-NEXT: xvcvspuxws v2, v2 2993; P9BE-NEXT: blr 2994; 2995; P9LE-LABEL: fromDiffMemVarAConvftoui: 2996; P9LE: # %bb.0: # %entry 2997; P9LE-NEXT: sldi r4, r4, 2 2998; P9LE-NEXT: lfsux f0, r3, r4 2999; P9LE-NEXT: lfs f1, 8(r3) 3000; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3001; P9LE-NEXT: lfs f1, 12(r3) 3002; P9LE-NEXT: xvcvdpsp v2, vs0 3003; P9LE-NEXT: lfs f0, 4(r3) 3004; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3005; P9LE-NEXT: xvcvdpsp v3, vs0 3006; P9LE-NEXT: vmrgew v2, v3, v2 3007; P9LE-NEXT: xvcvspuxws v2, v2 3008; P9LE-NEXT: blr 3009; 3010; P8BE-LABEL: fromDiffMemVarAConvftoui: 3011; P8BE: # %bb.0: # %entry 3012; P8BE-NEXT: sldi r4, r4, 2 3013; P8BE-NEXT: lfsux f0, r3, r4 3014; P8BE-NEXT: lfs f1, 12(r3) 3015; P8BE-NEXT: lfs f2, 4(r3) 3016; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3017; P8BE-NEXT: lfs f2, 8(r3) 3018; P8BE-NEXT: xvcvdpsp v2, vs1 3019; P8BE-NEXT: xxmrghd vs0, vs0, vs2 3020; P8BE-NEXT: xvcvdpsp v3, vs0 3021; P8BE-NEXT: vmrgew v2, v3, v2 3022; P8BE-NEXT: xvcvspuxws v2, v2 3023; P8BE-NEXT: blr 3024; 3025; P8LE-LABEL: fromDiffMemVarAConvftoui: 3026; P8LE: # %bb.0: # %entry 3027; P8LE-NEXT: sldi r4, r4, 2 3028; P8LE-NEXT: lfsux f0, r3, r4 3029; P8LE-NEXT: lfs f1, 8(r3) 3030; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3031; P8LE-NEXT: lfs f1, 4(r3) 3032; P8LE-NEXT: lfs f2, 12(r3) 3033; P8LE-NEXT: xvcvdpsp v2, vs0 3034; P8LE-NEXT: xxmrghd vs1, vs2, vs1 3035; P8LE-NEXT: xvcvdpsp v3, vs1 3036; P8LE-NEXT: vmrgew v2, v3, v2 3037; P8LE-NEXT: xvcvspuxws v2, v2 3038; P8LE-NEXT: blr 3039entry: 3040 %idxprom = sext i32 %elem to i64 3041 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom 3042 %0 = load float, ptr %arrayidx, align 4 3043 %conv = fptoui float %0 to i32 3044 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3045 %add = add nsw i32 %elem, 1 3046 %idxprom1 = sext i32 %add to i64 3047 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1 3048 %1 = load float, ptr %arrayidx2, align 4 3049 %conv3 = fptoui float %1 to i32 3050 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3051 %add5 = add nsw i32 %elem, 2 3052 %idxprom6 = sext i32 %add5 to i64 3053 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6 3054 %2 = load float, ptr %arrayidx7, align 4 3055 %conv8 = fptoui float %2 to i32 3056 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3057 %add10 = add nsw i32 %elem, 3 3058 %idxprom11 = sext i32 %add10 to i64 3059 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11 3060 %3 = load float, ptr %arrayidx12, align 4 3061 %conv13 = fptoui float %3 to i32 3062 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3063 ret <4 x i32> %vecinit14 3064; FIXME: implement finding consecutive loads with pre-inc 3065} 3066 3067define <4 x i32> @fromDiffMemVarDConvftoui(ptr nocapture readonly %arr, i32 signext %elem) { 3068; P9BE-LABEL: fromDiffMemVarDConvftoui: 3069; P9BE: # %bb.0: # %entry 3070; P9BE-NEXT: sldi r4, r4, 2 3071; P9BE-NEXT: lfsux f0, r3, r4 3072; P9BE-NEXT: lfs f1, -12(r3) 3073; P9BE-NEXT: lfs f2, -4(r3) 3074; P9BE-NEXT: xxmrghd vs1, vs2, vs1 3075; P9BE-NEXT: xvcvdpsp v2, vs1 3076; P9BE-NEXT: lfs f1, -8(r3) 3077; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3078; P9BE-NEXT: xvcvdpsp v3, vs0 3079; P9BE-NEXT: vmrgew v2, v3, v2 3080; P9BE-NEXT: xvcvspuxws v2, v2 3081; P9BE-NEXT: blr 3082; 3083; P9LE-LABEL: fromDiffMemVarDConvftoui: 3084; P9LE: # %bb.0: # %entry 3085; P9LE-NEXT: sldi r4, r4, 2 3086; P9LE-NEXT: lfsux f0, r3, r4 3087; P9LE-NEXT: lfs f1, -8(r3) 3088; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3089; P9LE-NEXT: lfs f1, -12(r3) 3090; P9LE-NEXT: xvcvdpsp v2, vs0 3091; P9LE-NEXT: lfs f0, -4(r3) 3092; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3093; P9LE-NEXT: xvcvdpsp v3, vs0 3094; P9LE-NEXT: vmrgew v2, v3, v2 3095; P9LE-NEXT: xvcvspuxws v2, v2 3096; P9LE-NEXT: blr 3097; 3098; P8BE-LABEL: fromDiffMemVarDConvftoui: 3099; P8BE: # %bb.0: # %entry 3100; P8BE-NEXT: sldi r4, r4, 2 3101; P8BE-NEXT: lfsux f0, r3, r4 3102; P8BE-NEXT: lfs f1, -12(r3) 3103; P8BE-NEXT: lfs f2, -4(r3) 3104; P8BE-NEXT: xxmrghd vs1, vs2, vs1 3105; P8BE-NEXT: lfs f2, -8(r3) 3106; P8BE-NEXT: xvcvdpsp v2, vs1 3107; P8BE-NEXT: xxmrghd vs0, vs0, vs2 3108; P8BE-NEXT: xvcvdpsp v3, vs0 3109; P8BE-NEXT: vmrgew v2, v3, v2 3110; P8BE-NEXT: xvcvspuxws v2, v2 3111; P8BE-NEXT: blr 3112; 3113; P8LE-LABEL: fromDiffMemVarDConvftoui: 3114; P8LE: # %bb.0: # %entry 3115; P8LE-NEXT: sldi r4, r4, 2 3116; P8LE-NEXT: lfsux f0, r3, r4 3117; P8LE-NEXT: lfs f1, -8(r3) 3118; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3119; P8LE-NEXT: lfs f1, -4(r3) 3120; P8LE-NEXT: lfs f2, -12(r3) 3121; P8LE-NEXT: xvcvdpsp v2, vs0 3122; P8LE-NEXT: xxmrghd vs1, vs2, vs1 3123; P8LE-NEXT: xvcvdpsp v3, vs1 3124; P8LE-NEXT: vmrgew v2, v3, v2 3125; P8LE-NEXT: xvcvspuxws v2, v2 3126; P8LE-NEXT: blr 3127entry: 3128 %idxprom = sext i32 %elem to i64 3129 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom 3130 %0 = load float, ptr %arrayidx, align 4 3131 %conv = fptoui float %0 to i32 3132 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3133 %sub = add nsw i32 %elem, -1 3134 %idxprom1 = sext i32 %sub to i64 3135 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1 3136 %1 = load float, ptr %arrayidx2, align 4 3137 %conv3 = fptoui float %1 to i32 3138 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3139 %sub5 = add nsw i32 %elem, -2 3140 %idxprom6 = sext i32 %sub5 to i64 3141 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6 3142 %2 = load float, ptr %arrayidx7, align 4 3143 %conv8 = fptoui float %2 to i32 3144 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3145 %sub10 = add nsw i32 %elem, -3 3146 %idxprom11 = sext i32 %sub10 to i64 3147 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11 3148 %3 = load float, ptr %arrayidx12, align 4 3149 %conv13 = fptoui float %3 to i32 3150 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3151 ret <4 x i32> %vecinit14 3152; FIXME: implement finding consecutive loads with pre-inc 3153} 3154 3155define <4 x i32> @spltRegValConvftoui(float %val) { 3156; P9BE-LABEL: spltRegValConvftoui: 3157; P9BE: # %bb.0: # %entry 3158; P9BE-NEXT: xscvdpuxws f0, f1 3159; P9BE-NEXT: xxspltw v2, vs0, 1 3160; P9BE-NEXT: blr 3161; 3162; P9LE-LABEL: spltRegValConvftoui: 3163; P9LE: # %bb.0: # %entry 3164; P9LE-NEXT: xscvdpuxws f0, f1 3165; P9LE-NEXT: xxspltw v2, vs0, 1 3166; P9LE-NEXT: blr 3167; 3168; P8BE-LABEL: spltRegValConvftoui: 3169; P8BE: # %bb.0: # %entry 3170; P8BE-NEXT: xscvdpuxws f0, f1 3171; P8BE-NEXT: xxspltw v2, vs0, 1 3172; P8BE-NEXT: blr 3173; 3174; P8LE-LABEL: spltRegValConvftoui: 3175; P8LE: # %bb.0: # %entry 3176; P8LE-NEXT: xscvdpuxws f0, f1 3177; P8LE-NEXT: xxspltw v2, vs0, 1 3178; P8LE-NEXT: blr 3179entry: 3180 %conv = fptoui float %val to i32 3181 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3182 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3183 ret <4 x i32> %splat.splat 3184} 3185 3186define <4 x i32> @spltMemValConvftoui(ptr nocapture readonly %ptr) { 3187; P9BE-LABEL: spltMemValConvftoui: 3188; P9BE: # %bb.0: # %entry 3189; P9BE-NEXT: lfiwzx f0, 0, r3 3190; P9BE-NEXT: xvcvspuxws vs0, vs0 3191; P9BE-NEXT: xxspltw v2, vs0, 1 3192; P9BE-NEXT: blr 3193; 3194; P9LE-LABEL: spltMemValConvftoui: 3195; P9LE: # %bb.0: # %entry 3196; P9LE-NEXT: lfiwzx f0, 0, r3 3197; P9LE-NEXT: xvcvspuxws vs0, vs0 3198; P9LE-NEXT: xxspltw v2, vs0, 1 3199; P9LE-NEXT: blr 3200; 3201; P8BE-LABEL: spltMemValConvftoui: 3202; P8BE: # %bb.0: # %entry 3203; P8BE-NEXT: lfsx f0, 0, r3 3204; P8BE-NEXT: xscvdpuxws f0, f0 3205; P8BE-NEXT: xxspltw v2, vs0, 1 3206; P8BE-NEXT: blr 3207; 3208; P8LE-LABEL: spltMemValConvftoui: 3209; P8LE: # %bb.0: # %entry 3210; P8LE-NEXT: lfsx f0, 0, r3 3211; P8LE-NEXT: xscvdpuxws f0, f0 3212; P8LE-NEXT: xxspltw v2, vs0, 1 3213; P8LE-NEXT: blr 3214entry: 3215 %0 = load float, ptr %ptr, align 4 3216 %conv = fptoui float %0 to i32 3217 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3218 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3219 ret <4 x i32> %splat.splat 3220} 3221 3222define <4 x i32> @spltCnstConvdtoui() { 3223; P9BE-LABEL: spltCnstConvdtoui: 3224; P9BE: # %bb.0: # %entry 3225; P9BE-NEXT: vspltisw v2, 4 3226; P9BE-NEXT: blr 3227; 3228; P9LE-LABEL: spltCnstConvdtoui: 3229; P9LE: # %bb.0: # %entry 3230; P9LE-NEXT: vspltisw v2, 4 3231; P9LE-NEXT: blr 3232; 3233; P8BE-LABEL: spltCnstConvdtoui: 3234; P8BE: # %bb.0: # %entry 3235; P8BE-NEXT: vspltisw v2, 4 3236; P8BE-NEXT: blr 3237; 3238; P8LE-LABEL: spltCnstConvdtoui: 3239; P8LE: # %bb.0: # %entry 3240; P8LE-NEXT: vspltisw v2, 4 3241; P8LE-NEXT: blr 3242entry: 3243 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4> 3244} 3245 3246define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) { 3247; P9BE-LABEL: fromRegsConvdtoui: 3248; P9BE: # %bb.0: # %entry 3249; P9BE-NEXT: xxmrghd vs0, vs2, vs4 3250; P9BE-NEXT: xvcvdpuxws v2, vs0 3251; P9BE-NEXT: xxmrghd vs0, vs1, vs3 3252; P9BE-NEXT: xvcvdpuxws v3, vs0 3253; P9BE-NEXT: vmrgew v2, v3, v2 3254; P9BE-NEXT: blr 3255; 3256; P9LE-LABEL: fromRegsConvdtoui: 3257; P9LE: # %bb.0: # %entry 3258; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3259; P9LE-NEXT: xvcvdpuxws v2, vs0 3260; P9LE-NEXT: xxmrghd vs0, vs4, vs2 3261; P9LE-NEXT: xvcvdpuxws v3, vs0 3262; P9LE-NEXT: vmrgew v2, v3, v2 3263; P9LE-NEXT: blr 3264; 3265; P8BE-LABEL: fromRegsConvdtoui: 3266; P8BE: # %bb.0: # %entry 3267; P8BE-NEXT: xxmrghd vs0, vs2, vs4 3268; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3269; P8BE-NEXT: xvcvdpuxws v2, vs0 3270; P8BE-NEXT: xvcvdpuxws v3, vs1 3271; P8BE-NEXT: vmrgew v2, v3, v2 3272; P8BE-NEXT: blr 3273; 3274; P8LE-LABEL: fromRegsConvdtoui: 3275; P8LE: # %bb.0: # %entry 3276; P8LE-NEXT: xxmrghd vs0, vs3, vs1 3277; P8LE-NEXT: xxmrghd vs1, vs4, vs2 3278; P8LE-NEXT: xvcvdpuxws v2, vs0 3279; P8LE-NEXT: xvcvdpuxws v3, vs1 3280; P8LE-NEXT: vmrgew v2, v3, v2 3281; P8LE-NEXT: blr 3282entry: 3283 %conv = fptoui double %a to i32 3284 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3285 %conv1 = fptoui double %b to i32 3286 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1 3287 %conv3 = fptoui double %c to i32 3288 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2 3289 %conv5 = fptoui double %d to i32 3290 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3 3291 ret <4 x i32> %vecinit6 3292} 3293 3294define <4 x i32> @fromDiffConstsConvdtoui() { 3295; P9BE-LABEL: fromDiffConstsConvdtoui: 3296; P9BE: # %bb.0: # %entry 3297; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3298; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3299; P9BE-NEXT: lxv v2, 0(r3) 3300; P9BE-NEXT: blr 3301; 3302; P9LE-LABEL: fromDiffConstsConvdtoui: 3303; P9LE: # %bb.0: # %entry 3304; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3305; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3306; P9LE-NEXT: lxv v2, 0(r3) 3307; P9LE-NEXT: blr 3308; 3309; P8BE-LABEL: fromDiffConstsConvdtoui: 3310; P8BE: # %bb.0: # %entry 3311; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3312; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3313; P8BE-NEXT: lxvw4x v2, 0, r3 3314; P8BE-NEXT: blr 3315; 3316; P8LE-LABEL: fromDiffConstsConvdtoui: 3317; P8LE: # %bb.0: # %entry 3318; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha 3319; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l 3320; P8LE-NEXT: lxvd2x vs0, 0, r3 3321; P8LE-NEXT: xxswapd v2, vs0 3322; P8LE-NEXT: blr 3323entry: 3324 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422> 3325} 3326 3327define <4 x i32> @fromDiffMemConsAConvdtoui(ptr nocapture readonly %ptr) { 3328; P9BE-LABEL: fromDiffMemConsAConvdtoui: 3329; P9BE: # %bb.0: # %entry 3330; P9BE-NEXT: lxv vs0, 0(r3) 3331; P9BE-NEXT: lxv vs1, 16(r3) 3332; P9BE-NEXT: xxmrgld vs2, vs0, vs1 3333; P9BE-NEXT: xxmrghd vs0, vs0, vs1 3334; P9BE-NEXT: xvcvdpuxws v2, vs2 3335; P9BE-NEXT: xvcvdpuxws v3, vs0 3336; P9BE-NEXT: vmrgew v2, v3, v2 3337; P9BE-NEXT: blr 3338; 3339; P9LE-LABEL: fromDiffMemConsAConvdtoui: 3340; P9LE: # %bb.0: # %entry 3341; P9LE-NEXT: lxv vs0, 0(r3) 3342; P9LE-NEXT: lxv vs1, 16(r3) 3343; P9LE-NEXT: xxmrgld vs2, vs1, vs0 3344; P9LE-NEXT: xxmrghd vs0, vs1, vs0 3345; P9LE-NEXT: xvcvdpuxws v2, vs2 3346; P9LE-NEXT: xvcvdpuxws v3, vs0 3347; P9LE-NEXT: vmrgew v2, v3, v2 3348; P9LE-NEXT: blr 3349; 3350; P8BE-LABEL: fromDiffMemConsAConvdtoui: 3351; P8BE: # %bb.0: # %entry 3352; P8BE-NEXT: li r4, 16 3353; P8BE-NEXT: lxvd2x vs0, 0, r3 3354; P8BE-NEXT: lxvd2x vs1, r3, r4 3355; P8BE-NEXT: xxmrgld vs2, vs0, vs1 3356; P8BE-NEXT: xxmrghd vs0, vs0, vs1 3357; P8BE-NEXT: xvcvdpuxws v2, vs2 3358; P8BE-NEXT: xvcvdpuxws v3, vs0 3359; P8BE-NEXT: vmrgew v2, v3, v2 3360; P8BE-NEXT: blr 3361; 3362; P8LE-LABEL: fromDiffMemConsAConvdtoui: 3363; P8LE: # %bb.0: # %entry 3364; P8LE-NEXT: li r4, 16 3365; P8LE-NEXT: lxvd2x vs0, 0, r3 3366; P8LE-NEXT: lxvd2x vs1, r3, r4 3367; P8LE-NEXT: xxswapd vs0, vs0 3368; P8LE-NEXT: xxswapd vs1, vs1 3369; P8LE-NEXT: xxmrgld vs2, vs1, vs0 3370; P8LE-NEXT: xxmrghd vs0, vs1, vs0 3371; P8LE-NEXT: xvcvdpuxws v2, vs2 3372; P8LE-NEXT: xvcvdpuxws v3, vs0 3373; P8LE-NEXT: vmrgew v2, v3, v2 3374; P8LE-NEXT: blr 3375entry: 3376 %0 = load <2 x double>, ptr %ptr, align 8 3377 %1 = fptoui <2 x double> %0 to <2 x i32> 3378 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 2 3379 %2 = load <2 x double>, ptr %arrayidx4, align 8 3380 %3 = fptoui <2 x double> %2 to <2 x i32> 3381 %vecinit9 = shufflevector <2 x i32> %1, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 3382 ret <4 x i32> %vecinit9 3383} 3384 3385define <4 x i32> @fromDiffMemConsDConvdtoui(ptr nocapture readonly %ptr) { 3386; P9BE-LABEL: fromDiffMemConsDConvdtoui: 3387; P9BE: # %bb.0: # %entry 3388; P9BE-NEXT: lfd f0, 24(r3) 3389; P9BE-NEXT: lfd f1, 16(r3) 3390; P9BE-NEXT: lfd f2, 8(r3) 3391; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3392; P9BE-NEXT: lfd f3, 0(r3) 3393; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3394; P9BE-NEXT: xvcvdpuxws v2, vs1 3395; P9BE-NEXT: xvcvdpuxws v3, vs0 3396; P9BE-NEXT: vmrgew v2, v3, v2 3397; P9BE-NEXT: blr 3398; 3399; P9LE-LABEL: fromDiffMemConsDConvdtoui: 3400; P9LE: # %bb.0: # %entry 3401; P9LE-NEXT: lfd f0, 24(r3) 3402; P9LE-NEXT: lfd f2, 8(r3) 3403; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3404; P9LE-NEXT: lfd f1, 16(r3) 3405; P9LE-NEXT: lfd f3, 0(r3) 3406; P9LE-NEXT: xvcvdpuxws v2, vs0 3407; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3408; P9LE-NEXT: xvcvdpuxws v3, vs0 3409; P9LE-NEXT: vmrgew v2, v3, v2 3410; P9LE-NEXT: blr 3411; 3412; P8BE-LABEL: fromDiffMemConsDConvdtoui: 3413; P8BE: # %bb.0: # %entry 3414; P8BE-NEXT: lfd f0, 24(r3) 3415; P8BE-NEXT: lfd f1, 16(r3) 3416; P8BE-NEXT: lfd f2, 8(r3) 3417; P8BE-NEXT: lfd f3, 0(r3) 3418; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3419; P8BE-NEXT: xxmrghd vs0, vs0, vs2 3420; P8BE-NEXT: xvcvdpuxws v2, vs1 3421; P8BE-NEXT: xvcvdpuxws v3, vs0 3422; P8BE-NEXT: vmrgew v2, v3, v2 3423; P8BE-NEXT: blr 3424; 3425; P8LE-LABEL: fromDiffMemConsDConvdtoui: 3426; P8LE: # %bb.0: # %entry 3427; P8LE-NEXT: lfd f0, 24(r3) 3428; P8LE-NEXT: lfd f1, 16(r3) 3429; P8LE-NEXT: lfd f2, 8(r3) 3430; P8LE-NEXT: lfd f3, 0(r3) 3431; P8LE-NEXT: xxmrghd vs0, vs2, vs0 3432; P8LE-NEXT: xxmrghd vs1, vs3, vs1 3433; P8LE-NEXT: xvcvdpuxws v2, vs0 3434; P8LE-NEXT: xvcvdpuxws v3, vs1 3435; P8LE-NEXT: vmrgew v2, v3, v2 3436; P8LE-NEXT: blr 3437entry: 3438 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3 3439 %0 = load double, ptr %arrayidx, align 8 3440 %conv = fptoui double %0 to i32 3441 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3442 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2 3443 %1 = load double, ptr %arrayidx1, align 8 3444 %conv2 = fptoui double %1 to i32 3445 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1 3446 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 1 3447 %2 = load double, ptr %arrayidx4, align 8 3448 %conv5 = fptoui double %2 to i32 3449 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2 3450 %3 = load double, ptr %ptr, align 8 3451 %conv8 = fptoui double %3 to i32 3452 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3 3453 ret <4 x i32> %vecinit9 3454} 3455 3456define <4 x i32> @fromDiffMemVarAConvdtoui(ptr nocapture readonly %arr, i32 signext %elem) { 3457; P9BE-LABEL: fromDiffMemVarAConvdtoui: 3458; P9BE: # %bb.0: # %entry 3459; P9BE-NEXT: sldi r4, r4, 3 3460; P9BE-NEXT: lfdux f0, r3, r4 3461; P9BE-NEXT: lfd f1, 8(r3) 3462; P9BE-NEXT: lfd f2, 16(r3) 3463; P9BE-NEXT: lfd f3, 24(r3) 3464; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3465; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3466; P9BE-NEXT: xvcvdpuxws v2, vs1 3467; P9BE-NEXT: xvcvdpuxws v3, vs0 3468; P9BE-NEXT: vmrgew v2, v3, v2 3469; P9BE-NEXT: blr 3470; 3471; P9LE-LABEL: fromDiffMemVarAConvdtoui: 3472; P9LE: # %bb.0: # %entry 3473; P9LE-NEXT: sldi r4, r4, 3 3474; P9LE-NEXT: lfdux f0, r3, r4 3475; P9LE-NEXT: lfd f2, 16(r3) 3476; P9LE-NEXT: lfd f1, 8(r3) 3477; P9LE-NEXT: lfd f3, 24(r3) 3478; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3479; P9LE-NEXT: xvcvdpuxws v2, vs0 3480; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3481; P9LE-NEXT: xvcvdpuxws v3, vs0 3482; P9LE-NEXT: vmrgew v2, v3, v2 3483; P9LE-NEXT: blr 3484; 3485; P8BE-LABEL: fromDiffMemVarAConvdtoui: 3486; P8BE: # %bb.0: # %entry 3487; P8BE-NEXT: sldi r4, r4, 3 3488; P8BE-NEXT: lfdux f0, r3, r4 3489; P8BE-NEXT: lfd f1, 8(r3) 3490; P8BE-NEXT: lfd f2, 16(r3) 3491; P8BE-NEXT: lfd f3, 24(r3) 3492; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3493; P8BE-NEXT: xxmrghd vs0, vs0, vs2 3494; P8BE-NEXT: xvcvdpuxws v2, vs1 3495; P8BE-NEXT: xvcvdpuxws v3, vs0 3496; P8BE-NEXT: vmrgew v2, v3, v2 3497; P8BE-NEXT: blr 3498; 3499; P8LE-LABEL: fromDiffMemVarAConvdtoui: 3500; P8LE: # %bb.0: # %entry 3501; P8LE-NEXT: sldi r4, r4, 3 3502; P8LE-NEXT: lfdux f0, r3, r4 3503; P8LE-NEXT: lfd f1, 8(r3) 3504; P8LE-NEXT: lfd f2, 16(r3) 3505; P8LE-NEXT: lfd f3, 24(r3) 3506; P8LE-NEXT: xxmrghd vs0, vs2, vs0 3507; P8LE-NEXT: xxmrghd vs1, vs3, vs1 3508; P8LE-NEXT: xvcvdpuxws v2, vs0 3509; P8LE-NEXT: xvcvdpuxws v3, vs1 3510; P8LE-NEXT: vmrgew v2, v3, v2 3511; P8LE-NEXT: blr 3512entry: 3513 %idxprom = sext i32 %elem to i64 3514 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom 3515 %0 = load double, ptr %arrayidx, align 8 3516 %conv = fptoui double %0 to i32 3517 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3518 %add = add nsw i32 %elem, 1 3519 %idxprom1 = sext i32 %add to i64 3520 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1 3521 %1 = load double, ptr %arrayidx2, align 8 3522 %conv3 = fptoui double %1 to i32 3523 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3524 %add5 = add nsw i32 %elem, 2 3525 %idxprom6 = sext i32 %add5 to i64 3526 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6 3527 %2 = load double, ptr %arrayidx7, align 8 3528 %conv8 = fptoui double %2 to i32 3529 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3530 %add10 = add nsw i32 %elem, 3 3531 %idxprom11 = sext i32 %add10 to i64 3532 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11 3533 %3 = load double, ptr %arrayidx12, align 8 3534 %conv13 = fptoui double %3 to i32 3535 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3536 ret <4 x i32> %vecinit14 3537} 3538 3539define <4 x i32> @fromDiffMemVarDConvdtoui(ptr nocapture readonly %arr, i32 signext %elem) { 3540; P9BE-LABEL: fromDiffMemVarDConvdtoui: 3541; P9BE: # %bb.0: # %entry 3542; P9BE-NEXT: sldi r4, r4, 3 3543; P9BE-NEXT: lfdux f0, r3, r4 3544; P9BE-NEXT: lfd f1, -8(r3) 3545; P9BE-NEXT: lfd f2, -16(r3) 3546; P9BE-NEXT: lfd f3, -24(r3) 3547; P9BE-NEXT: xxmrghd vs1, vs1, vs3 3548; P9BE-NEXT: xxmrghd vs0, vs0, vs2 3549; P9BE-NEXT: xvcvdpuxws v2, vs1 3550; P9BE-NEXT: xvcvdpuxws v3, vs0 3551; P9BE-NEXT: vmrgew v2, v3, v2 3552; P9BE-NEXT: blr 3553; 3554; P9LE-LABEL: fromDiffMemVarDConvdtoui: 3555; P9LE: # %bb.0: # %entry 3556; P9LE-NEXT: sldi r4, r4, 3 3557; P9LE-NEXT: lfdux f0, r3, r4 3558; P9LE-NEXT: lfd f2, -16(r3) 3559; P9LE-NEXT: lfd f1, -8(r3) 3560; P9LE-NEXT: lfd f3, -24(r3) 3561; P9LE-NEXT: xxmrghd vs0, vs2, vs0 3562; P9LE-NEXT: xvcvdpuxws v2, vs0 3563; P9LE-NEXT: xxmrghd vs0, vs3, vs1 3564; P9LE-NEXT: xvcvdpuxws v3, vs0 3565; P9LE-NEXT: vmrgew v2, v3, v2 3566; P9LE-NEXT: blr 3567; 3568; P8BE-LABEL: fromDiffMemVarDConvdtoui: 3569; P8BE: # %bb.0: # %entry 3570; P8BE-NEXT: sldi r4, r4, 3 3571; P8BE-NEXT: lfdux f0, r3, r4 3572; P8BE-NEXT: lfd f1, -8(r3) 3573; P8BE-NEXT: lfd f2, -16(r3) 3574; P8BE-NEXT: lfd f3, -24(r3) 3575; P8BE-NEXT: xxmrghd vs1, vs1, vs3 3576; P8BE-NEXT: xxmrghd vs0, vs0, vs2 3577; P8BE-NEXT: xvcvdpuxws v2, vs1 3578; P8BE-NEXT: xvcvdpuxws v3, vs0 3579; P8BE-NEXT: vmrgew v2, v3, v2 3580; P8BE-NEXT: blr 3581; 3582; P8LE-LABEL: fromDiffMemVarDConvdtoui: 3583; P8LE: # %bb.0: # %entry 3584; P8LE-NEXT: sldi r4, r4, 3 3585; P8LE-NEXT: lfdux f0, r3, r4 3586; P8LE-NEXT: lfd f1, -8(r3) 3587; P8LE-NEXT: lfd f2, -16(r3) 3588; P8LE-NEXT: lfd f3, -24(r3) 3589; P8LE-NEXT: xxmrghd vs0, vs2, vs0 3590; P8LE-NEXT: xxmrghd vs1, vs3, vs1 3591; P8LE-NEXT: xvcvdpuxws v2, vs0 3592; P8LE-NEXT: xvcvdpuxws v3, vs1 3593; P8LE-NEXT: vmrgew v2, v3, v2 3594; P8LE-NEXT: blr 3595entry: 3596 %idxprom = sext i32 %elem to i64 3597 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom 3598 %0 = load double, ptr %arrayidx, align 8 3599 %conv = fptoui double %0 to i32 3600 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0 3601 %sub = add nsw i32 %elem, -1 3602 %idxprom1 = sext i32 %sub to i64 3603 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1 3604 %1 = load double, ptr %arrayidx2, align 8 3605 %conv3 = fptoui double %1 to i32 3606 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1 3607 %sub5 = add nsw i32 %elem, -2 3608 %idxprom6 = sext i32 %sub5 to i64 3609 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6 3610 %2 = load double, ptr %arrayidx7, align 8 3611 %conv8 = fptoui double %2 to i32 3612 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2 3613 %sub10 = add nsw i32 %elem, -3 3614 %idxprom11 = sext i32 %sub10 to i64 3615 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11 3616 %3 = load double, ptr %arrayidx12, align 8 3617 %conv13 = fptoui double %3 to i32 3618 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3 3619 ret <4 x i32> %vecinit14 3620} 3621 3622define <4 x i32> @spltRegValConvdtoui(double %val) { 3623; P9BE-LABEL: spltRegValConvdtoui: 3624; P9BE: # %bb.0: # %entry 3625; P9BE-NEXT: xscvdpuxws f0, f1 3626; P9BE-NEXT: xxspltw v2, vs0, 1 3627; P9BE-NEXT: blr 3628; 3629; P9LE-LABEL: spltRegValConvdtoui: 3630; P9LE: # %bb.0: # %entry 3631; P9LE-NEXT: xscvdpuxws f0, f1 3632; P9LE-NEXT: xxspltw v2, vs0, 1 3633; P9LE-NEXT: blr 3634; 3635; P8BE-LABEL: spltRegValConvdtoui: 3636; P8BE: # %bb.0: # %entry 3637; P8BE-NEXT: xscvdpuxws f0, f1 3638; P8BE-NEXT: xxspltw v2, vs0, 1 3639; P8BE-NEXT: blr 3640; 3641; P8LE-LABEL: spltRegValConvdtoui: 3642; P8LE: # %bb.0: # %entry 3643; P8LE-NEXT: xscvdpuxws f0, f1 3644; P8LE-NEXT: xxspltw v2, vs0, 1 3645; P8LE-NEXT: blr 3646entry: 3647 %conv = fptoui double %val to i32 3648 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3649 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3650 ret <4 x i32> %splat.splat 3651} 3652 3653define <4 x i32> @spltMemValConvdtoui(ptr nocapture readonly %ptr) { 3654; P9BE-LABEL: spltMemValConvdtoui: 3655; P9BE: # %bb.0: # %entry 3656; P9BE-NEXT: lfd f0, 0(r3) 3657; P9BE-NEXT: xscvdpuxws f0, f0 3658; P9BE-NEXT: xxspltw v2, vs0, 1 3659; P9BE-NEXT: blr 3660; 3661; P9LE-LABEL: spltMemValConvdtoui: 3662; P9LE: # %bb.0: # %entry 3663; P9LE-NEXT: lfd f0, 0(r3) 3664; P9LE-NEXT: xscvdpuxws f0, f0 3665; P9LE-NEXT: xxspltw v2, vs0, 1 3666; P9LE-NEXT: blr 3667; 3668; P8BE-LABEL: spltMemValConvdtoui: 3669; P8BE: # %bb.0: # %entry 3670; P8BE-NEXT: lfdx f0, 0, r3 3671; P8BE-NEXT: xscvdpuxws f0, f0 3672; P8BE-NEXT: xxspltw v2, vs0, 1 3673; P8BE-NEXT: blr 3674; 3675; P8LE-LABEL: spltMemValConvdtoui: 3676; P8LE: # %bb.0: # %entry 3677; P8LE-NEXT: lfdx f0, 0, r3 3678; P8LE-NEXT: xscvdpuxws f0, f0 3679; P8LE-NEXT: xxspltw v2, vs0, 1 3680; P8LE-NEXT: blr 3681entry: 3682 %0 = load double, ptr %ptr, align 8 3683 %conv = fptoui double %0 to i32 3684 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 3685 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 3686 ret <4 x i32> %splat.splat 3687} 3688 3689define <2 x i64> @allZeroll() { 3690; P9BE-LABEL: allZeroll: 3691; P9BE: # %bb.0: # %entry 3692; P9BE-NEXT: xxlxor v2, v2, v2 3693; P9BE-NEXT: blr 3694; 3695; P9LE-LABEL: allZeroll: 3696; P9LE: # %bb.0: # %entry 3697; P9LE-NEXT: xxlxor v2, v2, v2 3698; P9LE-NEXT: blr 3699; 3700; P8BE-LABEL: allZeroll: 3701; P8BE: # %bb.0: # %entry 3702; P8BE-NEXT: xxlxor v2, v2, v2 3703; P8BE-NEXT: blr 3704; 3705; P8LE-LABEL: allZeroll: 3706; P8LE: # %bb.0: # %entry 3707; P8LE-NEXT: xxlxor v2, v2, v2 3708; P8LE-NEXT: blr 3709entry: 3710 ret <2 x i64> zeroinitializer 3711} 3712 3713define <2 x i64> @spltConst1ll() { 3714; P9BE-LABEL: spltConst1ll: 3715; P9BE: # %bb.0: # %entry 3716; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3717; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3718; P9BE-NEXT: lxv v2, 0(r3) 3719; P9BE-NEXT: blr 3720; 3721; P9LE-LABEL: spltConst1ll: 3722; P9LE: # %bb.0: # %entry 3723; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3724; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3725; P9LE-NEXT: lxv v2, 0(r3) 3726; P9LE-NEXT: blr 3727; 3728; P8BE-LABEL: spltConst1ll: 3729; P8BE: # %bb.0: # %entry 3730; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3731; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3732; P8BE-NEXT: lxvd2x v2, 0, r3 3733; P8BE-NEXT: blr 3734; 3735; P8LE-LABEL: spltConst1ll: 3736; P8LE: # %bb.0: # %entry 3737; P8LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha 3738; P8LE-NEXT: addi r3, r3, .LCPI65_0@toc@l 3739; P8LE-NEXT: lxvd2x v2, 0, r3 3740; P8LE-NEXT: blr 3741entry: 3742 ret <2 x i64> <i64 1, i64 1> 3743} 3744 3745define <2 x i64> @spltConst16kll() { 3746; P9BE-LABEL: spltConst16kll: 3747; P9BE: # %bb.0: # %entry 3748; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3749; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3750; P9BE-NEXT: lxv v2, 0(r3) 3751; P9BE-NEXT: blr 3752; 3753; P9LE-LABEL: spltConst16kll: 3754; P9LE: # %bb.0: # %entry 3755; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3756; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3757; P9LE-NEXT: lxv v2, 0(r3) 3758; P9LE-NEXT: blr 3759; 3760; P8BE-LABEL: spltConst16kll: 3761; P8BE: # %bb.0: # %entry 3762; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3763; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3764; P8BE-NEXT: lxvd2x v2, 0, r3 3765; P8BE-NEXT: blr 3766; 3767; P8LE-LABEL: spltConst16kll: 3768; P8LE: # %bb.0: # %entry 3769; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha 3770; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l 3771; P8LE-NEXT: lxvd2x v2, 0, r3 3772; P8LE-NEXT: blr 3773entry: 3774 ret <2 x i64> <i64 32767, i64 32767> 3775} 3776 3777define <2 x i64> @spltConst32kll() { 3778; P9BE-LABEL: spltConst32kll: 3779; P9BE: # %bb.0: # %entry 3780; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3781; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3782; P9BE-NEXT: lxv v2, 0(r3) 3783; P9BE-NEXT: blr 3784; 3785; P9LE-LABEL: spltConst32kll: 3786; P9LE: # %bb.0: # %entry 3787; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3788; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3789; P9LE-NEXT: lxv v2, 0(r3) 3790; P9LE-NEXT: blr 3791; 3792; P8BE-LABEL: spltConst32kll: 3793; P8BE: # %bb.0: # %entry 3794; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3795; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3796; P8BE-NEXT: lxvd2x v2, 0, r3 3797; P8BE-NEXT: blr 3798; 3799; P8LE-LABEL: spltConst32kll: 3800; P8LE: # %bb.0: # %entry 3801; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha 3802; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l 3803; P8LE-NEXT: lxvd2x v2, 0, r3 3804; P8LE-NEXT: blr 3805entry: 3806 ret <2 x i64> <i64 65535, i64 65535> 3807} 3808 3809define <2 x i64> @fromRegsll(i64 %a, i64 %b) { 3810; P9BE-LABEL: fromRegsll: 3811; P9BE: # %bb.0: # %entry 3812; P9BE-NEXT: mtvsrdd v2, r3, r4 3813; P9BE-NEXT: blr 3814; 3815; P9LE-LABEL: fromRegsll: 3816; P9LE: # %bb.0: # %entry 3817; P9LE-NEXT: mtvsrdd v2, r4, r3 3818; P9LE-NEXT: blr 3819; 3820; P8BE-LABEL: fromRegsll: 3821; P8BE: # %bb.0: # %entry 3822; P8BE-NEXT: mtfprd f0, r4 3823; P8BE-NEXT: mtfprd f1, r3 3824; P8BE-NEXT: xxmrghd v2, vs1, vs0 3825; P8BE-NEXT: blr 3826; 3827; P8LE-LABEL: fromRegsll: 3828; P8LE: # %bb.0: # %entry 3829; P8LE-NEXT: mtfprd f0, r3 3830; P8LE-NEXT: mtfprd f1, r4 3831; P8LE-NEXT: xxmrghd v2, vs1, vs0 3832; P8LE-NEXT: blr 3833entry: 3834 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 3835 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 3836 ret <2 x i64> %vecinit1 3837} 3838 3839define <2 x i64> @fromDiffConstsll() { 3840; P9BE-LABEL: fromDiffConstsll: 3841; P9BE: # %bb.0: # %entry 3842; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3843; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3844; P9BE-NEXT: lxv v2, 0(r3) 3845; P9BE-NEXT: blr 3846; 3847; P9LE-LABEL: fromDiffConstsll: 3848; P9LE: # %bb.0: # %entry 3849; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3850; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3851; P9LE-NEXT: lxv v2, 0(r3) 3852; P9LE-NEXT: blr 3853; 3854; P8BE-LABEL: fromDiffConstsll: 3855; P8BE: # %bb.0: # %entry 3856; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3857; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3858; P8BE-NEXT: lxvd2x v2, 0, r3 3859; P8BE-NEXT: blr 3860; 3861; P8LE-LABEL: fromDiffConstsll: 3862; P8LE: # %bb.0: # %entry 3863; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha 3864; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l 3865; P8LE-NEXT: lxvd2x vs0, 0, r3 3866; P8LE-NEXT: xxswapd v2, vs0 3867; P8LE-NEXT: blr 3868entry: 3869 ret <2 x i64> <i64 242, i64 -113> 3870} 3871 3872define <2 x i64> @fromDiffMemConsAll(ptr nocapture readonly %arr) { 3873; P9BE-LABEL: fromDiffMemConsAll: 3874; P9BE: # %bb.0: # %entry 3875; P9BE-NEXT: lxv v2, 0(r3) 3876; P9BE-NEXT: blr 3877; 3878; P9LE-LABEL: fromDiffMemConsAll: 3879; P9LE: # %bb.0: # %entry 3880; P9LE-NEXT: lxv v2, 0(r3) 3881; P9LE-NEXT: blr 3882; 3883; P8BE-LABEL: fromDiffMemConsAll: 3884; P8BE: # %bb.0: # %entry 3885; P8BE-NEXT: lxvd2x v2, 0, r3 3886; P8BE-NEXT: blr 3887; 3888; P8LE-LABEL: fromDiffMemConsAll: 3889; P8LE: # %bb.0: # %entry 3890; P8LE-NEXT: lxvd2x vs0, 0, r3 3891; P8LE-NEXT: xxswapd v2, vs0 3892; P8LE-NEXT: blr 3893entry: 3894 %0 = load i64, ptr %arr, align 8 3895 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3896 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 1 3897 %1 = load i64, ptr %arrayidx1, align 8 3898 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3899 ret <2 x i64> %vecinit2 3900} 3901 3902define <2 x i64> @fromDiffMemConsDll(ptr nocapture readonly %arr) { 3903; P9BE-LABEL: fromDiffMemConsDll: 3904; P9BE: # %bb.0: # %entry 3905; P9BE-NEXT: lxv v2, 16(r3) 3906; P9BE-NEXT: xxswapd v2, v2 3907; P9BE-NEXT: blr 3908; 3909; P9LE-LABEL: fromDiffMemConsDll: 3910; P9LE: # %bb.0: # %entry 3911; P9LE-NEXT: addi r3, r3, 16 3912; P9LE-NEXT: lxvd2x v2, 0, r3 3913; P9LE-NEXT: blr 3914; 3915; P8BE-LABEL: fromDiffMemConsDll: 3916; P8BE: # %bb.0: # %entry 3917; P8BE-NEXT: addi r3, r3, 16 3918; P8BE-NEXT: lxvd2x v2, 0, r3 3919; P8BE-NEXT: xxswapd v2, v2 3920; P8BE-NEXT: blr 3921; 3922; P8LE-LABEL: fromDiffMemConsDll: 3923; P8LE: # %bb.0: # %entry 3924; P8LE-NEXT: addi r3, r3, 16 3925; P8LE-NEXT: lxvd2x v2, 0, r3 3926; P8LE-NEXT: blr 3927entry: 3928 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 3 3929 %0 = load i64, ptr %arrayidx, align 8 3930 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3931 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 2 3932 %1 = load i64, ptr %arrayidx1, align 8 3933 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3934 ret <2 x i64> %vecinit2 3935} 3936 3937define <2 x i64> @fromDiffMemVarAll(ptr nocapture readonly %arr, i32 signext %elem) { 3938; P9BE-LABEL: fromDiffMemVarAll: 3939; P9BE: # %bb.0: # %entry 3940; P9BE-NEXT: sldi r4, r4, 3 3941; P9BE-NEXT: lxvx v2, r3, r4 3942; P9BE-NEXT: blr 3943; 3944; P9LE-LABEL: fromDiffMemVarAll: 3945; P9LE: # %bb.0: # %entry 3946; P9LE-NEXT: sldi r4, r4, 3 3947; P9LE-NEXT: lxvx v2, r3, r4 3948; P9LE-NEXT: blr 3949; 3950; P8BE-LABEL: fromDiffMemVarAll: 3951; P8BE: # %bb.0: # %entry 3952; P8BE-NEXT: sldi r4, r4, 3 3953; P8BE-NEXT: lxvd2x v2, r3, r4 3954; P8BE-NEXT: blr 3955; 3956; P8LE-LABEL: fromDiffMemVarAll: 3957; P8LE: # %bb.0: # %entry 3958; P8LE-NEXT: sldi r4, r4, 3 3959; P8LE-NEXT: lxvd2x vs0, r3, r4 3960; P8LE-NEXT: xxswapd v2, vs0 3961; P8LE-NEXT: blr 3962entry: 3963 %idxprom = sext i32 %elem to i64 3964 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom 3965 %0 = load i64, ptr %arrayidx, align 8 3966 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 3967 %add = add nsw i32 %elem, 1 3968 %idxprom1 = sext i32 %add to i64 3969 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1 3970 %1 = load i64, ptr %arrayidx2, align 8 3971 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 3972 ret <2 x i64> %vecinit3 3973} 3974 3975define <2 x i64> @fromDiffMemVarDll(ptr nocapture readonly %arr, i32 signext %elem) { 3976; P9BE-LABEL: fromDiffMemVarDll: 3977; P9BE: # %bb.0: # %entry 3978; P9BE-NEXT: sldi r4, r4, 3 3979; P9BE-NEXT: add r3, r3, r4 3980; P9BE-NEXT: li r4, -8 3981; P9BE-NEXT: lxvx v2, r3, r4 3982; P9BE-NEXT: xxswapd v2, v2 3983; P9BE-NEXT: blr 3984; 3985; P9LE-LABEL: fromDiffMemVarDll: 3986; P9LE: # %bb.0: # %entry 3987; P9LE-NEXT: sldi r4, r4, 3 3988; P9LE-NEXT: add r3, r3, r4 3989; P9LE-NEXT: addi r3, r3, -8 3990; P9LE-NEXT: lxvd2x v2, 0, r3 3991; P9LE-NEXT: blr 3992; 3993; P8BE-LABEL: fromDiffMemVarDll: 3994; P8BE: # %bb.0: # %entry 3995; P8BE-NEXT: sldi r4, r4, 3 3996; P8BE-NEXT: add r3, r3, r4 3997; P8BE-NEXT: addi r3, r3, -8 3998; P8BE-NEXT: lxvd2x v2, 0, r3 3999; P8BE-NEXT: xxswapd v2, v2 4000; P8BE-NEXT: blr 4001; 4002; P8LE-LABEL: fromDiffMemVarDll: 4003; P8LE: # %bb.0: # %entry 4004; P8LE-NEXT: sldi r4, r4, 3 4005; P8LE-NEXT: add r3, r3, r4 4006; P8LE-NEXT: addi r3, r3, -8 4007; P8LE-NEXT: lxvd2x v2, 0, r3 4008; P8LE-NEXT: blr 4009entry: 4010 %idxprom = sext i32 %elem to i64 4011 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom 4012 %0 = load i64, ptr %arrayidx, align 8 4013 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4014 %sub = add nsw i32 %elem, -1 4015 %idxprom1 = sext i32 %sub to i64 4016 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1 4017 %1 = load i64, ptr %arrayidx2, align 8 4018 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4019 ret <2 x i64> %vecinit3 4020} 4021 4022define <2 x i64> @fromRandMemConsll(ptr nocapture readonly %arr) { 4023; P9BE-LABEL: fromRandMemConsll: 4024; P9BE: # %bb.0: # %entry 4025; P9BE-NEXT: ld r4, 32(r3) 4026; P9BE-NEXT: ld r3, 144(r3) 4027; P9BE-NEXT: mtvsrdd v2, r4, r3 4028; P9BE-NEXT: blr 4029; 4030; P9LE-LABEL: fromRandMemConsll: 4031; P9LE: # %bb.0: # %entry 4032; P9LE-NEXT: ld r4, 32(r3) 4033; P9LE-NEXT: ld r3, 144(r3) 4034; P9LE-NEXT: mtvsrdd v2, r3, r4 4035; P9LE-NEXT: blr 4036; 4037; P8BE-LABEL: fromRandMemConsll: 4038; P8BE: # %bb.0: # %entry 4039; P8BE-NEXT: ld r4, 32(r3) 4040; P8BE-NEXT: ld r3, 144(r3) 4041; P8BE-NEXT: mtfprd f0, r3 4042; P8BE-NEXT: mtfprd f1, r4 4043; P8BE-NEXT: xxmrghd v2, vs1, vs0 4044; P8BE-NEXT: blr 4045; 4046; P8LE-LABEL: fromRandMemConsll: 4047; P8LE: # %bb.0: # %entry 4048; P8LE-NEXT: ld r4, 32(r3) 4049; P8LE-NEXT: ld r3, 144(r3) 4050; P8LE-NEXT: mtfprd f0, r4 4051; P8LE-NEXT: mtfprd f1, r3 4052; P8LE-NEXT: xxmrghd v2, vs1, vs0 4053; P8LE-NEXT: blr 4054entry: 4055 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 4 4056 %0 = load i64, ptr %arrayidx, align 8 4057 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4058 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 18 4059 %1 = load i64, ptr %arrayidx1, align 8 4060 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4061 ret <2 x i64> %vecinit2 4062} 4063 4064define <2 x i64> @fromRandMemVarll(ptr nocapture readonly %arr, i32 signext %elem) { 4065; P9BE-LABEL: fromRandMemVarll: 4066; P9BE: # %bb.0: # %entry 4067; P9BE-NEXT: sldi r4, r4, 3 4068; P9BE-NEXT: add r3, r3, r4 4069; P9BE-NEXT: ld r4, 32(r3) 4070; P9BE-NEXT: ld r3, 8(r3) 4071; P9BE-NEXT: mtvsrdd v2, r4, r3 4072; P9BE-NEXT: blr 4073; 4074; P9LE-LABEL: fromRandMemVarll: 4075; P9LE: # %bb.0: # %entry 4076; P9LE-NEXT: sldi r4, r4, 3 4077; P9LE-NEXT: add r3, r3, r4 4078; P9LE-NEXT: ld r4, 32(r3) 4079; P9LE-NEXT: ld r3, 8(r3) 4080; P9LE-NEXT: mtvsrdd v2, r3, r4 4081; P9LE-NEXT: blr 4082; 4083; P8BE-LABEL: fromRandMemVarll: 4084; P8BE: # %bb.0: # %entry 4085; P8BE-NEXT: sldi r4, r4, 3 4086; P8BE-NEXT: add r3, r3, r4 4087; P8BE-NEXT: ld r4, 32(r3) 4088; P8BE-NEXT: ld r3, 8(r3) 4089; P8BE-NEXT: mtfprd f0, r3 4090; P8BE-NEXT: mtfprd f1, r4 4091; P8BE-NEXT: xxmrghd v2, vs1, vs0 4092; P8BE-NEXT: blr 4093; 4094; P8LE-LABEL: fromRandMemVarll: 4095; P8LE: # %bb.0: # %entry 4096; P8LE-NEXT: sldi r4, r4, 3 4097; P8LE-NEXT: add r3, r3, r4 4098; P8LE-NEXT: ld r4, 32(r3) 4099; P8LE-NEXT: ld r3, 8(r3) 4100; P8LE-NEXT: mtfprd f0, r4 4101; P8LE-NEXT: mtfprd f1, r3 4102; P8LE-NEXT: xxmrghd v2, vs1, vs0 4103; P8LE-NEXT: blr 4104entry: 4105 %add = add nsw i32 %elem, 4 4106 %idxprom = sext i32 %add to i64 4107 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom 4108 %0 = load i64, ptr %arrayidx, align 8 4109 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 4110 %add1 = add nsw i32 %elem, 1 4111 %idxprom2 = sext i32 %add1 to i64 4112 %arrayidx3 = getelementptr inbounds i64, ptr %arr, i64 %idxprom2 4113 %1 = load i64, ptr %arrayidx3, align 8 4114 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 4115 ret <2 x i64> %vecinit4 4116} 4117 4118define <2 x i64> @spltRegValll(i64 %val) { 4119; P9BE-LABEL: spltRegValll: 4120; P9BE: # %bb.0: # %entry 4121; P9BE-NEXT: mtvsrdd v2, r3, r3 4122; P9BE-NEXT: blr 4123; 4124; P9LE-LABEL: spltRegValll: 4125; P9LE: # %bb.0: # %entry 4126; P9LE-NEXT: mtvsrdd v2, r3, r3 4127; P9LE-NEXT: blr 4128; 4129; P8BE-LABEL: spltRegValll: 4130; P8BE: # %bb.0: # %entry 4131; P8BE-NEXT: mtfprd f0, r3 4132; P8BE-NEXT: xxspltd v2, vs0, 0 4133; P8BE-NEXT: blr 4134; 4135; P8LE-LABEL: spltRegValll: 4136; P8LE: # %bb.0: # %entry 4137; P8LE-NEXT: mtfprd f0, r3 4138; P8LE-NEXT: xxspltd v2, vs0, 0 4139; P8LE-NEXT: blr 4140entry: 4141 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 4142 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4143 ret <2 x i64> %splat.splat 4144} 4145 4146define <2 x i64> @spltMemValll(ptr nocapture readonly %ptr) { 4147; P9BE-LABEL: spltMemValll: 4148; P9BE: # %bb.0: # %entry 4149; P9BE-NEXT: lxvdsx v2, 0, r3 4150; P9BE-NEXT: blr 4151; 4152; P9LE-LABEL: spltMemValll: 4153; P9LE: # %bb.0: # %entry 4154; P9LE-NEXT: lxvdsx v2, 0, r3 4155; P9LE-NEXT: blr 4156; 4157; P8BE-LABEL: spltMemValll: 4158; P8BE: # %bb.0: # %entry 4159; P8BE-NEXT: lxvdsx v2, 0, r3 4160; P8BE-NEXT: blr 4161; 4162; P8LE-LABEL: spltMemValll: 4163; P8LE: # %bb.0: # %entry 4164; P8LE-NEXT: lxvdsx v2, 0, r3 4165; P8LE-NEXT: blr 4166entry: 4167 %0 = load i64, ptr %ptr, align 8 4168 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 4169 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4170 ret <2 x i64> %splat.splat 4171} 4172 4173define <2 x i64> @spltCnstConvftoll() { 4174; P9BE-LABEL: spltCnstConvftoll: 4175; P9BE: # %bb.0: # %entry 4176; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4177; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4178; P9BE-NEXT: lxv v2, 0(r3) 4179; P9BE-NEXT: blr 4180; 4181; P9LE-LABEL: spltCnstConvftoll: 4182; P9LE: # %bb.0: # %entry 4183; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4184; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4185; P9LE-NEXT: lxv v2, 0(r3) 4186; P9LE-NEXT: blr 4187; 4188; P8BE-LABEL: spltCnstConvftoll: 4189; P8BE: # %bb.0: # %entry 4190; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4191; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4192; P8BE-NEXT: lxvd2x v2, 0, r3 4193; P8BE-NEXT: blr 4194; 4195; P8LE-LABEL: spltCnstConvftoll: 4196; P8LE: # %bb.0: # %entry 4197; P8LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha 4198; P8LE-NEXT: addi r3, r3, .LCPI78_0@toc@l 4199; P8LE-NEXT: lxvd2x v2, 0, r3 4200; P8LE-NEXT: blr 4201entry: 4202 ret <2 x i64> <i64 4, i64 4> 4203} 4204 4205define <2 x i64> @fromRegsConvftoll(float %a, float %b) { 4206; P9BE-LABEL: fromRegsConvftoll: 4207; P9BE: # %bb.0: # %entry 4208; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4209; P9BE-NEXT: xvcvdpsxds v2, vs0 4210; P9BE-NEXT: blr 4211; 4212; P9LE-LABEL: fromRegsConvftoll: 4213; P9LE: # %bb.0: # %entry 4214; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4215; P9LE-NEXT: xvcvdpsxds v2, vs0 4216; P9LE-NEXT: blr 4217; 4218; P8BE-LABEL: fromRegsConvftoll: 4219; P8BE: # %bb.0: # %entry 4220; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4221; P8BE-NEXT: xvcvdpsxds v2, vs0 4222; P8BE-NEXT: blr 4223; 4224; P8LE-LABEL: fromRegsConvftoll: 4225; P8LE: # %bb.0: # %entry 4226; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4227; P8LE-NEXT: xvcvdpsxds v2, vs0 4228; P8LE-NEXT: blr 4229entry: 4230 %conv = fptosi float %a to i64 4231 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4232 %conv1 = fptosi float %b to i64 4233 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4234 ret <2 x i64> %vecinit2 4235} 4236 4237define <2 x i64> @fromDiffConstsConvftoll() { 4238; P9BE-LABEL: fromDiffConstsConvftoll: 4239; P9BE: # %bb.0: # %entry 4240; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4241; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4242; P9BE-NEXT: lxv v2, 0(r3) 4243; P9BE-NEXT: blr 4244; 4245; P9LE-LABEL: fromDiffConstsConvftoll: 4246; P9LE: # %bb.0: # %entry 4247; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4248; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4249; P9LE-NEXT: lxv v2, 0(r3) 4250; P9LE-NEXT: blr 4251; 4252; P8BE-LABEL: fromDiffConstsConvftoll: 4253; P8BE: # %bb.0: # %entry 4254; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4255; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4256; P8BE-NEXT: lxvd2x v2, 0, r3 4257; P8BE-NEXT: blr 4258; 4259; P8LE-LABEL: fromDiffConstsConvftoll: 4260; P8LE: # %bb.0: # %entry 4261; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha 4262; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l 4263; P8LE-NEXT: lxvd2x vs0, 0, r3 4264; P8LE-NEXT: xxswapd v2, vs0 4265; P8LE-NEXT: blr 4266entry: 4267 ret <2 x i64> <i64 24, i64 234> 4268} 4269 4270define <2 x i64> @fromDiffMemConsAConvftoll(ptr nocapture readonly %ptr) { 4271; P9BE-LABEL: fromDiffMemConsAConvftoll: 4272; P9BE: # %bb.0: # %entry 4273; P9BE-NEXT: lfs f0, 0(r3) 4274; P9BE-NEXT: lfs f1, 4(r3) 4275; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4276; P9BE-NEXT: xvcvdpsxds v2, vs0 4277; P9BE-NEXT: blr 4278; 4279; P9LE-LABEL: fromDiffMemConsAConvftoll: 4280; P9LE: # %bb.0: # %entry 4281; P9LE-NEXT: lfs f0, 0(r3) 4282; P9LE-NEXT: lfs f1, 4(r3) 4283; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4284; P9LE-NEXT: xvcvdpsxds v2, vs0 4285; P9LE-NEXT: blr 4286; 4287; P8BE-LABEL: fromDiffMemConsAConvftoll: 4288; P8BE: # %bb.0: # %entry 4289; P8BE-NEXT: lfs f0, 0(r3) 4290; P8BE-NEXT: lfs f1, 4(r3) 4291; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4292; P8BE-NEXT: xvcvdpsxds v2, vs0 4293; P8BE-NEXT: blr 4294; 4295; P8LE-LABEL: fromDiffMemConsAConvftoll: 4296; P8LE: # %bb.0: # %entry 4297; P8LE-NEXT: lfs f0, 0(r3) 4298; P8LE-NEXT: lfs f1, 4(r3) 4299; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4300; P8LE-NEXT: xvcvdpsxds v2, vs0 4301; P8LE-NEXT: blr 4302entry: 4303 %0 = load float, ptr %ptr, align 4 4304 %conv = fptosi float %0 to i64 4305 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4306 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 1 4307 %1 = load float, ptr %arrayidx1, align 4 4308 %conv2 = fptosi float %1 to i64 4309 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4310 ret <2 x i64> %vecinit3 4311} 4312 4313define <2 x i64> @fromDiffMemConsDConvftoll(ptr nocapture readonly %ptr) { 4314; P9BE-LABEL: fromDiffMemConsDConvftoll: 4315; P9BE: # %bb.0: # %entry 4316; P9BE-NEXT: lfs f0, 12(r3) 4317; P9BE-NEXT: lfs f1, 8(r3) 4318; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4319; P9BE-NEXT: xvcvdpsxds v2, vs0 4320; P9BE-NEXT: blr 4321; 4322; P9LE-LABEL: fromDiffMemConsDConvftoll: 4323; P9LE: # %bb.0: # %entry 4324; P9LE-NEXT: lfs f0, 12(r3) 4325; P9LE-NEXT: lfs f1, 8(r3) 4326; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4327; P9LE-NEXT: xvcvdpsxds v2, vs0 4328; P9LE-NEXT: blr 4329; 4330; P8BE-LABEL: fromDiffMemConsDConvftoll: 4331; P8BE: # %bb.0: # %entry 4332; P8BE-NEXT: lfs f0, 12(r3) 4333; P8BE-NEXT: lfs f1, 8(r3) 4334; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4335; P8BE-NEXT: xvcvdpsxds v2, vs0 4336; P8BE-NEXT: blr 4337; 4338; P8LE-LABEL: fromDiffMemConsDConvftoll: 4339; P8LE: # %bb.0: # %entry 4340; P8LE-NEXT: lfs f0, 12(r3) 4341; P8LE-NEXT: lfs f1, 8(r3) 4342; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4343; P8LE-NEXT: xvcvdpsxds v2, vs0 4344; P8LE-NEXT: blr 4345entry: 4346 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3 4347 %0 = load float, ptr %arrayidx, align 4 4348 %conv = fptosi float %0 to i64 4349 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4350 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2 4351 %1 = load float, ptr %arrayidx1, align 4 4352 %conv2 = fptosi float %1 to i64 4353 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4354 ret <2 x i64> %vecinit3 4355} 4356 4357define <2 x i64> @fromDiffMemVarAConvftoll(ptr nocapture readonly %arr, i32 signext %elem) { 4358; P9BE-LABEL: fromDiffMemVarAConvftoll: 4359; P9BE: # %bb.0: # %entry 4360; P9BE-NEXT: sldi r4, r4, 2 4361; P9BE-NEXT: lfsux f0, r3, r4 4362; P9BE-NEXT: lfs f1, 4(r3) 4363; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4364; P9BE-NEXT: xvcvdpsxds v2, vs0 4365; P9BE-NEXT: blr 4366; 4367; P9LE-LABEL: fromDiffMemVarAConvftoll: 4368; P9LE: # %bb.0: # %entry 4369; P9LE-NEXT: sldi r4, r4, 2 4370; P9LE-NEXT: lfsux f0, r3, r4 4371; P9LE-NEXT: lfs f1, 4(r3) 4372; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4373; P9LE-NEXT: xvcvdpsxds v2, vs0 4374; P9LE-NEXT: blr 4375; 4376; P8BE-LABEL: fromDiffMemVarAConvftoll: 4377; P8BE: # %bb.0: # %entry 4378; P8BE-NEXT: sldi r4, r4, 2 4379; P8BE-NEXT: lfsux f0, r3, r4 4380; P8BE-NEXT: lfs f1, 4(r3) 4381; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4382; P8BE-NEXT: xvcvdpsxds v2, vs0 4383; P8BE-NEXT: blr 4384; 4385; P8LE-LABEL: fromDiffMemVarAConvftoll: 4386; P8LE: # %bb.0: # %entry 4387; P8LE-NEXT: sldi r4, r4, 2 4388; P8LE-NEXT: lfsux f0, r3, r4 4389; P8LE-NEXT: lfs f1, 4(r3) 4390; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4391; P8LE-NEXT: xvcvdpsxds v2, vs0 4392; P8LE-NEXT: blr 4393entry: 4394 %idxprom = sext i32 %elem to i64 4395 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom 4396 %0 = load float, ptr %arrayidx, align 4 4397 %conv = fptosi float %0 to i64 4398 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4399 %add = add nsw i32 %elem, 1 4400 %idxprom1 = sext i32 %add to i64 4401 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1 4402 %1 = load float, ptr %arrayidx2, align 4 4403 %conv3 = fptosi float %1 to i64 4404 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4405 ret <2 x i64> %vecinit4 4406} 4407 4408define <2 x i64> @fromDiffMemVarDConvftoll(ptr nocapture readonly %arr, i32 signext %elem) { 4409; P9BE-LABEL: fromDiffMemVarDConvftoll: 4410; P9BE: # %bb.0: # %entry 4411; P9BE-NEXT: sldi r4, r4, 2 4412; P9BE-NEXT: lfsux f0, r3, r4 4413; P9BE-NEXT: lfs f1, -4(r3) 4414; P9BE-NEXT: xxmrghd vs0, vs0, vs1 4415; P9BE-NEXT: xvcvdpsxds v2, vs0 4416; P9BE-NEXT: blr 4417; 4418; P9LE-LABEL: fromDiffMemVarDConvftoll: 4419; P9LE: # %bb.0: # %entry 4420; P9LE-NEXT: sldi r4, r4, 2 4421; P9LE-NEXT: lfsux f0, r3, r4 4422; P9LE-NEXT: lfs f1, -4(r3) 4423; P9LE-NEXT: xxmrghd vs0, vs1, vs0 4424; P9LE-NEXT: xvcvdpsxds v2, vs0 4425; P9LE-NEXT: blr 4426; 4427; P8BE-LABEL: fromDiffMemVarDConvftoll: 4428; P8BE: # %bb.0: # %entry 4429; P8BE-NEXT: sldi r4, r4, 2 4430; P8BE-NEXT: lfsux f0, r3, r4 4431; P8BE-NEXT: lfs f1, -4(r3) 4432; P8BE-NEXT: xxmrghd vs0, vs0, vs1 4433; P8BE-NEXT: xvcvdpsxds v2, vs0 4434; P8BE-NEXT: blr 4435; 4436; P8LE-LABEL: fromDiffMemVarDConvftoll: 4437; P8LE: # %bb.0: # %entry 4438; P8LE-NEXT: sldi r4, r4, 2 4439; P8LE-NEXT: lfsux f0, r3, r4 4440; P8LE-NEXT: lfs f1, -4(r3) 4441; P8LE-NEXT: xxmrghd vs0, vs1, vs0 4442; P8LE-NEXT: xvcvdpsxds v2, vs0 4443; P8LE-NEXT: blr 4444entry: 4445 %idxprom = sext i32 %elem to i64 4446 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom 4447 %0 = load float, ptr %arrayidx, align 4 4448 %conv = fptosi float %0 to i64 4449 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4450 %sub = add nsw i32 %elem, -1 4451 %idxprom1 = sext i32 %sub to i64 4452 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1 4453 %1 = load float, ptr %arrayidx2, align 4 4454 %conv3 = fptosi float %1 to i64 4455 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4456 ret <2 x i64> %vecinit4 4457} 4458 4459define <2 x i64> @spltRegValConvftoll(float %val) { 4460; P9BE-LABEL: spltRegValConvftoll: 4461; P9BE: # %bb.0: # %entry 4462; P9BE-NEXT: xscvdpsxds f0, f1 4463; P9BE-NEXT: xxspltd v2, f0, 0 4464; P9BE-NEXT: blr 4465; 4466; P9LE-LABEL: spltRegValConvftoll: 4467; P9LE: # %bb.0: # %entry 4468; P9LE-NEXT: xscvdpsxds f0, f1 4469; P9LE-NEXT: xxspltd v2, f0, 0 4470; P9LE-NEXT: blr 4471; 4472; P8BE-LABEL: spltRegValConvftoll: 4473; P8BE: # %bb.0: # %entry 4474; P8BE-NEXT: xscvdpsxds f0, f1 4475; P8BE-NEXT: xxspltd v2, f0, 0 4476; P8BE-NEXT: blr 4477; 4478; P8LE-LABEL: spltRegValConvftoll: 4479; P8LE: # %bb.0: # %entry 4480; P8LE-NEXT: xscvdpsxds f0, f1 4481; P8LE-NEXT: xxspltd v2, f0, 0 4482; P8LE-NEXT: blr 4483entry: 4484 %conv = fptosi float %val to i64 4485 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4486 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4487 ret <2 x i64> %splat.splat 4488} 4489 4490define <2 x i64> @spltMemValConvftoll(ptr nocapture readonly %ptr) { 4491; P9BE-LABEL: spltMemValConvftoll: 4492; P9BE: # %bb.0: # %entry 4493; P9BE-NEXT: lfs f0, 0(r3) 4494; P9BE-NEXT: xscvdpsxds f0, f0 4495; P9BE-NEXT: xxspltd v2, f0, 0 4496; P9BE-NEXT: blr 4497; 4498; P9LE-LABEL: spltMemValConvftoll: 4499; P9LE: # %bb.0: # %entry 4500; P9LE-NEXT: lfs f0, 0(r3) 4501; P9LE-NEXT: xscvdpsxds f0, f0 4502; P9LE-NEXT: xxspltd v2, vs0, 0 4503; P9LE-NEXT: blr 4504; 4505; P8BE-LABEL: spltMemValConvftoll: 4506; P8BE: # %bb.0: # %entry 4507; P8BE-NEXT: lfsx f0, 0, r3 4508; P8BE-NEXT: xscvdpsxds f0, f0 4509; P8BE-NEXT: xxspltd v2, f0, 0 4510; P8BE-NEXT: blr 4511; 4512; P8LE-LABEL: spltMemValConvftoll: 4513; P8LE: # %bb.0: # %entry 4514; P8LE-NEXT: lfsx f0, 0, r3 4515; P8LE-NEXT: xscvdpsxds f0, f0 4516; P8LE-NEXT: xxspltd v2, vs0, 0 4517; P8LE-NEXT: blr 4518entry: 4519 %0 = load float, ptr %ptr, align 4 4520 %conv = fptosi float %0 to i64 4521 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4522 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4523 ret <2 x i64> %splat.splat 4524} 4525 4526define <2 x i64> @spltCnstConvdtoll() { 4527; P9BE-LABEL: spltCnstConvdtoll: 4528; P9BE: # %bb.0: # %entry 4529; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4530; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4531; P9BE-NEXT: lxv v2, 0(r3) 4532; P9BE-NEXT: blr 4533; 4534; P9LE-LABEL: spltCnstConvdtoll: 4535; P9LE: # %bb.0: # %entry 4536; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4537; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4538; P9LE-NEXT: lxv v2, 0(r3) 4539; P9LE-NEXT: blr 4540; 4541; P8BE-LABEL: spltCnstConvdtoll: 4542; P8BE: # %bb.0: # %entry 4543; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4544; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4545; P8BE-NEXT: lxvd2x v2, 0, r3 4546; P8BE-NEXT: blr 4547; 4548; P8LE-LABEL: spltCnstConvdtoll: 4549; P8LE: # %bb.0: # %entry 4550; P8LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha 4551; P8LE-NEXT: addi r3, r3, .LCPI87_0@toc@l 4552; P8LE-NEXT: lxvd2x v2, 0, r3 4553; P8LE-NEXT: blr 4554entry: 4555 ret <2 x i64> <i64 4, i64 4> 4556} 4557 4558define <2 x i64> @fromRegsConvdtoll(double %a, double %b) { 4559; P9BE-LABEL: fromRegsConvdtoll: 4560; P9BE: # %bb.0: # %entry 4561; P9BE-NEXT: xxmrghd vs0, vs1, vs2 4562; P9BE-NEXT: xvcvdpsxds v2, vs0 4563; P9BE-NEXT: blr 4564; 4565; P9LE-LABEL: fromRegsConvdtoll: 4566; P9LE: # %bb.0: # %entry 4567; P9LE-NEXT: xxmrghd vs0, vs2, vs1 4568; P9LE-NEXT: xvcvdpsxds v2, vs0 4569; P9LE-NEXT: blr 4570; 4571; P8BE-LABEL: fromRegsConvdtoll: 4572; P8BE: # %bb.0: # %entry 4573; P8BE-NEXT: xxmrghd vs0, vs1, vs2 4574; P8BE-NEXT: xvcvdpsxds v2, vs0 4575; P8BE-NEXT: blr 4576; 4577; P8LE-LABEL: fromRegsConvdtoll: 4578; P8LE: # %bb.0: # %entry 4579; P8LE-NEXT: xxmrghd vs0, vs2, vs1 4580; P8LE-NEXT: xvcvdpsxds v2, vs0 4581; P8LE-NEXT: blr 4582entry: 4583 %conv = fptosi double %a to i64 4584 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4585 %conv1 = fptosi double %b to i64 4586 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 4587 ret <2 x i64> %vecinit2 4588} 4589 4590define <2 x i64> @fromDiffConstsConvdtoll() { 4591; P9BE-LABEL: fromDiffConstsConvdtoll: 4592; P9BE: # %bb.0: # %entry 4593; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4594; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4595; P9BE-NEXT: lxv v2, 0(r3) 4596; P9BE-NEXT: blr 4597; 4598; P9LE-LABEL: fromDiffConstsConvdtoll: 4599; P9LE: # %bb.0: # %entry 4600; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4601; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4602; P9LE-NEXT: lxv v2, 0(r3) 4603; P9LE-NEXT: blr 4604; 4605; P8BE-LABEL: fromDiffConstsConvdtoll: 4606; P8BE: # %bb.0: # %entry 4607; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4608; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4609; P8BE-NEXT: lxvd2x v2, 0, r3 4610; P8BE-NEXT: blr 4611; 4612; P8LE-LABEL: fromDiffConstsConvdtoll: 4613; P8LE: # %bb.0: # %entry 4614; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha 4615; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l 4616; P8LE-NEXT: lxvd2x vs0, 0, r3 4617; P8LE-NEXT: xxswapd v2, vs0 4618; P8LE-NEXT: blr 4619entry: 4620 ret <2 x i64> <i64 24, i64 234> 4621} 4622 4623define <2 x i64> @fromDiffMemConsAConvdtoll(ptr nocapture readonly %ptr) { 4624; P9BE-LABEL: fromDiffMemConsAConvdtoll: 4625; P9BE: # %bb.0: # %entry 4626; P9BE-NEXT: lxv vs0, 0(r3) 4627; P9BE-NEXT: xvcvdpsxds v2, vs0 4628; P9BE-NEXT: blr 4629; 4630; P9LE-LABEL: fromDiffMemConsAConvdtoll: 4631; P9LE: # %bb.0: # %entry 4632; P9LE-NEXT: lxv vs0, 0(r3) 4633; P9LE-NEXT: xvcvdpsxds v2, vs0 4634; P9LE-NEXT: blr 4635; 4636; P8BE-LABEL: fromDiffMemConsAConvdtoll: 4637; P8BE: # %bb.0: # %entry 4638; P8BE-NEXT: lxvd2x vs0, 0, r3 4639; P8BE-NEXT: xvcvdpsxds v2, vs0 4640; P8BE-NEXT: blr 4641; 4642; P8LE-LABEL: fromDiffMemConsAConvdtoll: 4643; P8LE: # %bb.0: # %entry 4644; P8LE-NEXT: lxvd2x vs0, 0, r3 4645; P8LE-NEXT: xxswapd vs0, vs0 4646; P8LE-NEXT: xvcvdpsxds v2, vs0 4647; P8LE-NEXT: blr 4648entry: 4649 %0 = load <2 x double>, ptr %ptr, align 8 4650 %1 = fptosi <2 x double> %0 to <2 x i64> 4651 ret <2 x i64> %1 4652} 4653 4654define <2 x i64> @fromDiffMemConsDConvdtoll(ptr nocapture readonly %ptr) { 4655; P9BE-LABEL: fromDiffMemConsDConvdtoll: 4656; P9BE: # %bb.0: # %entry 4657; P9BE-NEXT: lxv vs0, 16(r3) 4658; P9BE-NEXT: xxswapd vs0, vs0 4659; P9BE-NEXT: xvcvdpsxds v2, vs0 4660; P9BE-NEXT: blr 4661; 4662; P9LE-LABEL: fromDiffMemConsDConvdtoll: 4663; P9LE: # %bb.0: # %entry 4664; P9LE-NEXT: addi r3, r3, 16 4665; P9LE-NEXT: lxvd2x vs0, 0, r3 4666; P9LE-NEXT: xvcvdpsxds v2, vs0 4667; P9LE-NEXT: blr 4668; 4669; P8BE-LABEL: fromDiffMemConsDConvdtoll: 4670; P8BE: # %bb.0: # %entry 4671; P8BE-NEXT: addi r3, r3, 16 4672; P8BE-NEXT: lxvd2x vs0, 0, r3 4673; P8BE-NEXT: xxswapd vs0, vs0 4674; P8BE-NEXT: xvcvdpsxds v2, vs0 4675; P8BE-NEXT: blr 4676; 4677; P8LE-LABEL: fromDiffMemConsDConvdtoll: 4678; P8LE: # %bb.0: # %entry 4679; P8LE-NEXT: addi r3, r3, 16 4680; P8LE-NEXT: lxvd2x vs0, 0, r3 4681; P8LE-NEXT: xvcvdpsxds v2, vs0 4682; P8LE-NEXT: blr 4683entry: 4684 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3 4685 %0 = load double, ptr %arrayidx, align 8 4686 %conv = fptosi double %0 to i64 4687 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4688 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2 4689 %1 = load double, ptr %arrayidx1, align 8 4690 %conv2 = fptosi double %1 to i64 4691 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 4692 ret <2 x i64> %vecinit3 4693} 4694 4695define <2 x i64> @fromDiffMemVarAConvdtoll(ptr nocapture readonly %arr, i32 signext %elem) { 4696; P9BE-LABEL: fromDiffMemVarAConvdtoll: 4697; P9BE: # %bb.0: # %entry 4698; P9BE-NEXT: sldi r4, r4, 3 4699; P9BE-NEXT: lxvx vs0, r3, r4 4700; P9BE-NEXT: xvcvdpsxds v2, vs0 4701; P9BE-NEXT: blr 4702; 4703; P9LE-LABEL: fromDiffMemVarAConvdtoll: 4704; P9LE: # %bb.0: # %entry 4705; P9LE-NEXT: sldi r4, r4, 3 4706; P9LE-NEXT: lxvx vs0, r3, r4 4707; P9LE-NEXT: xvcvdpsxds v2, vs0 4708; P9LE-NEXT: blr 4709; 4710; P8BE-LABEL: fromDiffMemVarAConvdtoll: 4711; P8BE: # %bb.0: # %entry 4712; P8BE-NEXT: sldi r4, r4, 3 4713; P8BE-NEXT: lxvd2x vs0, r3, r4 4714; P8BE-NEXT: xvcvdpsxds v2, vs0 4715; P8BE-NEXT: blr 4716; 4717; P8LE-LABEL: fromDiffMemVarAConvdtoll: 4718; P8LE: # %bb.0: # %entry 4719; P8LE-NEXT: sldi r4, r4, 3 4720; P8LE-NEXT: lxvd2x vs0, r3, r4 4721; P8LE-NEXT: xxswapd vs0, vs0 4722; P8LE-NEXT: xvcvdpsxds v2, vs0 4723; P8LE-NEXT: blr 4724entry: 4725 %idxprom = sext i32 %elem to i64 4726 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom 4727 %0 = load double, ptr %arrayidx, align 8 4728 %conv = fptosi double %0 to i64 4729 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4730 %add = add nsw i32 %elem, 1 4731 %idxprom1 = sext i32 %add to i64 4732 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1 4733 %1 = load double, ptr %arrayidx2, align 8 4734 %conv3 = fptosi double %1 to i64 4735 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4736 ret <2 x i64> %vecinit4 4737} 4738 4739define <2 x i64> @fromDiffMemVarDConvdtoll(ptr nocapture readonly %arr, i32 signext %elem) { 4740; P9BE-LABEL: fromDiffMemVarDConvdtoll: 4741; P9BE: # %bb.0: # %entry 4742; P9BE-NEXT: sldi r4, r4, 3 4743; P9BE-NEXT: add r3, r3, r4 4744; P9BE-NEXT: li r4, -8 4745; P9BE-NEXT: lxvx vs0, r3, r4 4746; P9BE-NEXT: xxswapd vs0, vs0 4747; P9BE-NEXT: xvcvdpsxds v2, vs0 4748; P9BE-NEXT: blr 4749; 4750; P9LE-LABEL: fromDiffMemVarDConvdtoll: 4751; P9LE: # %bb.0: # %entry 4752; P9LE-NEXT: sldi r4, r4, 3 4753; P9LE-NEXT: add r3, r3, r4 4754; P9LE-NEXT: addi r3, r3, -8 4755; P9LE-NEXT: lxvd2x vs0, 0, r3 4756; P9LE-NEXT: xvcvdpsxds v2, vs0 4757; P9LE-NEXT: blr 4758; 4759; P8BE-LABEL: fromDiffMemVarDConvdtoll: 4760; P8BE: # %bb.0: # %entry 4761; P8BE-NEXT: sldi r4, r4, 3 4762; P8BE-NEXT: add r3, r3, r4 4763; P8BE-NEXT: addi r3, r3, -8 4764; P8BE-NEXT: lxvd2x vs0, 0, r3 4765; P8BE-NEXT: xxswapd vs0, vs0 4766; P8BE-NEXT: xvcvdpsxds v2, vs0 4767; P8BE-NEXT: blr 4768; 4769; P8LE-LABEL: fromDiffMemVarDConvdtoll: 4770; P8LE: # %bb.0: # %entry 4771; P8LE-NEXT: sldi r4, r4, 3 4772; P8LE-NEXT: add r3, r3, r4 4773; P8LE-NEXT: addi r3, r3, -8 4774; P8LE-NEXT: lxvd2x vs0, 0, r3 4775; P8LE-NEXT: xvcvdpsxds v2, vs0 4776; P8LE-NEXT: blr 4777entry: 4778 %idxprom = sext i32 %elem to i64 4779 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom 4780 %0 = load double, ptr %arrayidx, align 8 4781 %conv = fptosi double %0 to i64 4782 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 4783 %sub = add nsw i32 %elem, -1 4784 %idxprom1 = sext i32 %sub to i64 4785 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1 4786 %1 = load double, ptr %arrayidx2, align 8 4787 %conv3 = fptosi double %1 to i64 4788 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 4789 ret <2 x i64> %vecinit4 4790} 4791 4792define <2 x i64> @spltRegValConvdtoll(double %val) { 4793; P9BE-LABEL: spltRegValConvdtoll: 4794; P9BE: # %bb.0: # %entry 4795; P9BE-NEXT: xscvdpsxds f0, f1 4796; P9BE-NEXT: xxspltd v2, vs0, 0 4797; P9BE-NEXT: blr 4798; 4799; P9LE-LABEL: spltRegValConvdtoll: 4800; P9LE: # %bb.0: # %entry 4801; P9LE-NEXT: xscvdpsxds f0, f1 4802; P9LE-NEXT: xxspltd v2, vs0, 0 4803; P9LE-NEXT: blr 4804; 4805; P8BE-LABEL: spltRegValConvdtoll: 4806; P8BE: # %bb.0: # %entry 4807; P8BE-NEXT: xscvdpsxds f0, f1 4808; P8BE-NEXT: xxspltd v2, vs0, 0 4809; P8BE-NEXT: blr 4810; 4811; P8LE-LABEL: spltRegValConvdtoll: 4812; P8LE: # %bb.0: # %entry 4813; P8LE-NEXT: xscvdpsxds f0, f1 4814; P8LE-NEXT: xxspltd v2, vs0, 0 4815; P8LE-NEXT: blr 4816entry: 4817 %conv = fptosi double %val to i64 4818 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4819 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4820 ret <2 x i64> %splat.splat 4821} 4822 4823define <2 x i64> @spltMemValConvdtoll(ptr nocapture readonly %ptr) { 4824; P9BE-LABEL: spltMemValConvdtoll: 4825; P9BE: # %bb.0: # %entry 4826; P9BE-NEXT: lxvdsx vs0, 0, r3 4827; P9BE-NEXT: xvcvdpsxds v2, vs0 4828; P9BE-NEXT: blr 4829; 4830; P9LE-LABEL: spltMemValConvdtoll: 4831; P9LE: # %bb.0: # %entry 4832; P9LE-NEXT: lxvdsx vs0, 0, r3 4833; P9LE-NEXT: xvcvdpsxds v2, vs0 4834; P9LE-NEXT: blr 4835; 4836; P8BE-LABEL: spltMemValConvdtoll: 4837; P8BE: # %bb.0: # %entry 4838; P8BE-NEXT: lxvdsx vs0, 0, r3 4839; P8BE-NEXT: xvcvdpsxds v2, vs0 4840; P8BE-NEXT: blr 4841; 4842; P8LE-LABEL: spltMemValConvdtoll: 4843; P8LE: # %bb.0: # %entry 4844; P8LE-NEXT: lxvdsx vs0, 0, r3 4845; P8LE-NEXT: xvcvdpsxds v2, vs0 4846; P8LE-NEXT: blr 4847entry: 4848 %0 = load double, ptr %ptr, align 8 4849 %conv = fptosi double %0 to i64 4850 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 4851 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 4852 ret <2 x i64> %splat.splat 4853} 4854 4855define <2 x i64> @allZeroull() { 4856; P9BE-LABEL: allZeroull: 4857; P9BE: # %bb.0: # %entry 4858; P9BE-NEXT: xxlxor v2, v2, v2 4859; P9BE-NEXT: blr 4860; 4861; P9LE-LABEL: allZeroull: 4862; P9LE: # %bb.0: # %entry 4863; P9LE-NEXT: xxlxor v2, v2, v2 4864; P9LE-NEXT: blr 4865; 4866; P8BE-LABEL: allZeroull: 4867; P8BE: # %bb.0: # %entry 4868; P8BE-NEXT: xxlxor v2, v2, v2 4869; P8BE-NEXT: blr 4870; 4871; P8LE-LABEL: allZeroull: 4872; P8LE: # %bb.0: # %entry 4873; P8LE-NEXT: xxlxor v2, v2, v2 4874; P8LE-NEXT: blr 4875entry: 4876 ret <2 x i64> zeroinitializer 4877} 4878 4879define <2 x i64> @spltConst1ull() { 4880; P9BE-LABEL: spltConst1ull: 4881; P9BE: # %bb.0: # %entry 4882; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4883; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4884; P9BE-NEXT: lxv v2, 0(r3) 4885; P9BE-NEXT: blr 4886; 4887; P9LE-LABEL: spltConst1ull: 4888; P9LE: # %bb.0: # %entry 4889; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4890; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4891; P9LE-NEXT: lxv v2, 0(r3) 4892; P9LE-NEXT: blr 4893; 4894; P8BE-LABEL: spltConst1ull: 4895; P8BE: # %bb.0: # %entry 4896; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4897; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4898; P8BE-NEXT: lxvd2x v2, 0, r3 4899; P8BE-NEXT: blr 4900; 4901; P8LE-LABEL: spltConst1ull: 4902; P8LE: # %bb.0: # %entry 4903; P8LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha 4904; P8LE-NEXT: addi r3, r3, .LCPI97_0@toc@l 4905; P8LE-NEXT: lxvd2x v2, 0, r3 4906; P8LE-NEXT: blr 4907entry: 4908 ret <2 x i64> <i64 1, i64 1> 4909} 4910 4911define <2 x i64> @spltConst16kull() { 4912; P9BE-LABEL: spltConst16kull: 4913; P9BE: # %bb.0: # %entry 4914; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 4915; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 4916; P9BE-NEXT: lxv v2, 0(r3) 4917; P9BE-NEXT: blr 4918; 4919; P9LE-LABEL: spltConst16kull: 4920; P9LE: # %bb.0: # %entry 4921; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 4922; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 4923; P9LE-NEXT: lxv v2, 0(r3) 4924; P9LE-NEXT: blr 4925; 4926; P8BE-LABEL: spltConst16kull: 4927; P8BE: # %bb.0: # %entry 4928; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 4929; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l 4930; P8BE-NEXT: lxvd2x v2, 0, r3 4931; P8BE-NEXT: blr 4932; 4933; P8LE-LABEL: spltConst16kull: 4934; P8LE: # %bb.0: # %entry 4935; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha 4936; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l 4937; P8LE-NEXT: lxvd2x v2, 0, r3 4938; P8LE-NEXT: blr 4939entry: 4940 ret <2 x i64> <i64 32767, i64 32767> 4941} 4942 4943define <2 x i64> @spltConst32kull() { 4944; P9BE-LABEL: spltConst32kull: 4945; P9BE: # %bb.0: # %entry 4946; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 4947; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 4948; P9BE-NEXT: lxv v2, 0(r3) 4949; P9BE-NEXT: blr 4950; 4951; P9LE-LABEL: spltConst32kull: 4952; P9LE: # %bb.0: # %entry 4953; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 4954; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 4955; P9LE-NEXT: lxv v2, 0(r3) 4956; P9LE-NEXT: blr 4957; 4958; P8BE-LABEL: spltConst32kull: 4959; P8BE: # %bb.0: # %entry 4960; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 4961; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l 4962; P8BE-NEXT: lxvd2x v2, 0, r3 4963; P8BE-NEXT: blr 4964; 4965; P8LE-LABEL: spltConst32kull: 4966; P8LE: # %bb.0: # %entry 4967; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha 4968; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l 4969; P8LE-NEXT: lxvd2x v2, 0, r3 4970; P8LE-NEXT: blr 4971entry: 4972 ret <2 x i64> <i64 65535, i64 65535> 4973} 4974 4975define <2 x i64> @fromRegsull(i64 %a, i64 %b) { 4976; P9BE-LABEL: fromRegsull: 4977; P9BE: # %bb.0: # %entry 4978; P9BE-NEXT: mtvsrdd v2, r3, r4 4979; P9BE-NEXT: blr 4980; 4981; P9LE-LABEL: fromRegsull: 4982; P9LE: # %bb.0: # %entry 4983; P9LE-NEXT: mtvsrdd v2, r4, r3 4984; P9LE-NEXT: blr 4985; 4986; P8BE-LABEL: fromRegsull: 4987; P8BE: # %bb.0: # %entry 4988; P8BE-NEXT: mtfprd f0, r4 4989; P8BE-NEXT: mtfprd f1, r3 4990; P8BE-NEXT: xxmrghd v2, vs1, vs0 4991; P8BE-NEXT: blr 4992; 4993; P8LE-LABEL: fromRegsull: 4994; P8LE: # %bb.0: # %entry 4995; P8LE-NEXT: mtfprd f0, r3 4996; P8LE-NEXT: mtfprd f1, r4 4997; P8LE-NEXT: xxmrghd v2, vs1, vs0 4998; P8LE-NEXT: blr 4999entry: 5000 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 5001 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 5002 ret <2 x i64> %vecinit1 5003} 5004 5005define <2 x i64> @fromDiffConstsull() { 5006; P9BE-LABEL: fromDiffConstsull: 5007; P9BE: # %bb.0: # %entry 5008; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5009; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5010; P9BE-NEXT: lxv v2, 0(r3) 5011; P9BE-NEXT: blr 5012; 5013; P9LE-LABEL: fromDiffConstsull: 5014; P9LE: # %bb.0: # %entry 5015; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5016; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5017; P9LE-NEXT: lxv v2, 0(r3) 5018; P9LE-NEXT: blr 5019; 5020; P8BE-LABEL: fromDiffConstsull: 5021; P8BE: # %bb.0: # %entry 5022; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5023; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5024; P8BE-NEXT: lxvd2x v2, 0, r3 5025; P8BE-NEXT: blr 5026; 5027; P8LE-LABEL: fromDiffConstsull: 5028; P8LE: # %bb.0: # %entry 5029; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha 5030; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l 5031; P8LE-NEXT: lxvd2x vs0, 0, r3 5032; P8LE-NEXT: xxswapd v2, vs0 5033; P8LE-NEXT: blr 5034entry: 5035 ret <2 x i64> <i64 242, i64 -113> 5036} 5037 5038define <2 x i64> @fromDiffMemConsAull(ptr nocapture readonly %arr) { 5039; P9BE-LABEL: fromDiffMemConsAull: 5040; P9BE: # %bb.0: # %entry 5041; P9BE-NEXT: lxv v2, 0(r3) 5042; P9BE-NEXT: blr 5043; 5044; P9LE-LABEL: fromDiffMemConsAull: 5045; P9LE: # %bb.0: # %entry 5046; P9LE-NEXT: lxv v2, 0(r3) 5047; P9LE-NEXT: blr 5048; 5049; P8BE-LABEL: fromDiffMemConsAull: 5050; P8BE: # %bb.0: # %entry 5051; P8BE-NEXT: lxvd2x v2, 0, r3 5052; P8BE-NEXT: blr 5053; 5054; P8LE-LABEL: fromDiffMemConsAull: 5055; P8LE: # %bb.0: # %entry 5056; P8LE-NEXT: lxvd2x vs0, 0, r3 5057; P8LE-NEXT: xxswapd v2, vs0 5058; P8LE-NEXT: blr 5059entry: 5060 %0 = load i64, ptr %arr, align 8 5061 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5062 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 1 5063 %1 = load i64, ptr %arrayidx1, align 8 5064 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5065 ret <2 x i64> %vecinit2 5066} 5067 5068define <2 x i64> @fromDiffMemConsDull(ptr nocapture readonly %arr) { 5069; P9BE-LABEL: fromDiffMemConsDull: 5070; P9BE: # %bb.0: # %entry 5071; P9BE-NEXT: lxv v2, 16(r3) 5072; P9BE-NEXT: xxswapd v2, v2 5073; P9BE-NEXT: blr 5074; 5075; P9LE-LABEL: fromDiffMemConsDull: 5076; P9LE: # %bb.0: # %entry 5077; P9LE-NEXT: addi r3, r3, 16 5078; P9LE-NEXT: lxvd2x v2, 0, r3 5079; P9LE-NEXT: blr 5080; 5081; P8BE-LABEL: fromDiffMemConsDull: 5082; P8BE: # %bb.0: # %entry 5083; P8BE-NEXT: addi r3, r3, 16 5084; P8BE-NEXT: lxvd2x v2, 0, r3 5085; P8BE-NEXT: xxswapd v2, v2 5086; P8BE-NEXT: blr 5087; 5088; P8LE-LABEL: fromDiffMemConsDull: 5089; P8LE: # %bb.0: # %entry 5090; P8LE-NEXT: addi r3, r3, 16 5091; P8LE-NEXT: lxvd2x v2, 0, r3 5092; P8LE-NEXT: blr 5093entry: 5094 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 3 5095 %0 = load i64, ptr %arrayidx, align 8 5096 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5097 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 2 5098 %1 = load i64, ptr %arrayidx1, align 8 5099 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5100 ret <2 x i64> %vecinit2 5101} 5102 5103define <2 x i64> @fromDiffMemVarAull(ptr nocapture readonly %arr, i32 signext %elem) { 5104; P9BE-LABEL: fromDiffMemVarAull: 5105; P9BE: # %bb.0: # %entry 5106; P9BE-NEXT: sldi r4, r4, 3 5107; P9BE-NEXT: lxvx v2, r3, r4 5108; P9BE-NEXT: blr 5109; 5110; P9LE-LABEL: fromDiffMemVarAull: 5111; P9LE: # %bb.0: # %entry 5112; P9LE-NEXT: sldi r4, r4, 3 5113; P9LE-NEXT: lxvx v2, r3, r4 5114; P9LE-NEXT: blr 5115; 5116; P8BE-LABEL: fromDiffMemVarAull: 5117; P8BE: # %bb.0: # %entry 5118; P8BE-NEXT: sldi r4, r4, 3 5119; P8BE-NEXT: lxvd2x v2, r3, r4 5120; P8BE-NEXT: blr 5121; 5122; P8LE-LABEL: fromDiffMemVarAull: 5123; P8LE: # %bb.0: # %entry 5124; P8LE-NEXT: sldi r4, r4, 3 5125; P8LE-NEXT: lxvd2x vs0, r3, r4 5126; P8LE-NEXT: xxswapd v2, vs0 5127; P8LE-NEXT: blr 5128entry: 5129 %idxprom = sext i32 %elem to i64 5130 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom 5131 %0 = load i64, ptr %arrayidx, align 8 5132 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5133 %add = add nsw i32 %elem, 1 5134 %idxprom1 = sext i32 %add to i64 5135 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1 5136 %1 = load i64, ptr %arrayidx2, align 8 5137 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5138 ret <2 x i64> %vecinit3 5139} 5140 5141define <2 x i64> @fromDiffMemVarDull(ptr nocapture readonly %arr, i32 signext %elem) { 5142; P9BE-LABEL: fromDiffMemVarDull: 5143; P9BE: # %bb.0: # %entry 5144; P9BE-NEXT: sldi r4, r4, 3 5145; P9BE-NEXT: add r3, r3, r4 5146; P9BE-NEXT: li r4, -8 5147; P9BE-NEXT: lxvx v2, r3, r4 5148; P9BE-NEXT: xxswapd v2, v2 5149; P9BE-NEXT: blr 5150; 5151; P9LE-LABEL: fromDiffMemVarDull: 5152; P9LE: # %bb.0: # %entry 5153; P9LE-NEXT: sldi r4, r4, 3 5154; P9LE-NEXT: add r3, r3, r4 5155; P9LE-NEXT: addi r3, r3, -8 5156; P9LE-NEXT: lxvd2x v2, 0, r3 5157; P9LE-NEXT: blr 5158; 5159; P8BE-LABEL: fromDiffMemVarDull: 5160; P8BE: # %bb.0: # %entry 5161; P8BE-NEXT: sldi r4, r4, 3 5162; P8BE-NEXT: add r3, r3, r4 5163; P8BE-NEXT: addi r3, r3, -8 5164; P8BE-NEXT: lxvd2x v2, 0, r3 5165; P8BE-NEXT: xxswapd v2, v2 5166; P8BE-NEXT: blr 5167; 5168; P8LE-LABEL: fromDiffMemVarDull: 5169; P8LE: # %bb.0: # %entry 5170; P8LE-NEXT: sldi r4, r4, 3 5171; P8LE-NEXT: add r3, r3, r4 5172; P8LE-NEXT: addi r3, r3, -8 5173; P8LE-NEXT: lxvd2x v2, 0, r3 5174; P8LE-NEXT: blr 5175entry: 5176 %idxprom = sext i32 %elem to i64 5177 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom 5178 %0 = load i64, ptr %arrayidx, align 8 5179 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5180 %sub = add nsw i32 %elem, -1 5181 %idxprom1 = sext i32 %sub to i64 5182 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1 5183 %1 = load i64, ptr %arrayidx2, align 8 5184 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5185 ret <2 x i64> %vecinit3 5186} 5187 5188define <2 x i64> @fromRandMemConsull(ptr nocapture readonly %arr) { 5189; P9BE-LABEL: fromRandMemConsull: 5190; P9BE: # %bb.0: # %entry 5191; P9BE-NEXT: ld r4, 32(r3) 5192; P9BE-NEXT: ld r3, 144(r3) 5193; P9BE-NEXT: mtvsrdd v2, r4, r3 5194; P9BE-NEXT: blr 5195; 5196; P9LE-LABEL: fromRandMemConsull: 5197; P9LE: # %bb.0: # %entry 5198; P9LE-NEXT: ld r4, 32(r3) 5199; P9LE-NEXT: ld r3, 144(r3) 5200; P9LE-NEXT: mtvsrdd v2, r3, r4 5201; P9LE-NEXT: blr 5202; 5203; P8BE-LABEL: fromRandMemConsull: 5204; P8BE: # %bb.0: # %entry 5205; P8BE-NEXT: ld r4, 32(r3) 5206; P8BE-NEXT: ld r3, 144(r3) 5207; P8BE-NEXT: mtfprd f0, r3 5208; P8BE-NEXT: mtfprd f1, r4 5209; P8BE-NEXT: xxmrghd v2, vs1, vs0 5210; P8BE-NEXT: blr 5211; 5212; P8LE-LABEL: fromRandMemConsull: 5213; P8LE: # %bb.0: # %entry 5214; P8LE-NEXT: ld r4, 32(r3) 5215; P8LE-NEXT: ld r3, 144(r3) 5216; P8LE-NEXT: mtfprd f0, r4 5217; P8LE-NEXT: mtfprd f1, r3 5218; P8LE-NEXT: xxmrghd v2, vs1, vs0 5219; P8LE-NEXT: blr 5220entry: 5221 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 4 5222 %0 = load i64, ptr %arrayidx, align 8 5223 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5224 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 18 5225 %1 = load i64, ptr %arrayidx1, align 8 5226 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5227 ret <2 x i64> %vecinit2 5228} 5229 5230define <2 x i64> @fromRandMemVarull(ptr nocapture readonly %arr, i32 signext %elem) { 5231; P9BE-LABEL: fromRandMemVarull: 5232; P9BE: # %bb.0: # %entry 5233; P9BE-NEXT: sldi r4, r4, 3 5234; P9BE-NEXT: add r3, r3, r4 5235; P9BE-NEXT: ld r4, 32(r3) 5236; P9BE-NEXT: ld r3, 8(r3) 5237; P9BE-NEXT: mtvsrdd v2, r4, r3 5238; P9BE-NEXT: blr 5239; 5240; P9LE-LABEL: fromRandMemVarull: 5241; P9LE: # %bb.0: # %entry 5242; P9LE-NEXT: sldi r4, r4, 3 5243; P9LE-NEXT: add r3, r3, r4 5244; P9LE-NEXT: ld r4, 32(r3) 5245; P9LE-NEXT: ld r3, 8(r3) 5246; P9LE-NEXT: mtvsrdd v2, r3, r4 5247; P9LE-NEXT: blr 5248; 5249; P8BE-LABEL: fromRandMemVarull: 5250; P8BE: # %bb.0: # %entry 5251; P8BE-NEXT: sldi r4, r4, 3 5252; P8BE-NEXT: add r3, r3, r4 5253; P8BE-NEXT: ld r4, 32(r3) 5254; P8BE-NEXT: ld r3, 8(r3) 5255; P8BE-NEXT: mtfprd f0, r3 5256; P8BE-NEXT: mtfprd f1, r4 5257; P8BE-NEXT: xxmrghd v2, vs1, vs0 5258; P8BE-NEXT: blr 5259; 5260; P8LE-LABEL: fromRandMemVarull: 5261; P8LE: # %bb.0: # %entry 5262; P8LE-NEXT: sldi r4, r4, 3 5263; P8LE-NEXT: add r3, r3, r4 5264; P8LE-NEXT: ld r4, 32(r3) 5265; P8LE-NEXT: ld r3, 8(r3) 5266; P8LE-NEXT: mtfprd f0, r4 5267; P8LE-NEXT: mtfprd f1, r3 5268; P8LE-NEXT: xxmrghd v2, vs1, vs0 5269; P8LE-NEXT: blr 5270entry: 5271 %add = add nsw i32 %elem, 4 5272 %idxprom = sext i32 %add to i64 5273 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom 5274 %0 = load i64, ptr %arrayidx, align 8 5275 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 5276 %add1 = add nsw i32 %elem, 1 5277 %idxprom2 = sext i32 %add1 to i64 5278 %arrayidx3 = getelementptr inbounds i64, ptr %arr, i64 %idxprom2 5279 %1 = load i64, ptr %arrayidx3, align 8 5280 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1 5281 ret <2 x i64> %vecinit4 5282} 5283 5284define <2 x i64> @spltRegValull(i64 %val) { 5285; P9BE-LABEL: spltRegValull: 5286; P9BE: # %bb.0: # %entry 5287; P9BE-NEXT: mtvsrdd v2, r3, r3 5288; P9BE-NEXT: blr 5289; 5290; P9LE-LABEL: spltRegValull: 5291; P9LE: # %bb.0: # %entry 5292; P9LE-NEXT: mtvsrdd v2, r3, r3 5293; P9LE-NEXT: blr 5294; 5295; P8BE-LABEL: spltRegValull: 5296; P8BE: # %bb.0: # %entry 5297; P8BE-NEXT: mtfprd f0, r3 5298; P8BE-NEXT: xxspltd v2, vs0, 0 5299; P8BE-NEXT: blr 5300; 5301; P8LE-LABEL: spltRegValull: 5302; P8LE: # %bb.0: # %entry 5303; P8LE-NEXT: mtfprd f0, r3 5304; P8LE-NEXT: xxspltd v2, vs0, 0 5305; P8LE-NEXT: blr 5306entry: 5307 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 5308 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5309 ret <2 x i64> %splat.splat 5310} 5311 5312define <2 x i64> @spltMemValull(ptr nocapture readonly %ptr) { 5313; P9BE-LABEL: spltMemValull: 5314; P9BE: # %bb.0: # %entry 5315; P9BE-NEXT: lxvdsx v2, 0, r3 5316; P9BE-NEXT: blr 5317; 5318; P9LE-LABEL: spltMemValull: 5319; P9LE: # %bb.0: # %entry 5320; P9LE-NEXT: lxvdsx v2, 0, r3 5321; P9LE-NEXT: blr 5322; 5323; P8BE-LABEL: spltMemValull: 5324; P8BE: # %bb.0: # %entry 5325; P8BE-NEXT: lxvdsx v2, 0, r3 5326; P8BE-NEXT: blr 5327; 5328; P8LE-LABEL: spltMemValull: 5329; P8LE: # %bb.0: # %entry 5330; P8LE-NEXT: lxvdsx v2, 0, r3 5331; P8LE-NEXT: blr 5332entry: 5333 %0 = load i64, ptr %ptr, align 8 5334 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 5335 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5336 ret <2 x i64> %splat.splat 5337} 5338 5339define <2 x i64> @spltCnstConvftoull() { 5340; P9BE-LABEL: spltCnstConvftoull: 5341; P9BE: # %bb.0: # %entry 5342; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5343; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5344; P9BE-NEXT: lxv v2, 0(r3) 5345; P9BE-NEXT: blr 5346; 5347; P9LE-LABEL: spltCnstConvftoull: 5348; P9LE: # %bb.0: # %entry 5349; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5350; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5351; P9LE-NEXT: lxv v2, 0(r3) 5352; P9LE-NEXT: blr 5353; 5354; P8BE-LABEL: spltCnstConvftoull: 5355; P8BE: # %bb.0: # %entry 5356; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5357; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5358; P8BE-NEXT: lxvd2x v2, 0, r3 5359; P8BE-NEXT: blr 5360; 5361; P8LE-LABEL: spltCnstConvftoull: 5362; P8LE: # %bb.0: # %entry 5363; P8LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha 5364; P8LE-NEXT: addi r3, r3, .LCPI110_0@toc@l 5365; P8LE-NEXT: lxvd2x v2, 0, r3 5366; P8LE-NEXT: blr 5367entry: 5368 ret <2 x i64> <i64 4, i64 4> 5369} 5370 5371define <2 x i64> @fromRegsConvftoull(float %a, float %b) { 5372; P9BE-LABEL: fromRegsConvftoull: 5373; P9BE: # %bb.0: # %entry 5374; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5375; P9BE-NEXT: xvcvdpuxds v2, vs0 5376; P9BE-NEXT: blr 5377; 5378; P9LE-LABEL: fromRegsConvftoull: 5379; P9LE: # %bb.0: # %entry 5380; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5381; P9LE-NEXT: xvcvdpuxds v2, vs0 5382; P9LE-NEXT: blr 5383; 5384; P8BE-LABEL: fromRegsConvftoull: 5385; P8BE: # %bb.0: # %entry 5386; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5387; P8BE-NEXT: xvcvdpuxds v2, vs0 5388; P8BE-NEXT: blr 5389; 5390; P8LE-LABEL: fromRegsConvftoull: 5391; P8LE: # %bb.0: # %entry 5392; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5393; P8LE-NEXT: xvcvdpuxds v2, vs0 5394; P8LE-NEXT: blr 5395entry: 5396 %conv = fptoui float %a to i64 5397 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5398 %conv1 = fptoui float %b to i64 5399 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5400 ret <2 x i64> %vecinit2 5401} 5402 5403define <2 x i64> @fromDiffConstsConvftoull() { 5404; P9BE-LABEL: fromDiffConstsConvftoull: 5405; P9BE: # %bb.0: # %entry 5406; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5407; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5408; P9BE-NEXT: lxv v2, 0(r3) 5409; P9BE-NEXT: blr 5410; 5411; P9LE-LABEL: fromDiffConstsConvftoull: 5412; P9LE: # %bb.0: # %entry 5413; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5414; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5415; P9LE-NEXT: lxv v2, 0(r3) 5416; P9LE-NEXT: blr 5417; 5418; P8BE-LABEL: fromDiffConstsConvftoull: 5419; P8BE: # %bb.0: # %entry 5420; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5421; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5422; P8BE-NEXT: lxvd2x v2, 0, r3 5423; P8BE-NEXT: blr 5424; 5425; P8LE-LABEL: fromDiffConstsConvftoull: 5426; P8LE: # %bb.0: # %entry 5427; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha 5428; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l 5429; P8LE-NEXT: lxvd2x vs0, 0, r3 5430; P8LE-NEXT: xxswapd v2, vs0 5431; P8LE-NEXT: blr 5432entry: 5433 ret <2 x i64> <i64 24, i64 234> 5434} 5435 5436define <2 x i64> @fromDiffMemConsAConvftoull(ptr nocapture readonly %ptr) { 5437; P9BE-LABEL: fromDiffMemConsAConvftoull: 5438; P9BE: # %bb.0: # %entry 5439; P9BE-NEXT: lfs f0, 0(r3) 5440; P9BE-NEXT: lfs f1, 4(r3) 5441; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5442; P9BE-NEXT: xvcvdpuxds v2, vs0 5443; P9BE-NEXT: blr 5444; 5445; P9LE-LABEL: fromDiffMemConsAConvftoull: 5446; P9LE: # %bb.0: # %entry 5447; P9LE-NEXT: lfs f0, 0(r3) 5448; P9LE-NEXT: lfs f1, 4(r3) 5449; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5450; P9LE-NEXT: xvcvdpuxds v2, vs0 5451; P9LE-NEXT: blr 5452; 5453; P8BE-LABEL: fromDiffMemConsAConvftoull: 5454; P8BE: # %bb.0: # %entry 5455; P8BE-NEXT: lfs f0, 0(r3) 5456; P8BE-NEXT: lfs f1, 4(r3) 5457; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5458; P8BE-NEXT: xvcvdpuxds v2, vs0 5459; P8BE-NEXT: blr 5460; 5461; P8LE-LABEL: fromDiffMemConsAConvftoull: 5462; P8LE: # %bb.0: # %entry 5463; P8LE-NEXT: lfs f0, 0(r3) 5464; P8LE-NEXT: lfs f1, 4(r3) 5465; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5466; P8LE-NEXT: xvcvdpuxds v2, vs0 5467; P8LE-NEXT: blr 5468entry: 5469 %0 = load float, ptr %ptr, align 4 5470 %conv = fptoui float %0 to i64 5471 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5472 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 1 5473 %1 = load float, ptr %arrayidx1, align 4 5474 %conv2 = fptoui float %1 to i64 5475 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5476 ret <2 x i64> %vecinit3 5477} 5478 5479define <2 x i64> @fromDiffMemConsDConvftoull(ptr nocapture readonly %ptr) { 5480; P9BE-LABEL: fromDiffMemConsDConvftoull: 5481; P9BE: # %bb.0: # %entry 5482; P9BE-NEXT: lfs f0, 12(r3) 5483; P9BE-NEXT: lfs f1, 8(r3) 5484; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5485; P9BE-NEXT: xvcvdpuxds v2, vs0 5486; P9BE-NEXT: blr 5487; 5488; P9LE-LABEL: fromDiffMemConsDConvftoull: 5489; P9LE: # %bb.0: # %entry 5490; P9LE-NEXT: lfs f0, 12(r3) 5491; P9LE-NEXT: lfs f1, 8(r3) 5492; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5493; P9LE-NEXT: xvcvdpuxds v2, vs0 5494; P9LE-NEXT: blr 5495; 5496; P8BE-LABEL: fromDiffMemConsDConvftoull: 5497; P8BE: # %bb.0: # %entry 5498; P8BE-NEXT: lfs f0, 12(r3) 5499; P8BE-NEXT: lfs f1, 8(r3) 5500; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5501; P8BE-NEXT: xvcvdpuxds v2, vs0 5502; P8BE-NEXT: blr 5503; 5504; P8LE-LABEL: fromDiffMemConsDConvftoull: 5505; P8LE: # %bb.0: # %entry 5506; P8LE-NEXT: lfs f0, 12(r3) 5507; P8LE-NEXT: lfs f1, 8(r3) 5508; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5509; P8LE-NEXT: xvcvdpuxds v2, vs0 5510; P8LE-NEXT: blr 5511entry: 5512 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3 5513 %0 = load float, ptr %arrayidx, align 4 5514 %conv = fptoui float %0 to i64 5515 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5516 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2 5517 %1 = load float, ptr %arrayidx1, align 4 5518 %conv2 = fptoui float %1 to i64 5519 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5520 ret <2 x i64> %vecinit3 5521} 5522 5523define <2 x i64> @fromDiffMemVarAConvftoull(ptr nocapture readonly %arr, i32 signext %elem) { 5524; P9BE-LABEL: fromDiffMemVarAConvftoull: 5525; P9BE: # %bb.0: # %entry 5526; P9BE-NEXT: sldi r4, r4, 2 5527; P9BE-NEXT: lfsux f0, r3, r4 5528; P9BE-NEXT: lfs f1, 4(r3) 5529; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5530; P9BE-NEXT: xvcvdpuxds v2, vs0 5531; P9BE-NEXT: blr 5532; 5533; P9LE-LABEL: fromDiffMemVarAConvftoull: 5534; P9LE: # %bb.0: # %entry 5535; P9LE-NEXT: sldi r4, r4, 2 5536; P9LE-NEXT: lfsux f0, r3, r4 5537; P9LE-NEXT: lfs f1, 4(r3) 5538; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5539; P9LE-NEXT: xvcvdpuxds v2, vs0 5540; P9LE-NEXT: blr 5541; 5542; P8BE-LABEL: fromDiffMemVarAConvftoull: 5543; P8BE: # %bb.0: # %entry 5544; P8BE-NEXT: sldi r4, r4, 2 5545; P8BE-NEXT: lfsux f0, r3, r4 5546; P8BE-NEXT: lfs f1, 4(r3) 5547; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5548; P8BE-NEXT: xvcvdpuxds v2, vs0 5549; P8BE-NEXT: blr 5550; 5551; P8LE-LABEL: fromDiffMemVarAConvftoull: 5552; P8LE: # %bb.0: # %entry 5553; P8LE-NEXT: sldi r4, r4, 2 5554; P8LE-NEXT: lfsux f0, r3, r4 5555; P8LE-NEXT: lfs f1, 4(r3) 5556; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5557; P8LE-NEXT: xvcvdpuxds v2, vs0 5558; P8LE-NEXT: blr 5559entry: 5560 %idxprom = sext i32 %elem to i64 5561 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom 5562 %0 = load float, ptr %arrayidx, align 4 5563 %conv = fptoui float %0 to i64 5564 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5565 %add = add nsw i32 %elem, 1 5566 %idxprom1 = sext i32 %add to i64 5567 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1 5568 %1 = load float, ptr %arrayidx2, align 4 5569 %conv3 = fptoui float %1 to i64 5570 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5571 ret <2 x i64> %vecinit4 5572} 5573 5574define <2 x i64> @fromDiffMemVarDConvftoull(ptr nocapture readonly %arr, i32 signext %elem) { 5575; P9BE-LABEL: fromDiffMemVarDConvftoull: 5576; P9BE: # %bb.0: # %entry 5577; P9BE-NEXT: sldi r4, r4, 2 5578; P9BE-NEXT: lfsux f0, r3, r4 5579; P9BE-NEXT: lfs f1, -4(r3) 5580; P9BE-NEXT: xxmrghd vs0, vs0, vs1 5581; P9BE-NEXT: xvcvdpuxds v2, vs0 5582; P9BE-NEXT: blr 5583; 5584; P9LE-LABEL: fromDiffMemVarDConvftoull: 5585; P9LE: # %bb.0: # %entry 5586; P9LE-NEXT: sldi r4, r4, 2 5587; P9LE-NEXT: lfsux f0, r3, r4 5588; P9LE-NEXT: lfs f1, -4(r3) 5589; P9LE-NEXT: xxmrghd vs0, vs1, vs0 5590; P9LE-NEXT: xvcvdpuxds v2, vs0 5591; P9LE-NEXT: blr 5592; 5593; P8BE-LABEL: fromDiffMemVarDConvftoull: 5594; P8BE: # %bb.0: # %entry 5595; P8BE-NEXT: sldi r4, r4, 2 5596; P8BE-NEXT: lfsux f0, r3, r4 5597; P8BE-NEXT: lfs f1, -4(r3) 5598; P8BE-NEXT: xxmrghd vs0, vs0, vs1 5599; P8BE-NEXT: xvcvdpuxds v2, vs0 5600; P8BE-NEXT: blr 5601; 5602; P8LE-LABEL: fromDiffMemVarDConvftoull: 5603; P8LE: # %bb.0: # %entry 5604; P8LE-NEXT: sldi r4, r4, 2 5605; P8LE-NEXT: lfsux f0, r3, r4 5606; P8LE-NEXT: lfs f1, -4(r3) 5607; P8LE-NEXT: xxmrghd vs0, vs1, vs0 5608; P8LE-NEXT: xvcvdpuxds v2, vs0 5609; P8LE-NEXT: blr 5610entry: 5611 %idxprom = sext i32 %elem to i64 5612 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom 5613 %0 = load float, ptr %arrayidx, align 4 5614 %conv = fptoui float %0 to i64 5615 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5616 %sub = add nsw i32 %elem, -1 5617 %idxprom1 = sext i32 %sub to i64 5618 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1 5619 %1 = load float, ptr %arrayidx2, align 4 5620 %conv3 = fptoui float %1 to i64 5621 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5622 ret <2 x i64> %vecinit4 5623} 5624 5625define <2 x i64> @spltRegValConvftoull(float %val) { 5626; P9BE-LABEL: spltRegValConvftoull: 5627; P9BE: # %bb.0: # %entry 5628; P9BE-NEXT: xscvdpuxds f0, f1 5629; P9BE-NEXT: xxspltd v2, f0, 0 5630; P9BE-NEXT: blr 5631; 5632; P9LE-LABEL: spltRegValConvftoull: 5633; P9LE: # %bb.0: # %entry 5634; P9LE-NEXT: xscvdpuxds f0, f1 5635; P9LE-NEXT: xxspltd v2, f0, 0 5636; P9LE-NEXT: blr 5637; 5638; P8BE-LABEL: spltRegValConvftoull: 5639; P8BE: # %bb.0: # %entry 5640; P8BE-NEXT: xscvdpuxds f0, f1 5641; P8BE-NEXT: xxspltd v2, f0, 0 5642; P8BE-NEXT: blr 5643; 5644; P8LE-LABEL: spltRegValConvftoull: 5645; P8LE: # %bb.0: # %entry 5646; P8LE-NEXT: xscvdpuxds f0, f1 5647; P8LE-NEXT: xxspltd v2, f0, 0 5648; P8LE-NEXT: blr 5649entry: 5650 %conv = fptoui float %val to i64 5651 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5652 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5653 ret <2 x i64> %splat.splat 5654} 5655 5656define <2 x i64> @spltMemValConvftoull(ptr nocapture readonly %ptr) { 5657; P9BE-LABEL: spltMemValConvftoull: 5658; P9BE: # %bb.0: # %entry 5659; P9BE-NEXT: lfs f0, 0(r3) 5660; P9BE-NEXT: xscvdpuxds f0, f0 5661; P9BE-NEXT: xxspltd v2, f0, 0 5662; P9BE-NEXT: blr 5663; 5664; P9LE-LABEL: spltMemValConvftoull: 5665; P9LE: # %bb.0: # %entry 5666; P9LE-NEXT: lfs f0, 0(r3) 5667; P9LE-NEXT: xscvdpuxds f0, f0 5668; P9LE-NEXT: xxspltd v2, vs0, 0 5669; P9LE-NEXT: blr 5670; 5671; P8BE-LABEL: spltMemValConvftoull: 5672; P8BE: # %bb.0: # %entry 5673; P8BE-NEXT: lfsx f0, 0, r3 5674; P8BE-NEXT: xscvdpuxds f0, f0 5675; P8BE-NEXT: xxspltd v2, f0, 0 5676; P8BE-NEXT: blr 5677; 5678; P8LE-LABEL: spltMemValConvftoull: 5679; P8LE: # %bb.0: # %entry 5680; P8LE-NEXT: lfsx f0, 0, r3 5681; P8LE-NEXT: xscvdpuxds f0, f0 5682; P8LE-NEXT: xxspltd v2, vs0, 0 5683; P8LE-NEXT: blr 5684entry: 5685 %0 = load float, ptr %ptr, align 4 5686 %conv = fptoui float %0 to i64 5687 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5688 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5689 ret <2 x i64> %splat.splat 5690} 5691 5692define <2 x i64> @spltCnstConvdtoull() { 5693; P9BE-LABEL: spltCnstConvdtoull: 5694; P9BE: # %bb.0: # %entry 5695; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5696; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5697; P9BE-NEXT: lxv v2, 0(r3) 5698; P9BE-NEXT: blr 5699; 5700; P9LE-LABEL: spltCnstConvdtoull: 5701; P9LE: # %bb.0: # %entry 5702; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5703; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5704; P9LE-NEXT: lxv v2, 0(r3) 5705; P9LE-NEXT: blr 5706; 5707; P8BE-LABEL: spltCnstConvdtoull: 5708; P8BE: # %bb.0: # %entry 5709; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5710; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5711; P8BE-NEXT: lxvd2x v2, 0, r3 5712; P8BE-NEXT: blr 5713; 5714; P8LE-LABEL: spltCnstConvdtoull: 5715; P8LE: # %bb.0: # %entry 5716; P8LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha 5717; P8LE-NEXT: addi r3, r3, .LCPI119_0@toc@l 5718; P8LE-NEXT: lxvd2x v2, 0, r3 5719; P8LE-NEXT: blr 5720entry: 5721 ret <2 x i64> <i64 4, i64 4> 5722} 5723 5724define <2 x i64> @fromRegsConvdtoull(double %a, double %b) { 5725; P9BE-LABEL: fromRegsConvdtoull: 5726; P9BE: # %bb.0: # %entry 5727; P9BE-NEXT: xxmrghd vs0, vs1, vs2 5728; P9BE-NEXT: xvcvdpuxds v2, vs0 5729; P9BE-NEXT: blr 5730; 5731; P9LE-LABEL: fromRegsConvdtoull: 5732; P9LE: # %bb.0: # %entry 5733; P9LE-NEXT: xxmrghd vs0, vs2, vs1 5734; P9LE-NEXT: xvcvdpuxds v2, vs0 5735; P9LE-NEXT: blr 5736; 5737; P8BE-LABEL: fromRegsConvdtoull: 5738; P8BE: # %bb.0: # %entry 5739; P8BE-NEXT: xxmrghd vs0, vs1, vs2 5740; P8BE-NEXT: xvcvdpuxds v2, vs0 5741; P8BE-NEXT: blr 5742; 5743; P8LE-LABEL: fromRegsConvdtoull: 5744; P8LE: # %bb.0: # %entry 5745; P8LE-NEXT: xxmrghd vs0, vs2, vs1 5746; P8LE-NEXT: xvcvdpuxds v2, vs0 5747; P8LE-NEXT: blr 5748entry: 5749 %conv = fptoui double %a to i64 5750 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5751 %conv1 = fptoui double %b to i64 5752 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1 5753 ret <2 x i64> %vecinit2 5754} 5755 5756define <2 x i64> @fromDiffConstsConvdtoull() { 5757; P9BE-LABEL: fromDiffConstsConvdtoull: 5758; P9BE: # %bb.0: # %entry 5759; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5760; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5761; P9BE-NEXT: lxv v2, 0(r3) 5762; P9BE-NEXT: blr 5763; 5764; P9LE-LABEL: fromDiffConstsConvdtoull: 5765; P9LE: # %bb.0: # %entry 5766; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5767; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5768; P9LE-NEXT: lxv v2, 0(r3) 5769; P9LE-NEXT: blr 5770; 5771; P8BE-LABEL: fromDiffConstsConvdtoull: 5772; P8BE: # %bb.0: # %entry 5773; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5774; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5775; P8BE-NEXT: lxvd2x v2, 0, r3 5776; P8BE-NEXT: blr 5777; 5778; P8LE-LABEL: fromDiffConstsConvdtoull: 5779; P8LE: # %bb.0: # %entry 5780; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha 5781; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l 5782; P8LE-NEXT: lxvd2x vs0, 0, r3 5783; P8LE-NEXT: xxswapd v2, vs0 5784; P8LE-NEXT: blr 5785entry: 5786 ret <2 x i64> <i64 24, i64 234> 5787} 5788 5789define <2 x i64> @fromDiffMemConsAConvdtoull(ptr nocapture readonly %ptr) { 5790; P9BE-LABEL: fromDiffMemConsAConvdtoull: 5791; P9BE: # %bb.0: # %entry 5792; P9BE-NEXT: lxv vs0, 0(r3) 5793; P9BE-NEXT: xvcvdpuxds v2, vs0 5794; P9BE-NEXT: blr 5795; 5796; P9LE-LABEL: fromDiffMemConsAConvdtoull: 5797; P9LE: # %bb.0: # %entry 5798; P9LE-NEXT: lxv vs0, 0(r3) 5799; P9LE-NEXT: xvcvdpuxds v2, vs0 5800; P9LE-NEXT: blr 5801; 5802; P8BE-LABEL: fromDiffMemConsAConvdtoull: 5803; P8BE: # %bb.0: # %entry 5804; P8BE-NEXT: lxvd2x vs0, 0, r3 5805; P8BE-NEXT: xvcvdpuxds v2, vs0 5806; P8BE-NEXT: blr 5807; 5808; P8LE-LABEL: fromDiffMemConsAConvdtoull: 5809; P8LE: # %bb.0: # %entry 5810; P8LE-NEXT: lxvd2x vs0, 0, r3 5811; P8LE-NEXT: xxswapd vs0, vs0 5812; P8LE-NEXT: xvcvdpuxds v2, vs0 5813; P8LE-NEXT: blr 5814entry: 5815 %0 = load <2 x double>, ptr %ptr, align 8 5816 %1 = fptoui <2 x double> %0 to <2 x i64> 5817 ret <2 x i64> %1 5818} 5819 5820define <2 x i64> @fromDiffMemConsDConvdtoull(ptr nocapture readonly %ptr) { 5821; P9BE-LABEL: fromDiffMemConsDConvdtoull: 5822; P9BE: # %bb.0: # %entry 5823; P9BE-NEXT: lxv vs0, 16(r3) 5824; P9BE-NEXT: xxswapd vs0, vs0 5825; P9BE-NEXT: xvcvdpuxds v2, vs0 5826; P9BE-NEXT: blr 5827; 5828; P9LE-LABEL: fromDiffMemConsDConvdtoull: 5829; P9LE: # %bb.0: # %entry 5830; P9LE-NEXT: addi r3, r3, 16 5831; P9LE-NEXT: lxvd2x vs0, 0, r3 5832; P9LE-NEXT: xvcvdpuxds v2, vs0 5833; P9LE-NEXT: blr 5834; 5835; P8BE-LABEL: fromDiffMemConsDConvdtoull: 5836; P8BE: # %bb.0: # %entry 5837; P8BE-NEXT: addi r3, r3, 16 5838; P8BE-NEXT: lxvd2x vs0, 0, r3 5839; P8BE-NEXT: xxswapd vs0, vs0 5840; P8BE-NEXT: xvcvdpuxds v2, vs0 5841; P8BE-NEXT: blr 5842; 5843; P8LE-LABEL: fromDiffMemConsDConvdtoull: 5844; P8LE: # %bb.0: # %entry 5845; P8LE-NEXT: addi r3, r3, 16 5846; P8LE-NEXT: lxvd2x vs0, 0, r3 5847; P8LE-NEXT: xvcvdpuxds v2, vs0 5848; P8LE-NEXT: blr 5849entry: 5850 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3 5851 %0 = load double, ptr %arrayidx, align 8 5852 %conv = fptoui double %0 to i64 5853 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5854 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2 5855 %1 = load double, ptr %arrayidx1, align 8 5856 %conv2 = fptoui double %1 to i64 5857 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 5858 ret <2 x i64> %vecinit3 5859} 5860 5861define <2 x i64> @fromDiffMemVarAConvdtoull(ptr nocapture readonly %arr, i32 signext %elem) { 5862; P9BE-LABEL: fromDiffMemVarAConvdtoull: 5863; P9BE: # %bb.0: # %entry 5864; P9BE-NEXT: sldi r4, r4, 3 5865; P9BE-NEXT: lxvx vs0, r3, r4 5866; P9BE-NEXT: xvcvdpuxds v2, vs0 5867; P9BE-NEXT: blr 5868; 5869; P9LE-LABEL: fromDiffMemVarAConvdtoull: 5870; P9LE: # %bb.0: # %entry 5871; P9LE-NEXT: sldi r4, r4, 3 5872; P9LE-NEXT: lxvx vs0, r3, r4 5873; P9LE-NEXT: xvcvdpuxds v2, vs0 5874; P9LE-NEXT: blr 5875; 5876; P8BE-LABEL: fromDiffMemVarAConvdtoull: 5877; P8BE: # %bb.0: # %entry 5878; P8BE-NEXT: sldi r4, r4, 3 5879; P8BE-NEXT: lxvd2x vs0, r3, r4 5880; P8BE-NEXT: xvcvdpuxds v2, vs0 5881; P8BE-NEXT: blr 5882; 5883; P8LE-LABEL: fromDiffMemVarAConvdtoull: 5884; P8LE: # %bb.0: # %entry 5885; P8LE-NEXT: sldi r4, r4, 3 5886; P8LE-NEXT: lxvd2x vs0, r3, r4 5887; P8LE-NEXT: xxswapd vs0, vs0 5888; P8LE-NEXT: xvcvdpuxds v2, vs0 5889; P8LE-NEXT: blr 5890entry: 5891 %idxprom = sext i32 %elem to i64 5892 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom 5893 %0 = load double, ptr %arrayidx, align 8 5894 %conv = fptoui double %0 to i64 5895 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5896 %add = add nsw i32 %elem, 1 5897 %idxprom1 = sext i32 %add to i64 5898 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1 5899 %1 = load double, ptr %arrayidx2, align 8 5900 %conv3 = fptoui double %1 to i64 5901 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5902 ret <2 x i64> %vecinit4 5903} 5904 5905define <2 x i64> @fromDiffMemVarDConvdtoull(ptr nocapture readonly %arr, i32 signext %elem) { 5906; P9BE-LABEL: fromDiffMemVarDConvdtoull: 5907; P9BE: # %bb.0: # %entry 5908; P9BE-NEXT: sldi r4, r4, 3 5909; P9BE-NEXT: add r3, r3, r4 5910; P9BE-NEXT: li r4, -8 5911; P9BE-NEXT: lxvx vs0, r3, r4 5912; P9BE-NEXT: xxswapd vs0, vs0 5913; P9BE-NEXT: xvcvdpuxds v2, vs0 5914; P9BE-NEXT: blr 5915; 5916; P9LE-LABEL: fromDiffMemVarDConvdtoull: 5917; P9LE: # %bb.0: # %entry 5918; P9LE-NEXT: sldi r4, r4, 3 5919; P9LE-NEXT: add r3, r3, r4 5920; P9LE-NEXT: addi r3, r3, -8 5921; P9LE-NEXT: lxvd2x vs0, 0, r3 5922; P9LE-NEXT: xvcvdpuxds v2, vs0 5923; P9LE-NEXT: blr 5924; 5925; P8BE-LABEL: fromDiffMemVarDConvdtoull: 5926; P8BE: # %bb.0: # %entry 5927; P8BE-NEXT: sldi r4, r4, 3 5928; P8BE-NEXT: add r3, r3, r4 5929; P8BE-NEXT: addi r3, r3, -8 5930; P8BE-NEXT: lxvd2x vs0, 0, r3 5931; P8BE-NEXT: xxswapd vs0, vs0 5932; P8BE-NEXT: xvcvdpuxds v2, vs0 5933; P8BE-NEXT: blr 5934; 5935; P8LE-LABEL: fromDiffMemVarDConvdtoull: 5936; P8LE: # %bb.0: # %entry 5937; P8LE-NEXT: sldi r4, r4, 3 5938; P8LE-NEXT: add r3, r3, r4 5939; P8LE-NEXT: addi r3, r3, -8 5940; P8LE-NEXT: lxvd2x vs0, 0, r3 5941; P8LE-NEXT: xvcvdpuxds v2, vs0 5942; P8LE-NEXT: blr 5943entry: 5944 %idxprom = sext i32 %elem to i64 5945 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom 5946 %0 = load double, ptr %arrayidx, align 8 5947 %conv = fptoui double %0 to i64 5948 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 5949 %sub = add nsw i32 %elem, -1 5950 %idxprom1 = sext i32 %sub to i64 5951 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1 5952 %1 = load double, ptr %arrayidx2, align 8 5953 %conv3 = fptoui double %1 to i64 5954 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1 5955 ret <2 x i64> %vecinit4 5956} 5957 5958define <2 x i64> @spltRegValConvdtoull(double %val) { 5959; P9BE-LABEL: spltRegValConvdtoull: 5960; P9BE: # %bb.0: # %entry 5961; P9BE-NEXT: xscvdpuxds f0, f1 5962; P9BE-NEXT: xxspltd v2, vs0, 0 5963; P9BE-NEXT: blr 5964; 5965; P9LE-LABEL: spltRegValConvdtoull: 5966; P9LE: # %bb.0: # %entry 5967; P9LE-NEXT: xscvdpuxds f0, f1 5968; P9LE-NEXT: xxspltd v2, vs0, 0 5969; P9LE-NEXT: blr 5970; 5971; P8BE-LABEL: spltRegValConvdtoull: 5972; P8BE: # %bb.0: # %entry 5973; P8BE-NEXT: xscvdpuxds f0, f1 5974; P8BE-NEXT: xxspltd v2, vs0, 0 5975; P8BE-NEXT: blr 5976; 5977; P8LE-LABEL: spltRegValConvdtoull: 5978; P8LE: # %bb.0: # %entry 5979; P8LE-NEXT: xscvdpuxds f0, f1 5980; P8LE-NEXT: xxspltd v2, vs0, 0 5981; P8LE-NEXT: blr 5982entry: 5983 %conv = fptoui double %val to i64 5984 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 5985 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 5986 ret <2 x i64> %splat.splat 5987} 5988 5989define <2 x i64> @spltMemValConvdtoull(ptr nocapture readonly %ptr) { 5990; P9BE-LABEL: spltMemValConvdtoull: 5991; P9BE: # %bb.0: # %entry 5992; P9BE-NEXT: lxvdsx vs0, 0, r3 5993; P9BE-NEXT: xvcvdpuxds v2, vs0 5994; P9BE-NEXT: blr 5995; 5996; P9LE-LABEL: spltMemValConvdtoull: 5997; P9LE: # %bb.0: # %entry 5998; P9LE-NEXT: lxvdsx vs0, 0, r3 5999; P9LE-NEXT: xvcvdpuxds v2, vs0 6000; P9LE-NEXT: blr 6001; 6002; P8BE-LABEL: spltMemValConvdtoull: 6003; P8BE: # %bb.0: # %entry 6004; P8BE-NEXT: lxvdsx vs0, 0, r3 6005; P8BE-NEXT: xvcvdpuxds v2, vs0 6006; P8BE-NEXT: blr 6007; 6008; P8LE-LABEL: spltMemValConvdtoull: 6009; P8LE: # %bb.0: # %entry 6010; P8LE-NEXT: lxvdsx vs0, 0, r3 6011; P8LE-NEXT: xvcvdpuxds v2, vs0 6012; P8LE-NEXT: blr 6013entry: 6014 %0 = load double, ptr %ptr, align 8 6015 %conv = fptoui double %0 to i64 6016 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0 6017 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 6018 ret <2 x i64> %splat.splat 6019} 6020 6021; Some additional patterns that come up in real code. 6022define dso_local <2 x double> @sint_to_fp_widen02(<4 x i32> %a) { 6023; P9BE-LABEL: sint_to_fp_widen02: 6024; P9BE: # %bb.0: # %entry 6025; P9BE-NEXT: xvcvsxwdp v2, v2 6026; P9BE-NEXT: blr 6027; 6028; P9LE-LABEL: sint_to_fp_widen02: 6029; P9LE: # %bb.0: # %entry 6030; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6031; P9LE-NEXT: xvcvsxwdp v2, vs0 6032; P9LE-NEXT: blr 6033; 6034; P8BE-LABEL: sint_to_fp_widen02: 6035; P8BE: # %bb.0: # %entry 6036; P8BE-NEXT: xvcvsxwdp v2, v2 6037; P8BE-NEXT: blr 6038; 6039; P8LE-LABEL: sint_to_fp_widen02: 6040; P8LE: # %bb.0: # %entry 6041; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6042; P8LE-NEXT: xvcvsxwdp v2, vs0 6043; P8LE-NEXT: blr 6044entry: 6045 %vecext = extractelement <4 x i32> %a, i32 0 6046 %conv = sitofp i32 %vecext to double 6047 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6048 %vecext1 = extractelement <4 x i32> %a, i32 2 6049 %conv2 = sitofp i32 %vecext1 to double 6050 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6051 ret <2 x double> %vecinit3 6052} 6053 6054define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) { 6055; P9BE-LABEL: sint_to_fp_widen13: 6056; P9BE: # %bb.0: # %entry 6057; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6058; P9BE-NEXT: xvcvsxwdp v2, vs0 6059; P9BE-NEXT: blr 6060; 6061; P9LE-LABEL: sint_to_fp_widen13: 6062; P9LE: # %bb.0: # %entry 6063; P9LE-NEXT: xvcvsxwdp v2, v2 6064; P9LE-NEXT: blr 6065; 6066; P8BE-LABEL: sint_to_fp_widen13: 6067; P8BE: # %bb.0: # %entry 6068; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6069; P8BE-NEXT: xvcvsxwdp v2, vs0 6070; P8BE-NEXT: blr 6071; 6072; P8LE-LABEL: sint_to_fp_widen13: 6073; P8LE: # %bb.0: # %entry 6074; P8LE-NEXT: xvcvsxwdp v2, v2 6075; P8LE-NEXT: blr 6076entry: 6077 %vecext = extractelement <4 x i32> %a, i32 1 6078 %conv = sitofp i32 %vecext to double 6079 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6080 %vecext1 = extractelement <4 x i32> %a, i32 3 6081 %conv2 = sitofp i32 %vecext1 to double 6082 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6083 ret <2 x double> %vecinit3 6084} 6085 6086define dso_local <2 x double> @uint_to_fp_widen02(<4 x i32> %a) { 6087; P9BE-LABEL: uint_to_fp_widen02: 6088; P9BE: # %bb.0: # %entry 6089; P9BE-NEXT: xvcvuxwdp v2, v2 6090; P9BE-NEXT: blr 6091; 6092; P9LE-LABEL: uint_to_fp_widen02: 6093; P9LE: # %bb.0: # %entry 6094; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6095; P9LE-NEXT: xvcvuxwdp v2, vs0 6096; P9LE-NEXT: blr 6097; 6098; P8BE-LABEL: uint_to_fp_widen02: 6099; P8BE: # %bb.0: # %entry 6100; P8BE-NEXT: xvcvuxwdp v2, v2 6101; P8BE-NEXT: blr 6102; 6103; P8LE-LABEL: uint_to_fp_widen02: 6104; P8LE: # %bb.0: # %entry 6105; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6106; P8LE-NEXT: xvcvuxwdp v2, vs0 6107; P8LE-NEXT: blr 6108entry: 6109 %vecext = extractelement <4 x i32> %a, i32 0 6110 %conv = uitofp i32 %vecext to double 6111 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6112 %vecext1 = extractelement <4 x i32> %a, i32 2 6113 %conv2 = uitofp i32 %vecext1 to double 6114 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6115 ret <2 x double> %vecinit3 6116} 6117 6118define dso_local <2 x double> @uint_to_fp_widen13(<4 x i32> %a) { 6119; P9BE-LABEL: uint_to_fp_widen13: 6120; P9BE: # %bb.0: # %entry 6121; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6122; P9BE-NEXT: xvcvuxwdp v2, vs0 6123; P9BE-NEXT: blr 6124; 6125; P9LE-LABEL: uint_to_fp_widen13: 6126; P9LE: # %bb.0: # %entry 6127; P9LE-NEXT: xvcvuxwdp v2, v2 6128; P9LE-NEXT: blr 6129; 6130; P8BE-LABEL: uint_to_fp_widen13: 6131; P8BE: # %bb.0: # %entry 6132; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6133; P8BE-NEXT: xvcvuxwdp v2, vs0 6134; P8BE-NEXT: blr 6135; 6136; P8LE-LABEL: uint_to_fp_widen13: 6137; P8LE: # %bb.0: # %entry 6138; P8LE-NEXT: xvcvuxwdp v2, v2 6139; P8LE-NEXT: blr 6140entry: 6141 %vecext = extractelement <4 x i32> %a, i32 1 6142 %conv = uitofp i32 %vecext to double 6143 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6144 %vecext1 = extractelement <4 x i32> %a, i32 3 6145 %conv2 = uitofp i32 %vecext1 to double 6146 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6147 ret <2 x double> %vecinit3 6148} 6149 6150define dso_local <2 x double> @fp_extend01(<4 x float> %a) { 6151; P9BE-LABEL: fp_extend01: 6152; P9BE: # %bb.0: # %entry 6153; P9BE-NEXT: xxmrghw vs0, v2, v2 6154; P9BE-NEXT: xvcvspdp v2, vs0 6155; P9BE-NEXT: blr 6156; 6157; P9LE-LABEL: fp_extend01: 6158; P9LE: # %bb.0: # %entry 6159; P9LE-NEXT: xxmrglw vs0, v2, v2 6160; P9LE-NEXT: xvcvspdp v2, vs0 6161; P9LE-NEXT: blr 6162; 6163; P8BE-LABEL: fp_extend01: 6164; P8BE: # %bb.0: # %entry 6165; P8BE-NEXT: xxmrghw vs0, v2, v2 6166; P8BE-NEXT: xvcvspdp v2, vs0 6167; P8BE-NEXT: blr 6168; 6169; P8LE-LABEL: fp_extend01: 6170; P8LE: # %bb.0: # %entry 6171; P8LE-NEXT: xxmrglw vs0, v2, v2 6172; P8LE-NEXT: xvcvspdp v2, vs0 6173; P8LE-NEXT: blr 6174entry: 6175 %vecext = extractelement <4 x float> %a, i32 0 6176 %conv = fpext float %vecext to double 6177 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6178 %vecext1 = extractelement <4 x float> %a, i32 1 6179 %conv2 = fpext float %vecext1 to double 6180 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6181 ret <2 x double> %vecinit3 6182} 6183 6184define dso_local <2 x double> @fp_extend10(<4 x float> %a) { 6185; P9BE-LABEL: fp_extend10: 6186; P9BE: # %bb.0: # %entry 6187; P9BE-NEXT: xxmrghw vs0, v2, v2 6188; P9BE-NEXT: xvcvspdp vs0, vs0 6189; P9BE-NEXT: xxswapd v2, vs0 6190; P9BE-NEXT: blr 6191; 6192; P9LE-LABEL: fp_extend10: 6193; P9LE: # %bb.0: # %entry 6194; P9LE-NEXT: xxmrglw vs0, v2, v2 6195; P9LE-NEXT: xvcvspdp vs0, vs0 6196; P9LE-NEXT: xxswapd v2, vs0 6197; P9LE-NEXT: blr 6198; 6199; P8BE-LABEL: fp_extend10: 6200; P8BE: # %bb.0: # %entry 6201; P8BE-NEXT: xxmrghw vs0, v2, v2 6202; P8BE-NEXT: xvcvspdp vs0, vs0 6203; P8BE-NEXT: xxswapd v2, vs0 6204; P8BE-NEXT: blr 6205; 6206; P8LE-LABEL: fp_extend10: 6207; P8LE: # %bb.0: # %entry 6208; P8LE-NEXT: xxmrglw vs0, v2, v2 6209; P8LE-NEXT: xvcvspdp vs0, vs0 6210; P8LE-NEXT: xxswapd v2, vs0 6211; P8LE-NEXT: blr 6212entry: 6213 %vecext = extractelement <4 x float> %a, i32 1 6214 %conv = fpext float %vecext to double 6215 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6216 %vecext1 = extractelement <4 x float> %a, i32 0 6217 %conv2 = fpext float %vecext1 to double 6218 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6219 ret <2 x double> %vecinit3 6220} 6221 6222define dso_local <2 x double> @fp_extend02(<4 x float> %a) { 6223; P9BE-LABEL: fp_extend02: 6224; P9BE: # %bb.0: # %entry 6225; P9BE-NEXT: xvcvspdp v2, v2 6226; P9BE-NEXT: blr 6227; 6228; P9LE-LABEL: fp_extend02: 6229; P9LE: # %bb.0: # %entry 6230; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6231; P9LE-NEXT: xvcvspdp v2, vs0 6232; P9LE-NEXT: blr 6233; 6234; P8BE-LABEL: fp_extend02: 6235; P8BE: # %bb.0: # %entry 6236; P8BE-NEXT: xvcvspdp v2, v2 6237; P8BE-NEXT: blr 6238; 6239; P8LE-LABEL: fp_extend02: 6240; P8LE: # %bb.0: # %entry 6241; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6242; P8LE-NEXT: xvcvspdp v2, vs0 6243; P8LE-NEXT: blr 6244entry: 6245 %vecext = extractelement <4 x float> %a, i32 0 6246 %conv = fpext float %vecext to double 6247 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6248 %vecext1 = extractelement <4 x float> %a, i32 2 6249 %conv2 = fpext float %vecext1 to double 6250 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6251 ret <2 x double> %vecinit3 6252} 6253 6254define dso_local <2 x double> @fp_extend13(<4 x float> %a) { 6255; P9BE-LABEL: fp_extend13: 6256; P9BE: # %bb.0: # %entry 6257; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6258; P9BE-NEXT: xvcvspdp v2, vs0 6259; P9BE-NEXT: blr 6260; 6261; P9LE-LABEL: fp_extend13: 6262; P9LE: # %bb.0: # %entry 6263; P9LE-NEXT: xvcvspdp v2, v2 6264; P9LE-NEXT: blr 6265; 6266; P8BE-LABEL: fp_extend13: 6267; P8BE: # %bb.0: # %entry 6268; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6269; P8BE-NEXT: xvcvspdp v2, vs0 6270; P8BE-NEXT: blr 6271; 6272; P8LE-LABEL: fp_extend13: 6273; P8LE: # %bb.0: # %entry 6274; P8LE-NEXT: xvcvspdp v2, v2 6275; P8LE-NEXT: blr 6276entry: 6277 %vecext = extractelement <4 x float> %a, i32 1 6278 %conv = fpext float %vecext to double 6279 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6280 %vecext1 = extractelement <4 x float> %a, i32 3 6281 %conv2 = fpext float %vecext1 to double 6282 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6283 ret <2 x double> %vecinit3 6284} 6285 6286define dso_local <2 x double> @fp_extend23(<4 x float> %a) { 6287; P9BE-LABEL: fp_extend23: 6288; P9BE: # %bb.0: # %entry 6289; P9BE-NEXT: xxmrglw vs0, v2, v2 6290; P9BE-NEXT: xvcvspdp v2, vs0 6291; P9BE-NEXT: blr 6292; 6293; P9LE-LABEL: fp_extend23: 6294; P9LE: # %bb.0: # %entry 6295; P9LE-NEXT: xxmrghw vs0, v2, v2 6296; P9LE-NEXT: xvcvspdp v2, vs0 6297; P9LE-NEXT: blr 6298; 6299; P8BE-LABEL: fp_extend23: 6300; P8BE: # %bb.0: # %entry 6301; P8BE-NEXT: xxmrglw vs0, v2, v2 6302; P8BE-NEXT: xvcvspdp v2, vs0 6303; P8BE-NEXT: blr 6304; 6305; P8LE-LABEL: fp_extend23: 6306; P8LE: # %bb.0: # %entry 6307; P8LE-NEXT: xxmrghw vs0, v2, v2 6308; P8LE-NEXT: xvcvspdp v2, vs0 6309; P8LE-NEXT: blr 6310entry: 6311 %vecext = extractelement <4 x float> %a, i32 2 6312 %conv = fpext float %vecext to double 6313 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6314 %vecext1 = extractelement <4 x float> %a, i32 3 6315 %conv2 = fpext float %vecext1 to double 6316 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6317 ret <2 x double> %vecinit3 6318} 6319 6320define dso_local <2 x double> @fp_extend32(<4 x float> %a) { 6321; P9BE-LABEL: fp_extend32: 6322; P9BE: # %bb.0: # %entry 6323; P9BE-NEXT: xxmrglw vs0, v2, v2 6324; P9BE-NEXT: xvcvspdp vs0, vs0 6325; P9BE-NEXT: xxswapd v2, vs0 6326; P9BE-NEXT: blr 6327; 6328; P9LE-LABEL: fp_extend32: 6329; P9LE: # %bb.0: # %entry 6330; P9LE-NEXT: xxmrghw vs0, v2, v2 6331; P9LE-NEXT: xvcvspdp vs0, vs0 6332; P9LE-NEXT: xxswapd v2, vs0 6333; P9LE-NEXT: blr 6334; 6335; P8BE-LABEL: fp_extend32: 6336; P8BE: # %bb.0: # %entry 6337; P8BE-NEXT: xxmrglw vs0, v2, v2 6338; P8BE-NEXT: xvcvspdp vs0, vs0 6339; P8BE-NEXT: xxswapd v2, vs0 6340; P8BE-NEXT: blr 6341; 6342; P8LE-LABEL: fp_extend32: 6343; P8LE: # %bb.0: # %entry 6344; P8LE-NEXT: xxmrghw vs0, v2, v2 6345; P8LE-NEXT: xvcvspdp vs0, vs0 6346; P8LE-NEXT: xxswapd v2, vs0 6347; P8LE-NEXT: blr 6348entry: 6349 %vecext = extractelement <4 x float> %a, i32 3 6350 %conv = fpext float %vecext to double 6351 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6352 %vecext1 = extractelement <4 x float> %a, i32 2 6353 %conv2 = fpext float %vecext1 to double 6354 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6355 ret <2 x double> %vecinit3 6356} 6357 6358define dso_local <2 x double> @fp_extend_two00(<4 x float> %a, <4 x float> %b) { 6359; P9BE-LABEL: fp_extend_two00: 6360; P9BE: # %bb.0: # %entry 6361; P9BE-NEXT: xxmrghd vs0, v2, v3 6362; P9BE-NEXT: xvcvspdp v2, vs0 6363; P9BE-NEXT: blr 6364; 6365; P9LE-LABEL: fp_extend_two00: 6366; P9LE: # %bb.0: # %entry 6367; P9LE-NEXT: xxmrgld vs0, v3, v2 6368; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 1 6369; P9LE-NEXT: xvcvspdp v2, vs0 6370; P9LE-NEXT: blr 6371; 6372; P8BE-LABEL: fp_extend_two00: 6373; P8BE: # %bb.0: # %entry 6374; P8BE-NEXT: xxmrghd vs0, v2, v3 6375; P8BE-NEXT: xvcvspdp v2, vs0 6376; P8BE-NEXT: blr 6377; 6378; P8LE-LABEL: fp_extend_two00: 6379; P8LE: # %bb.0: # %entry 6380; P8LE-NEXT: xxmrgld vs0, v3, v2 6381; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 1 6382; P8LE-NEXT: xvcvspdp v2, vs0 6383; P8LE-NEXT: blr 6384entry: 6385 %vecext = extractelement <4 x float> %a, i32 0 6386 %conv = fpext float %vecext to double 6387 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6388 %vecext1 = extractelement <4 x float> %b, i32 0 6389 %conv2 = fpext float %vecext1 to double 6390 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6391 ret <2 x double> %vecinit3 6392} 6393 6394define dso_local <2 x double> @fp_extend_two33(<4 x float> %a, <4 x float> %b) { 6395; P9BE-LABEL: fp_extend_two33: 6396; P9BE: # %bb.0: # %entry 6397; P9BE-NEXT: xxmrgld vs0, v2, v3 6398; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 1 6399; P9BE-NEXT: xvcvspdp v2, vs0 6400; P9BE-NEXT: blr 6401; 6402; P9LE-LABEL: fp_extend_two33: 6403; P9LE: # %bb.0: # %entry 6404; P9LE-NEXT: xxmrghd vs0, v3, v2 6405; P9LE-NEXT: xvcvspdp v2, vs0 6406; P9LE-NEXT: blr 6407; 6408; P8BE-LABEL: fp_extend_two33: 6409; P8BE: # %bb.0: # %entry 6410; P8BE-NEXT: xxmrgld vs0, v2, v3 6411; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 1 6412; P8BE-NEXT: xvcvspdp v2, vs0 6413; P8BE-NEXT: blr 6414; 6415; P8LE-LABEL: fp_extend_two33: 6416; P8LE: # %bb.0: # %entry 6417; P8LE-NEXT: xxmrghd vs0, v3, v2 6418; P8LE-NEXT: xvcvspdp v2, vs0 6419; P8LE-NEXT: blr 6420entry: 6421 %vecext = extractelement <4 x float> %a, i32 3 6422 %conv = fpext float %vecext to double 6423 %vecinit = insertelement <2 x double> undef, double %conv, i32 0 6424 %vecext1 = extractelement <4 x float> %b, i32 3 6425 %conv2 = fpext float %vecext1 to double 6426 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 6427 ret <2 x double> %vecinit3 6428} 6429 6430define dso_local <2 x i64> @test_xvcvspsxds13(<4 x float> %a) local_unnamed_addr { 6431; P9BE-LABEL: test_xvcvspsxds13: 6432; P9BE: # %bb.0: # %entry 6433; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6434; P9BE-NEXT: xvcvspsxds v2, vs0 6435; P9BE-NEXT: blr 6436; 6437; P9LE-LABEL: test_xvcvspsxds13: 6438; P9LE: # %bb.0: # %entry 6439; P9LE-NEXT: xvcvspsxds v2, v2 6440; P9LE-NEXT: blr 6441; 6442; P8BE-LABEL: test_xvcvspsxds13: 6443; P8BE: # %bb.0: # %entry 6444; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6445; P8BE-NEXT: xvcvspsxds v2, vs0 6446; P8BE-NEXT: blr 6447; 6448; P8LE-LABEL: test_xvcvspsxds13: 6449; P8LE: # %bb.0: # %entry 6450; P8LE-NEXT: xvcvspsxds v2, v2 6451; P8LE-NEXT: blr 6452entry: 6453 %vecext = extractelement <4 x float> %a, i32 1 6454 %conv = fptosi float %vecext to i64 6455 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6456 %vecext1 = extractelement <4 x float> %a, i32 3 6457 %conv2 = fptosi float %vecext1 to i64 6458 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6459 ret <2 x i64> %vecinit3 6460} 6461 6462define dso_local <2 x i64> @test_xvcvspuxds13(<4 x float> %a) local_unnamed_addr { 6463; P9BE-LABEL: test_xvcvspuxds13: 6464; P9BE: # %bb.0: # %entry 6465; P9BE-NEXT: xxsldwi vs0, v2, v2, 1 6466; P9BE-NEXT: xvcvspuxds v2, vs0 6467; P9BE-NEXT: blr 6468; 6469; P9LE-LABEL: test_xvcvspuxds13: 6470; P9LE: # %bb.0: # %entry 6471; P9LE-NEXT: xvcvspuxds v2, v2 6472; P9LE-NEXT: blr 6473; 6474; P8BE-LABEL: test_xvcvspuxds13: 6475; P8BE: # %bb.0: # %entry 6476; P8BE-NEXT: xxsldwi vs0, v2, v2, 1 6477; P8BE-NEXT: xvcvspuxds v2, vs0 6478; P8BE-NEXT: blr 6479; 6480; P8LE-LABEL: test_xvcvspuxds13: 6481; P8LE: # %bb.0: # %entry 6482; P8LE-NEXT: xvcvspuxds v2, v2 6483; P8LE-NEXT: blr 6484entry: 6485 %vecext = extractelement <4 x float> %a, i32 1 6486 %conv = fptoui float %vecext to i64 6487 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6488 %vecext1 = extractelement <4 x float> %a, i32 3 6489 %conv2 = fptoui float %vecext1 to i64 6490 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6491 ret <2 x i64> %vecinit3 6492} 6493 6494define dso_local <2 x i64> @test_xvcvspsxds02(<4 x float> %a) local_unnamed_addr { 6495; P9BE-LABEL: test_xvcvspsxds02: 6496; P9BE: # %bb.0: # %entry 6497; P9BE-NEXT: xvcvspsxds v2, v2 6498; P9BE-NEXT: blr 6499; 6500; P9LE-LABEL: test_xvcvspsxds02: 6501; P9LE: # %bb.0: # %entry 6502; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6503; P9LE-NEXT: xvcvspsxds v2, vs0 6504; P9LE-NEXT: blr 6505; 6506; P8BE-LABEL: test_xvcvspsxds02: 6507; P8BE: # %bb.0: # %entry 6508; P8BE-NEXT: xvcvspsxds v2, v2 6509; P8BE-NEXT: blr 6510; 6511; P8LE-LABEL: test_xvcvspsxds02: 6512; P8LE: # %bb.0: # %entry 6513; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6514; P8LE-NEXT: xvcvspsxds v2, vs0 6515; P8LE-NEXT: blr 6516entry: 6517 %vecext = extractelement <4 x float> %a, i32 0 6518 %conv = fptosi float %vecext to i64 6519 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6520 %vecext1 = extractelement <4 x float> %a, i32 2 6521 %conv2 = fptosi float %vecext1 to i64 6522 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6523 ret <2 x i64> %vecinit3 6524} 6525 6526define dso_local <2 x i64> @test_xvcvspuxds02(<4 x float> %a) local_unnamed_addr { 6527; P9BE-LABEL: test_xvcvspuxds02: 6528; P9BE: # %bb.0: # %entry 6529; P9BE-NEXT: xvcvspuxds v2, v2 6530; P9BE-NEXT: blr 6531; 6532; P9LE-LABEL: test_xvcvspuxds02: 6533; P9LE: # %bb.0: # %entry 6534; P9LE-NEXT: xxsldwi vs0, v2, v2, 1 6535; P9LE-NEXT: xvcvspuxds v2, vs0 6536; P9LE-NEXT: blr 6537; 6538; P8BE-LABEL: test_xvcvspuxds02: 6539; P8BE: # %bb.0: # %entry 6540; P8BE-NEXT: xvcvspuxds v2, v2 6541; P8BE-NEXT: blr 6542; 6543; P8LE-LABEL: test_xvcvspuxds02: 6544; P8LE: # %bb.0: # %entry 6545; P8LE-NEXT: xxsldwi vs0, v2, v2, 1 6546; P8LE-NEXT: xvcvspuxds v2, vs0 6547; P8LE-NEXT: blr 6548entry: 6549 %vecext = extractelement <4 x float> %a, i32 0 6550 %conv = fptoui float %vecext to i64 6551 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0 6552 %vecext1 = extractelement <4 x float> %a, i32 2 6553 %conv2 = fptoui float %vecext1 to i64 6554 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1 6555 ret <2 x i64> %vecinit3 6556} 6557