1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr7 < %s | FileCheck --check-prefix=PWR7-BE %s 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck --check-prefix=PWR8-BE %s 4; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr7 < %s | FileCheck --check-prefix=PWR7-LE %s 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck --check-prefix=PWR8-LE %s 6 7define <2 x i64> @build_v2i64_extload_0(ptr nocapture noundef readonly %p) { 8; PWR7-BE-LABEL: build_v2i64_extload_0: 9; PWR7-BE: # %bb.0: # %entry 10; PWR7-BE-NEXT: lwz 3, 0(3) 11; PWR7-BE-NEXT: li 4, 0 12; PWR7-BE-NEXT: std 4, -8(1) 13; PWR7-BE-NEXT: std 3, -16(1) 14; PWR7-BE-NEXT: addi 3, 1, -16 15; PWR7-BE-NEXT: lxvd2x 34, 0, 3 16; PWR7-BE-NEXT: blr 17; 18; PWR8-BE-LABEL: build_v2i64_extload_0: 19; PWR8-BE: # %bb.0: # %entry 20; PWR8-BE-NEXT: lwz 3, 0(3) 21; PWR8-BE-NEXT: li 4, 0 22; PWR8-BE-NEXT: mtfprd 0, 4 23; PWR8-BE-NEXT: mtfprd 1, 3 24; PWR8-BE-NEXT: xxmrghd 34, 1, 0 25; PWR8-BE-NEXT: blr 26; 27; PWR7-LE-LABEL: build_v2i64_extload_0: 28; PWR7-LE: # %bb.0: # %entry 29; PWR7-LE-NEXT: lfiwzx 0, 0, 3 30; PWR7-LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha 31; PWR7-LE-NEXT: xxlxor 36, 36, 36 32; PWR7-LE-NEXT: addi 3, 3, .LCPI0_0@toc@l 33; PWR7-LE-NEXT: xxspltw 34, 0, 1 34; PWR7-LE-NEXT: lxvd2x 0, 0, 3 35; PWR7-LE-NEXT: xxswapd 35, 0 36; PWR7-LE-NEXT: vperm 2, 4, 2, 3 37; PWR7-LE-NEXT: blr 38; 39; PWR8-LE-LABEL: build_v2i64_extload_0: 40; PWR8-LE: # %bb.0: # %entry 41; PWR8-LE-NEXT: lwz 3, 0(3) 42; PWR8-LE-NEXT: li 4, 0 43; PWR8-LE-NEXT: rldimi 3, 4, 32, 0 44; PWR8-LE-NEXT: rldimi 4, 4, 32, 0 45; PWR8-LE-NEXT: mtfprd 0, 3 46; PWR8-LE-NEXT: mtfprd 1, 4 47; PWR8-LE-NEXT: xxmrghd 34, 1, 0 48; PWR8-LE-NEXT: blr 49entry: 50 %0 = load i32, ptr %p, align 4 51 %conv = zext i32 %0 to i64 52 %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %conv, i64 0 53 ret <2 x i64> %vecinit1 54} 55 56define <2 x i64> @build_v2i64_extload_1(ptr nocapture noundef readonly %p) { 57; PWR7-BE-LABEL: build_v2i64_extload_1: 58; PWR7-BE: # %bb.0: # %entry 59; PWR7-BE-NEXT: lwz 3, 0(3) 60; PWR7-BE-NEXT: li 4, 0 61; PWR7-BE-NEXT: std 4, -16(1) 62; PWR7-BE-NEXT: std 3, -8(1) 63; PWR7-BE-NEXT: addi 3, 1, -16 64; PWR7-BE-NEXT: lxvd2x 34, 0, 3 65; PWR7-BE-NEXT: blr 66; 67; PWR8-BE-LABEL: build_v2i64_extload_1: 68; PWR8-BE: # %bb.0: # %entry 69; PWR8-BE-NEXT: lwz 3, 0(3) 70; PWR8-BE-NEXT: li 4, 0 71; PWR8-BE-NEXT: mtfprd 0, 4 72; PWR8-BE-NEXT: mtfprd 1, 3 73; PWR8-BE-NEXT: xxmrghd 34, 0, 1 74; PWR8-BE-NEXT: blr 75; 76; PWR7-LE-LABEL: build_v2i64_extload_1: 77; PWR7-LE: # %bb.0: # %entry 78; PWR7-LE-NEXT: lwz 3, 0(3) 79; PWR7-LE-NEXT: li 4, 0 80; PWR7-LE-NEXT: std 4, -16(1) 81; PWR7-LE-NEXT: std 3, -8(1) 82; PWR7-LE-NEXT: addi 3, 1, -16 83; PWR7-LE-NEXT: lxvd2x 0, 0, 3 84; PWR7-LE-NEXT: xxswapd 34, 0 85; PWR7-LE-NEXT: blr 86; 87; PWR8-LE-LABEL: build_v2i64_extload_1: 88; PWR8-LE: # %bb.0: # %entry 89; PWR8-LE-NEXT: lwz 3, 0(3) 90; PWR8-LE-NEXT: li 4, 0 91; PWR8-LE-NEXT: mtfprd 0, 4 92; PWR8-LE-NEXT: mtfprd 1, 3 93; PWR8-LE-NEXT: xxmrghd 34, 1, 0 94; PWR8-LE-NEXT: blr 95entry: 96 %0 = load i32, ptr %p, align 4 97 %conv = zext i32 %0 to i64 98 %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %conv, i64 1 99 ret <2 x i64> %vecinit1 100} 101 102define <2 x double> @build_v2f64_extload_0(ptr nocapture noundef readonly %p) { 103; PWR7-BE-LABEL: build_v2f64_extload_0: 104; PWR7-BE: # %bb.0: # %entry 105; PWR7-BE-NEXT: lfs 0, 0(3) 106; PWR7-BE-NEXT: xxlxor 1, 1, 1 107; PWR7-BE-NEXT: xxmrghd 34, 0, 1 108; PWR7-BE-NEXT: blr 109; 110; PWR8-BE-LABEL: build_v2f64_extload_0: 111; PWR8-BE: # %bb.0: # %entry 112; PWR8-BE-NEXT: lfs 0, 0(3) 113; PWR8-BE-NEXT: xxlxor 1, 1, 1 114; PWR8-BE-NEXT: xxmrghd 34, 0, 1 115; PWR8-BE-NEXT: blr 116; 117; PWR7-LE-LABEL: build_v2f64_extload_0: 118; PWR7-LE: # %bb.0: # %entry 119; PWR7-LE-NEXT: lfs 0, 0(3) 120; PWR7-LE-NEXT: xxlxor 1, 1, 1 121; PWR7-LE-NEXT: xxmrghd 34, 1, 0 122; PWR7-LE-NEXT: blr 123; 124; PWR8-LE-LABEL: build_v2f64_extload_0: 125; PWR8-LE: # %bb.0: # %entry 126; PWR8-LE-NEXT: lfs 0, 0(3) 127; PWR8-LE-NEXT: xxlxor 1, 1, 1 128; PWR8-LE-NEXT: xxmrghd 34, 1, 0 129; PWR8-LE-NEXT: blr 130entry: 131 %0 = load float, ptr %p, align 4 132 %conv = fpext float %0 to double 133 %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %conv, i64 0 134 ret <2 x double> %vecinit1 135} 136 137define <2 x double> @build_v2f64_extload_1(ptr nocapture noundef readonly %p) { 138; PWR7-BE-LABEL: build_v2f64_extload_1: 139; PWR7-BE: # %bb.0: # %entry 140; PWR7-BE-NEXT: lfs 0, 0(3) 141; PWR7-BE-NEXT: xxlxor 1, 1, 1 142; PWR7-BE-NEXT: xxmrghd 34, 1, 0 143; PWR7-BE-NEXT: blr 144; 145; PWR8-BE-LABEL: build_v2f64_extload_1: 146; PWR8-BE: # %bb.0: # %entry 147; PWR8-BE-NEXT: lfs 0, 0(3) 148; PWR8-BE-NEXT: xxlxor 1, 1, 1 149; PWR8-BE-NEXT: xxmrghd 34, 1, 0 150; PWR8-BE-NEXT: blr 151; 152; PWR7-LE-LABEL: build_v2f64_extload_1: 153; PWR7-LE: # %bb.0: # %entry 154; PWR7-LE-NEXT: lfs 0, 0(3) 155; PWR7-LE-NEXT: xxlxor 1, 1, 1 156; PWR7-LE-NEXT: xxmrghd 34, 0, 1 157; PWR7-LE-NEXT: blr 158; 159; PWR8-LE-LABEL: build_v2f64_extload_1: 160; PWR8-LE: # %bb.0: # %entry 161; PWR8-LE-NEXT: lfs 0, 0(3) 162; PWR8-LE-NEXT: xxlxor 1, 1, 1 163; PWR8-LE-NEXT: xxmrghd 34, 0, 1 164; PWR8-LE-NEXT: blr 165entry: 166 %0 = load float, ptr %p, align 4 167 %conv = fpext float %0 to double 168 %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %conv, i64 1 169 ret <2 x double> %vecinit1 170} 171 172define <2 x double> @build_v2f64_load_0(ptr nocapture noundef readonly %p) { 173; PWR7-BE-LABEL: build_v2f64_load_0: 174; PWR7-BE: # %bb.0: # %entry 175; PWR7-BE-NEXT: lfd 0, 0(3) 176; PWR7-BE-NEXT: xxlxor 1, 1, 1 177; PWR7-BE-NEXT: xxmrghd 34, 0, 1 178; PWR7-BE-NEXT: blr 179; 180; PWR8-BE-LABEL: build_v2f64_load_0: 181; PWR8-BE: # %bb.0: # %entry 182; PWR8-BE-NEXT: lfd 0, 0(3) 183; PWR8-BE-NEXT: xxlxor 1, 1, 1 184; PWR8-BE-NEXT: xxmrghd 34, 0, 1 185; PWR8-BE-NEXT: blr 186; 187; PWR7-LE-LABEL: build_v2f64_load_0: 188; PWR7-LE: # %bb.0: # %entry 189; PWR7-LE-NEXT: lfd 0, 0(3) 190; PWR7-LE-NEXT: xxlxor 1, 1, 1 191; PWR7-LE-NEXT: xxmrghd 34, 1, 0 192; PWR7-LE-NEXT: blr 193; 194; PWR8-LE-LABEL: build_v2f64_load_0: 195; PWR8-LE: # %bb.0: # %entry 196; PWR8-LE-NEXT: lfd 0, 0(3) 197; PWR8-LE-NEXT: xxlxor 1, 1, 1 198; PWR8-LE-NEXT: xxmrghd 34, 1, 0 199; PWR8-LE-NEXT: blr 200entry: 201 %0 = load double, ptr %p, align 8 202 %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %0, i64 0 203 ret <2 x double> %vecinit1 204} 205 206define <2 x double> @build_v2f64_load_1(ptr nocapture noundef readonly %p) { 207; PWR7-BE-LABEL: build_v2f64_load_1: 208; PWR7-BE: # %bb.0: # %entry 209; PWR7-BE-NEXT: lfd 0, 0(3) 210; PWR7-BE-NEXT: xxlxor 1, 1, 1 211; PWR7-BE-NEXT: xxmrghd 34, 1, 0 212; PWR7-BE-NEXT: blr 213; 214; PWR8-BE-LABEL: build_v2f64_load_1: 215; PWR8-BE: # %bb.0: # %entry 216; PWR8-BE-NEXT: lfd 0, 0(3) 217; PWR8-BE-NEXT: xxlxor 1, 1, 1 218; PWR8-BE-NEXT: xxmrghd 34, 1, 0 219; PWR8-BE-NEXT: blr 220; 221; PWR7-LE-LABEL: build_v2f64_load_1: 222; PWR7-LE: # %bb.0: # %entry 223; PWR7-LE-NEXT: lfd 0, 0(3) 224; PWR7-LE-NEXT: xxlxor 1, 1, 1 225; PWR7-LE-NEXT: xxmrghd 34, 0, 1 226; PWR7-LE-NEXT: blr 227; 228; PWR8-LE-LABEL: build_v2f64_load_1: 229; PWR8-LE: # %bb.0: # %entry 230; PWR8-LE-NEXT: lfd 0, 0(3) 231; PWR8-LE-NEXT: xxlxor 1, 1, 1 232; PWR8-LE-NEXT: xxmrghd 34, 0, 1 233; PWR8-LE-NEXT: blr 234entry: 235 %0 = load double, ptr %p, align 8 236 %vecinit1 = insertelement <2 x double> <double 0.000000e+00, double 0.000000e+00>, double %0, i64 1 237 ret <2 x double> %vecinit1 238} 239 240define <2 x i64> @build_v2i64_load_0(ptr nocapture noundef readonly %p) { 241; PWR7-BE-LABEL: build_v2i64_load_0: 242; PWR7-BE: # %bb.0: # %entry 243; PWR7-BE-NEXT: ld 3, 0(3) 244; PWR7-BE-NEXT: li 4, 0 245; PWR7-BE-NEXT: std 4, -8(1) 246; PWR7-BE-NEXT: std 3, -16(1) 247; PWR7-BE-NEXT: addi 3, 1, -16 248; PWR7-BE-NEXT: lxvd2x 34, 0, 3 249; PWR7-BE-NEXT: blr 250; 251; PWR8-BE-LABEL: build_v2i64_load_0: 252; PWR8-BE: # %bb.0: # %entry 253; PWR8-BE-NEXT: ld 3, 0(3) 254; PWR8-BE-NEXT: li 4, 0 255; PWR8-BE-NEXT: mtfprd 0, 4 256; PWR8-BE-NEXT: mtfprd 1, 3 257; PWR8-BE-NEXT: xxmrghd 34, 1, 0 258; PWR8-BE-NEXT: blr 259; 260; PWR7-LE-LABEL: build_v2i64_load_0: 261; PWR7-LE: # %bb.0: # %entry 262; PWR7-LE-NEXT: ld 3, 0(3) 263; PWR7-LE-NEXT: li 4, 0 264; PWR7-LE-NEXT: std 4, -8(1) 265; PWR7-LE-NEXT: std 3, -16(1) 266; PWR7-LE-NEXT: addi 3, 1, -16 267; PWR7-LE-NEXT: lxvd2x 0, 0, 3 268; PWR7-LE-NEXT: xxswapd 34, 0 269; PWR7-LE-NEXT: blr 270; 271; PWR8-LE-LABEL: build_v2i64_load_0: 272; PWR8-LE: # %bb.0: # %entry 273; PWR8-LE-NEXT: ld 3, 0(3) 274; PWR8-LE-NEXT: li 4, 0 275; PWR8-LE-NEXT: mtfprd 0, 4 276; PWR8-LE-NEXT: mtfprd 1, 3 277; PWR8-LE-NEXT: xxmrghd 34, 0, 1 278; PWR8-LE-NEXT: blr 279entry: 280 %0 = load i64, ptr %p, align 8 281 %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %0, i64 0 282 ret <2 x i64> %vecinit1 283} 284 285define <2 x i64> @build_v2i64_load_1(ptr nocapture noundef readonly %p) { 286; PWR7-BE-LABEL: build_v2i64_load_1: 287; PWR7-BE: # %bb.0: # %entry 288; PWR7-BE-NEXT: ld 3, 0(3) 289; PWR7-BE-NEXT: li 4, 0 290; PWR7-BE-NEXT: std 4, -16(1) 291; PWR7-BE-NEXT: std 3, -8(1) 292; PWR7-BE-NEXT: addi 3, 1, -16 293; PWR7-BE-NEXT: lxvd2x 34, 0, 3 294; PWR7-BE-NEXT: blr 295; 296; PWR8-BE-LABEL: build_v2i64_load_1: 297; PWR8-BE: # %bb.0: # %entry 298; PWR8-BE-NEXT: ld 3, 0(3) 299; PWR8-BE-NEXT: li 4, 0 300; PWR8-BE-NEXT: mtfprd 0, 4 301; PWR8-BE-NEXT: mtfprd 1, 3 302; PWR8-BE-NEXT: xxmrghd 34, 0, 1 303; PWR8-BE-NEXT: blr 304; 305; PWR7-LE-LABEL: build_v2i64_load_1: 306; PWR7-LE: # %bb.0: # %entry 307; PWR7-LE-NEXT: ld 3, 0(3) 308; PWR7-LE-NEXT: li 4, 0 309; PWR7-LE-NEXT: std 4, -16(1) 310; PWR7-LE-NEXT: std 3, -8(1) 311; PWR7-LE-NEXT: addi 3, 1, -16 312; PWR7-LE-NEXT: lxvd2x 0, 0, 3 313; PWR7-LE-NEXT: xxswapd 34, 0 314; PWR7-LE-NEXT: blr 315; 316; PWR8-LE-LABEL: build_v2i64_load_1: 317; PWR8-LE: # %bb.0: # %entry 318; PWR8-LE-NEXT: ld 3, 0(3) 319; PWR8-LE-NEXT: li 4, 0 320; PWR8-LE-NEXT: mtfprd 0, 4 321; PWR8-LE-NEXT: mtfprd 1, 3 322; PWR8-LE-NEXT: xxmrghd 34, 1, 0 323; PWR8-LE-NEXT: blr 324entry: 325 %0 = load i64, ptr %p, align 8 326 %vecinit1 = insertelement <2 x i64> <i64 0, i64 0>, i64 %0, i64 1 327 ret <2 x i64> %vecinit1 328} 329 330define <4 x i32> @build_v4i32_load_0(ptr nocapture noundef readonly %p) { 331; PWR7-BE-LABEL: build_v4i32_load_0: 332; PWR7-BE: # %bb.0: # %entry 333; PWR7-BE-NEXT: lfiwzx 0, 0, 3 334; PWR7-BE-NEXT: addis 3, 2, .LCPI8_0@toc@ha 335; PWR7-BE-NEXT: xxlxor 36, 36, 36 336; PWR7-BE-NEXT: addi 3, 3, .LCPI8_0@toc@l 337; PWR7-BE-NEXT: lxvw4x 35, 0, 3 338; PWR7-BE-NEXT: xxspltw 34, 0, 1 339; PWR7-BE-NEXT: vperm 2, 2, 4, 3 340; PWR7-BE-NEXT: blr 341; 342; PWR8-BE-LABEL: build_v4i32_load_0: 343; PWR8-BE: # %bb.0: # %entry 344; PWR8-BE-NEXT: lwz 3, 0(3) 345; PWR8-BE-NEXT: li 4, 0 346; PWR8-BE-NEXT: li 5, 0 347; PWR8-BE-NEXT: rldimi 4, 4, 32, 0 348; PWR8-BE-NEXT: rldimi 5, 3, 32, 0 349; PWR8-BE-NEXT: mtfprd 1, 4 350; PWR8-BE-NEXT: mtfprd 0, 5 351; PWR8-BE-NEXT: xxmrghd 34, 0, 1 352; PWR8-BE-NEXT: blr 353; 354; PWR7-LE-LABEL: build_v4i32_load_0: 355; PWR7-LE: # %bb.0: # %entry 356; PWR7-LE-NEXT: lfiwzx 0, 0, 3 357; PWR7-LE-NEXT: addis 3, 2, .LCPI8_0@toc@ha 358; PWR7-LE-NEXT: xxlxor 36, 36, 36 359; PWR7-LE-NEXT: addi 3, 3, .LCPI8_0@toc@l 360; PWR7-LE-NEXT: xxspltw 34, 0, 1 361; PWR7-LE-NEXT: lxvd2x 0, 0, 3 362; PWR7-LE-NEXT: xxswapd 35, 0 363; PWR7-LE-NEXT: vperm 2, 4, 2, 3 364; PWR7-LE-NEXT: blr 365; 366; PWR8-LE-LABEL: build_v4i32_load_0: 367; PWR8-LE: # %bb.0: # %entry 368; PWR8-LE-NEXT: lwz 3, 0(3) 369; PWR8-LE-NEXT: li 4, 0 370; PWR8-LE-NEXT: rldimi 3, 4, 32, 0 371; PWR8-LE-NEXT: rldimi 4, 4, 32, 0 372; PWR8-LE-NEXT: mtfprd 0, 3 373; PWR8-LE-NEXT: mtfprd 1, 4 374; PWR8-LE-NEXT: xxmrghd 34, 1, 0 375; PWR8-LE-NEXT: blr 376entry: 377 %0 = load i32, ptr %p, align 4 378 %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 0 379 ret <4 x i32> %vecinit1 380} 381 382define <4 x i32> @build_v4i32_load_1(ptr nocapture noundef readonly %p) { 383; PWR7-BE-LABEL: build_v4i32_load_1: 384; PWR7-BE: # %bb.0: # %entry 385; PWR7-BE-NEXT: lfiwzx 0, 0, 3 386; PWR7-BE-NEXT: addis 3, 2, .LCPI9_0@toc@ha 387; PWR7-BE-NEXT: xxlxor 36, 36, 36 388; PWR7-BE-NEXT: addi 3, 3, .LCPI9_0@toc@l 389; PWR7-BE-NEXT: lxvw4x 35, 0, 3 390; PWR7-BE-NEXT: xxspltw 34, 0, 1 391; PWR7-BE-NEXT: vperm 2, 4, 2, 3 392; PWR7-BE-NEXT: blr 393; 394; PWR8-BE-LABEL: build_v4i32_load_1: 395; PWR8-BE: # %bb.0: # %entry 396; PWR8-BE-NEXT: lwz 3, 0(3) 397; PWR8-BE-NEXT: li 4, 0 398; PWR8-BE-NEXT: rldimi 3, 4, 32, 0 399; PWR8-BE-NEXT: rldimi 4, 4, 32, 0 400; PWR8-BE-NEXT: mtfprd 0, 3 401; PWR8-BE-NEXT: mtfprd 1, 4 402; PWR8-BE-NEXT: xxmrghd 34, 0, 1 403; PWR8-BE-NEXT: blr 404; 405; PWR7-LE-LABEL: build_v4i32_load_1: 406; PWR7-LE: # %bb.0: # %entry 407; PWR7-LE-NEXT: lfiwzx 0, 0, 3 408; PWR7-LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha 409; PWR7-LE-NEXT: xxlxor 36, 36, 36 410; PWR7-LE-NEXT: addi 3, 3, .LCPI9_0@toc@l 411; PWR7-LE-NEXT: xxspltw 34, 0, 1 412; PWR7-LE-NEXT: lxvd2x 0, 0, 3 413; PWR7-LE-NEXT: xxswapd 35, 0 414; PWR7-LE-NEXT: vperm 2, 2, 4, 3 415; PWR7-LE-NEXT: blr 416; 417; PWR8-LE-LABEL: build_v4i32_load_1: 418; PWR8-LE: # %bb.0: # %entry 419; PWR8-LE-NEXT: lwz 3, 0(3) 420; PWR8-LE-NEXT: li 4, 0 421; PWR8-LE-NEXT: li 5, 0 422; PWR8-LE-NEXT: rldimi 4, 4, 32, 0 423; PWR8-LE-NEXT: rldimi 5, 3, 32, 0 424; PWR8-LE-NEXT: mtfprd 1, 4 425; PWR8-LE-NEXT: mtfprd 0, 5 426; PWR8-LE-NEXT: xxmrghd 34, 1, 0 427; PWR8-LE-NEXT: blr 428entry: 429 %0 = load i32, ptr %p, align 4 430 %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 1 431 ret <4 x i32> %vecinit1 432} 433 434define <4 x i32> @build_v4i32_load_2(ptr nocapture noundef readonly %p) { 435; PWR7-BE-LABEL: build_v4i32_load_2: 436; PWR7-BE: # %bb.0: # %entry 437; PWR7-BE-NEXT: lfiwzx 0, 0, 3 438; PWR7-BE-NEXT: addis 3, 2, .LCPI10_0@toc@ha 439; PWR7-BE-NEXT: xxlxor 36, 36, 36 440; PWR7-BE-NEXT: addi 3, 3, .LCPI10_0@toc@l 441; PWR7-BE-NEXT: lxvw4x 35, 0, 3 442; PWR7-BE-NEXT: xxspltw 34, 0, 1 443; PWR7-BE-NEXT: vperm 2, 4, 2, 3 444; PWR7-BE-NEXT: blr 445; 446; PWR8-BE-LABEL: build_v4i32_load_2: 447; PWR8-BE: # %bb.0: # %entry 448; PWR8-BE-NEXT: lwz 3, 0(3) 449; PWR8-BE-NEXT: li 4, 0 450; PWR8-BE-NEXT: li 5, 0 451; PWR8-BE-NEXT: rldimi 4, 4, 32, 0 452; PWR8-BE-NEXT: rldimi 5, 3, 32, 0 453; PWR8-BE-NEXT: mtfprd 1, 4 454; PWR8-BE-NEXT: mtfprd 0, 5 455; PWR8-BE-NEXT: xxmrghd 34, 1, 0 456; PWR8-BE-NEXT: blr 457; 458; PWR7-LE-LABEL: build_v4i32_load_2: 459; PWR7-LE: # %bb.0: # %entry 460; PWR7-LE-NEXT: lfiwzx 0, 0, 3 461; PWR7-LE-NEXT: addis 3, 2, .LCPI10_0@toc@ha 462; PWR7-LE-NEXT: xxlxor 36, 36, 36 463; PWR7-LE-NEXT: addi 3, 3, .LCPI10_0@toc@l 464; PWR7-LE-NEXT: xxspltw 34, 0, 1 465; PWR7-LE-NEXT: lxvd2x 0, 0, 3 466; PWR7-LE-NEXT: xxswapd 35, 0 467; PWR7-LE-NEXT: vperm 2, 2, 4, 3 468; PWR7-LE-NEXT: blr 469; 470; PWR8-LE-LABEL: build_v4i32_load_2: 471; PWR8-LE: # %bb.0: # %entry 472; PWR8-LE-NEXT: lwz 3, 0(3) 473; PWR8-LE-NEXT: li 4, 0 474; PWR8-LE-NEXT: rldimi 3, 4, 32, 0 475; PWR8-LE-NEXT: rldimi 4, 4, 32, 0 476; PWR8-LE-NEXT: mtfprd 0, 3 477; PWR8-LE-NEXT: mtfprd 1, 4 478; PWR8-LE-NEXT: xxmrghd 34, 0, 1 479; PWR8-LE-NEXT: blr 480entry: 481 %0 = load i32, ptr %p, align 4 482 %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 2 483 ret <4 x i32> %vecinit1 484} 485 486define <4 x i32> @build_v4i32_load_3(ptr nocapture noundef readonly %p) { 487; PWR7-BE-LABEL: build_v4i32_load_3: 488; PWR7-BE: # %bb.0: # %entry 489; PWR7-BE-NEXT: lfiwzx 0, 0, 3 490; PWR7-BE-NEXT: addis 3, 2, .LCPI11_0@toc@ha 491; PWR7-BE-NEXT: xxlxor 36, 36, 36 492; PWR7-BE-NEXT: addi 3, 3, .LCPI11_0@toc@l 493; PWR7-BE-NEXT: lxvw4x 35, 0, 3 494; PWR7-BE-NEXT: xxspltw 34, 0, 1 495; PWR7-BE-NEXT: vperm 2, 4, 2, 3 496; PWR7-BE-NEXT: blr 497; 498; PWR8-BE-LABEL: build_v4i32_load_3: 499; PWR8-BE: # %bb.0: # %entry 500; PWR8-BE-NEXT: lwz 3, 0(3) 501; PWR8-BE-NEXT: li 4, 0 502; PWR8-BE-NEXT: rldimi 3, 4, 32, 0 503; PWR8-BE-NEXT: rldimi 4, 4, 32, 0 504; PWR8-BE-NEXT: mtfprd 0, 3 505; PWR8-BE-NEXT: mtfprd 1, 4 506; PWR8-BE-NEXT: xxmrghd 34, 1, 0 507; PWR8-BE-NEXT: blr 508; 509; PWR7-LE-LABEL: build_v4i32_load_3: 510; PWR7-LE: # %bb.0: # %entry 511; PWR7-LE-NEXT: lfiwzx 0, 0, 3 512; PWR7-LE-NEXT: addis 3, 2, .LCPI11_0@toc@ha 513; PWR7-LE-NEXT: xxlxor 36, 36, 36 514; PWR7-LE-NEXT: addi 3, 3, .LCPI11_0@toc@l 515; PWR7-LE-NEXT: xxspltw 34, 0, 1 516; PWR7-LE-NEXT: lxvd2x 0, 0, 3 517; PWR7-LE-NEXT: xxswapd 35, 0 518; PWR7-LE-NEXT: vperm 2, 2, 4, 3 519; PWR7-LE-NEXT: blr 520; 521; PWR8-LE-LABEL: build_v4i32_load_3: 522; PWR8-LE: # %bb.0: # %entry 523; PWR8-LE-NEXT: lwz 3, 0(3) 524; PWR8-LE-NEXT: li 4, 0 525; PWR8-LE-NEXT: li 5, 0 526; PWR8-LE-NEXT: rldimi 4, 4, 32, 0 527; PWR8-LE-NEXT: rldimi 5, 3, 32, 0 528; PWR8-LE-NEXT: mtfprd 1, 4 529; PWR8-LE-NEXT: mtfprd 0, 5 530; PWR8-LE-NEXT: xxmrghd 34, 0, 1 531; PWR8-LE-NEXT: blr 532entry: 533 %0 = load i32, ptr %p, align 4 534 %vecinit1 = insertelement <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i32 %0, i32 3 535 ret <4 x i32> %vecinit1 536} 537 538define <4 x float> @build_v4f32_load_0(ptr nocapture noundef readonly %p) { 539; PWR7-BE-LABEL: build_v4f32_load_0: 540; PWR7-BE: # %bb.0: # %entry 541; PWR7-BE-NEXT: lwz 3, 0(3) 542; PWR7-BE-NEXT: li 4, 0 543; PWR7-BE-NEXT: stw 4, -16(1) 544; PWR7-BE-NEXT: stw 3, -32(1) 545; PWR7-BE-NEXT: addis 3, 2, .LCPI12_0@toc@ha 546; PWR7-BE-NEXT: addi 3, 3, .LCPI12_0@toc@l 547; PWR7-BE-NEXT: lxvw4x 34, 0, 3 548; PWR7-BE-NEXT: addi 3, 1, -16 549; PWR7-BE-NEXT: lxvw4x 35, 0, 3 550; PWR7-BE-NEXT: addi 3, 1, -32 551; PWR7-BE-NEXT: lxvw4x 36, 0, 3 552; PWR7-BE-NEXT: vperm 2, 4, 3, 2 553; PWR7-BE-NEXT: blr 554; 555; PWR8-BE-LABEL: build_v4f32_load_0: 556; PWR8-BE: # %bb.0: # %entry 557; PWR8-BE-NEXT: lfs 0, 0(3) 558; PWR8-BE-NEXT: xxlxor 1, 1, 1 559; PWR8-BE-NEXT: xxmrghd 0, 0, 1 560; PWR8-BE-NEXT: xxspltd 1, 1, 0 561; PWR8-BE-NEXT: xvcvdpsp 34, 0 562; PWR8-BE-NEXT: xvcvdpsp 35, 1 563; PWR8-BE-NEXT: vmrgew 2, 2, 3 564; PWR8-BE-NEXT: blr 565; 566; PWR7-LE-LABEL: build_v4f32_load_0: 567; PWR7-LE: # %bb.0: # %entry 568; PWR7-LE-NEXT: li 4, 0 569; PWR7-LE-NEXT: lwz 3, 0(3) 570; PWR7-LE-NEXT: stw 4, -16(1) 571; PWR7-LE-NEXT: addis 4, 2, .LCPI12_0@toc@ha 572; PWR7-LE-NEXT: addi 4, 4, .LCPI12_0@toc@l 573; PWR7-LE-NEXT: stw 3, -32(1) 574; PWR7-LE-NEXT: addi 3, 1, -32 575; PWR7-LE-NEXT: lxvd2x 0, 0, 4 576; PWR7-LE-NEXT: addi 4, 1, -16 577; PWR7-LE-NEXT: lxvd2x 1, 0, 4 578; PWR7-LE-NEXT: xxswapd 34, 0 579; PWR7-LE-NEXT: lxvd2x 0, 0, 3 580; PWR7-LE-NEXT: xxswapd 35, 1 581; PWR7-LE-NEXT: xxswapd 36, 0 582; PWR7-LE-NEXT: vperm 2, 3, 4, 2 583; PWR7-LE-NEXT: blr 584; 585; PWR8-LE-LABEL: build_v4f32_load_0: 586; PWR8-LE: # %bb.0: # %entry 587; PWR8-LE-NEXT: lfs 0, 0(3) 588; PWR8-LE-NEXT: xxlxor 1, 1, 1 589; PWR8-LE-NEXT: xxmrghd 0, 1, 0 590; PWR8-LE-NEXT: xxspltd 1, 1, 0 591; PWR8-LE-NEXT: xvcvdpsp 34, 0 592; PWR8-LE-NEXT: xvcvdpsp 35, 1 593; PWR8-LE-NEXT: vmrgew 2, 3, 2 594; PWR8-LE-NEXT: blr 595entry: 596 %0 = load float, ptr %p, align 4 597 %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 0 598 ret <4 x float> %vecinit1 599} 600 601define <4 x float> @build_v4f32_load_1(ptr nocapture noundef readonly %p) { 602; PWR7-BE-LABEL: build_v4f32_load_1: 603; PWR7-BE: # %bb.0: # %entry 604; PWR7-BE-NEXT: lwz 3, 0(3) 605; PWR7-BE-NEXT: li 4, 0 606; PWR7-BE-NEXT: stw 4, -32(1) 607; PWR7-BE-NEXT: stw 3, -16(1) 608; PWR7-BE-NEXT: addis 3, 2, .LCPI13_0@toc@ha 609; PWR7-BE-NEXT: addi 3, 3, .LCPI13_0@toc@l 610; PWR7-BE-NEXT: lxvw4x 34, 0, 3 611; PWR7-BE-NEXT: addi 3, 1, -32 612; PWR7-BE-NEXT: lxvw4x 35, 0, 3 613; PWR7-BE-NEXT: addi 3, 1, -16 614; PWR7-BE-NEXT: lxvw4x 36, 0, 3 615; PWR7-BE-NEXT: vperm 2, 3, 4, 2 616; PWR7-BE-NEXT: blr 617; 618; PWR8-BE-LABEL: build_v4f32_load_1: 619; PWR8-BE: # %bb.0: # %entry 620; PWR8-BE-NEXT: lfs 0, 0(3) 621; PWR8-BE-NEXT: xxlxor 1, 1, 1 622; PWR8-BE-NEXT: xxmrghd 0, 0, 1 623; PWR8-BE-NEXT: xxspltd 1, 1, 0 624; PWR8-BE-NEXT: xvcvdpsp 34, 0 625; PWR8-BE-NEXT: xvcvdpsp 35, 1 626; PWR8-BE-NEXT: vmrgew 2, 3, 2 627; PWR8-BE-NEXT: blr 628; 629; PWR7-LE-LABEL: build_v4f32_load_1: 630; PWR7-LE: # %bb.0: # %entry 631; PWR7-LE-NEXT: li 4, 0 632; PWR7-LE-NEXT: lwz 3, 0(3) 633; PWR7-LE-NEXT: stw 4, -32(1) 634; PWR7-LE-NEXT: addis 4, 2, .LCPI13_0@toc@ha 635; PWR7-LE-NEXT: addi 4, 4, .LCPI13_0@toc@l 636; PWR7-LE-NEXT: stw 3, -16(1) 637; PWR7-LE-NEXT: addi 3, 1, -16 638; PWR7-LE-NEXT: lxvd2x 0, 0, 4 639; PWR7-LE-NEXT: addi 4, 1, -32 640; PWR7-LE-NEXT: lxvd2x 1, 0, 4 641; PWR7-LE-NEXT: xxswapd 34, 0 642; PWR7-LE-NEXT: lxvd2x 0, 0, 3 643; PWR7-LE-NEXT: xxswapd 35, 1 644; PWR7-LE-NEXT: xxswapd 36, 0 645; PWR7-LE-NEXT: vperm 2, 4, 3, 2 646; PWR7-LE-NEXT: blr 647; 648; PWR8-LE-LABEL: build_v4f32_load_1: 649; PWR8-LE: # %bb.0: # %entry 650; PWR8-LE-NEXT: lfs 0, 0(3) 651; PWR8-LE-NEXT: xxlxor 1, 1, 1 652; PWR8-LE-NEXT: xxmrghd 0, 1, 0 653; PWR8-LE-NEXT: xxspltd 1, 1, 0 654; PWR8-LE-NEXT: xvcvdpsp 34, 0 655; PWR8-LE-NEXT: xvcvdpsp 35, 1 656; PWR8-LE-NEXT: vmrgew 2, 2, 3 657; PWR8-LE-NEXT: blr 658entry: 659 %0 = load float, ptr %p, align 4 660 %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 1 661 ret <4 x float> %vecinit1 662} 663 664define <4 x float> @build_v4f32_load_2(ptr nocapture noundef readonly %p) { 665; PWR7-BE-LABEL: build_v4f32_load_2: 666; PWR7-BE: # %bb.0: # %entry 667; PWR7-BE-NEXT: lwz 3, 0(3) 668; PWR7-BE-NEXT: li 4, 0 669; PWR7-BE-NEXT: stw 4, -32(1) 670; PWR7-BE-NEXT: stw 3, -16(1) 671; PWR7-BE-NEXT: addis 3, 2, .LCPI14_0@toc@ha 672; PWR7-BE-NEXT: addi 3, 3, .LCPI14_0@toc@l 673; PWR7-BE-NEXT: lxvw4x 34, 0, 3 674; PWR7-BE-NEXT: addi 3, 1, -32 675; PWR7-BE-NEXT: lxvw4x 35, 0, 3 676; PWR7-BE-NEXT: addi 3, 1, -16 677; PWR7-BE-NEXT: lxvw4x 36, 0, 3 678; PWR7-BE-NEXT: vperm 2, 3, 4, 2 679; PWR7-BE-NEXT: blr 680; 681; PWR8-BE-LABEL: build_v4f32_load_2: 682; PWR8-BE: # %bb.0: # %entry 683; PWR8-BE-NEXT: lfs 0, 0(3) 684; PWR8-BE-NEXT: xxlxor 1, 1, 1 685; PWR8-BE-NEXT: xxmrghd 0, 1, 0 686; PWR8-BE-NEXT: xxspltd 1, 1, 0 687; PWR8-BE-NEXT: xvcvdpsp 34, 0 688; PWR8-BE-NEXT: xvcvdpsp 35, 1 689; PWR8-BE-NEXT: vmrgew 2, 2, 3 690; PWR8-BE-NEXT: blr 691; 692; PWR7-LE-LABEL: build_v4f32_load_2: 693; PWR7-LE: # %bb.0: # %entry 694; PWR7-LE-NEXT: li 4, 0 695; PWR7-LE-NEXT: lwz 3, 0(3) 696; PWR7-LE-NEXT: stw 4, -32(1) 697; PWR7-LE-NEXT: addis 4, 2, .LCPI14_0@toc@ha 698; PWR7-LE-NEXT: addi 4, 4, .LCPI14_0@toc@l 699; PWR7-LE-NEXT: stw 3, -16(1) 700; PWR7-LE-NEXT: addi 3, 1, -16 701; PWR7-LE-NEXT: lxvd2x 0, 0, 4 702; PWR7-LE-NEXT: addi 4, 1, -32 703; PWR7-LE-NEXT: lxvd2x 1, 0, 4 704; PWR7-LE-NEXT: xxswapd 34, 0 705; PWR7-LE-NEXT: lxvd2x 0, 0, 3 706; PWR7-LE-NEXT: xxswapd 35, 1 707; PWR7-LE-NEXT: xxswapd 36, 0 708; PWR7-LE-NEXT: vperm 2, 4, 3, 2 709; PWR7-LE-NEXT: blr 710; 711; PWR8-LE-LABEL: build_v4f32_load_2: 712; PWR8-LE: # %bb.0: # %entry 713; PWR8-LE-NEXT: lfs 0, 0(3) 714; PWR8-LE-NEXT: xxlxor 1, 1, 1 715; PWR8-LE-NEXT: xxmrghd 0, 0, 1 716; PWR8-LE-NEXT: xxspltd 1, 1, 0 717; PWR8-LE-NEXT: xvcvdpsp 34, 0 718; PWR8-LE-NEXT: xvcvdpsp 35, 1 719; PWR8-LE-NEXT: vmrgew 2, 3, 2 720; PWR8-LE-NEXT: blr 721entry: 722 %0 = load float, ptr %p, align 4 723 %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 2 724 ret <4 x float> %vecinit1 725} 726 727define <4 x float> @build_v4f32_load_3(ptr nocapture noundef readonly %p) { 728; PWR7-BE-LABEL: build_v4f32_load_3: 729; PWR7-BE: # %bb.0: # %entry 730; PWR7-BE-NEXT: lwz 3, 0(3) 731; PWR7-BE-NEXT: li 4, 0 732; PWR7-BE-NEXT: stw 4, -32(1) 733; PWR7-BE-NEXT: stw 3, -16(1) 734; PWR7-BE-NEXT: addis 3, 2, .LCPI15_0@toc@ha 735; PWR7-BE-NEXT: addi 3, 3, .LCPI15_0@toc@l 736; PWR7-BE-NEXT: lxvw4x 34, 0, 3 737; PWR7-BE-NEXT: addi 3, 1, -32 738; PWR7-BE-NEXT: lxvw4x 35, 0, 3 739; PWR7-BE-NEXT: addi 3, 1, -16 740; PWR7-BE-NEXT: lxvw4x 36, 0, 3 741; PWR7-BE-NEXT: vperm 2, 3, 4, 2 742; PWR7-BE-NEXT: blr 743; 744; PWR8-BE-LABEL: build_v4f32_load_3: 745; PWR8-BE: # %bb.0: # %entry 746; PWR8-BE-NEXT: lfs 0, 0(3) 747; PWR8-BE-NEXT: xxlxor 1, 1, 1 748; PWR8-BE-NEXT: xxmrghd 0, 1, 0 749; PWR8-BE-NEXT: xxspltd 1, 1, 0 750; PWR8-BE-NEXT: xvcvdpsp 34, 0 751; PWR8-BE-NEXT: xvcvdpsp 35, 1 752; PWR8-BE-NEXT: vmrgew 2, 3, 2 753; PWR8-BE-NEXT: blr 754; 755; PWR7-LE-LABEL: build_v4f32_load_3: 756; PWR7-LE: # %bb.0: # %entry 757; PWR7-LE-NEXT: li 4, 0 758; PWR7-LE-NEXT: lwz 3, 0(3) 759; PWR7-LE-NEXT: stw 4, -32(1) 760; PWR7-LE-NEXT: addis 4, 2, .LCPI15_0@toc@ha 761; PWR7-LE-NEXT: addi 4, 4, .LCPI15_0@toc@l 762; PWR7-LE-NEXT: stw 3, -16(1) 763; PWR7-LE-NEXT: addi 3, 1, -16 764; PWR7-LE-NEXT: lxvd2x 0, 0, 4 765; PWR7-LE-NEXT: addi 4, 1, -32 766; PWR7-LE-NEXT: lxvd2x 1, 0, 4 767; PWR7-LE-NEXT: xxswapd 34, 0 768; PWR7-LE-NEXT: lxvd2x 0, 0, 3 769; PWR7-LE-NEXT: xxswapd 35, 1 770; PWR7-LE-NEXT: xxswapd 36, 0 771; PWR7-LE-NEXT: vperm 2, 4, 3, 2 772; PWR7-LE-NEXT: blr 773; 774; PWR8-LE-LABEL: build_v4f32_load_3: 775; PWR8-LE: # %bb.0: # %entry 776; PWR8-LE-NEXT: lfs 0, 0(3) 777; PWR8-LE-NEXT: xxlxor 1, 1, 1 778; PWR8-LE-NEXT: xxmrghd 0, 0, 1 779; PWR8-LE-NEXT: xxspltd 1, 1, 0 780; PWR8-LE-NEXT: xvcvdpsp 34, 0 781; PWR8-LE-NEXT: xvcvdpsp 35, 1 782; PWR8-LE-NEXT: vmrgew 2, 2, 3 783; PWR8-LE-NEXT: blr 784entry: 785 %0 = load float, ptr %p, align 4 786 %vecinit1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %0, i32 3 787 ret <4 x float> %vecinit1 788} 789