1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 3 4; equivalent C code 5; struct s64 { 6; int a:5; 7; int b:16; 8; long c:42; 9; }; 10; void bitfieldinsert64(struct s *p, unsigned short v) { 11; p->b = v; 12; } 13 14%struct.s64 = type { i64 } 15 16define void @bitfieldinsert64(ptr nocapture %p, i16 zeroext %v) { 17; CHECK-LABEL: @bitfieldinsert64 18; CHECK: ld [[REG1:[0-9]+]], 0(3) 19; CHECK-NEXT: rlwimi [[REG1]], 4, 5, 11, 26 20; CHECK-NEXT: std [[REG1]], 0(3) 21; CHECK-NEXT: blr 22entry: 23 %0 = zext i16 %v to i64 24 %bf.load = load i64, ptr %p, align 8 25 %bf.shl = shl nuw nsw i64 %0, 5 26 %bf.clear = and i64 %bf.load, -2097121 27 %bf.set = or i64 %bf.clear, %bf.shl 28 store i64 %bf.set, ptr %p, align 8 29 ret void 30} 31 32; bitfieldinsert32: Test for rlwimi 33; equivalent C code 34; struct s32 { 35; int a:8; 36; int b:16; 37; int c:8; 38; }; 39; void bitfieldinsert32(struct s32 *p, unsigned int v) { 40; p->b = v; 41; } 42 43%struct.s32 = type { i32 } 44 45define void @bitfieldinsert32(ptr nocapture %p, i32 zeroext %v) { 46; CHECK-LABEL: @bitfieldinsert32 47; CHECK: lwz [[REG1:[0-9]+]], 0(3) 48; CHECK-NEXT: rlwimi [[REG1]], 4, 8, 8, 23 49; CHECK-NEXT: stw [[REG1]], 0(3) 50; CHECK-NEXT: blr 51entry: 52 %bf.load = load i32, ptr %p, align 4 53 %bf.value = shl i32 %v, 8 54 %bf.shl = and i32 %bf.value, 16776960 55 %bf.clear = and i32 %bf.load, -16776961 56 %bf.set = or i32 %bf.clear, %bf.shl 57 store i32 %bf.set, ptr %p, align 4 58 ret void 59} 60 61; test cases which include ISD::TRUNCATE 62; equivalent C code 63; struct s64b { 64; int a:4; 65; int b:16; 66; int c:24; 67; }; 68; void bitfieldinsert64b(struct s64b *p, unsigned char v) { 69; p->b = v; 70; } 71 72%struct.s64b = type { i24, i24 } 73 74define void @bitfieldinsert64b(ptr nocapture %p, i8 zeroext %v) { 75; CHECK-LABEL: @bitfieldinsert64b 76; CHECK: lwz [[REG1:[0-9]+]], 0(3) 77; CHECK-NEXT: rlwimi [[REG1]], 4, 4, 12, 27 78; CHECK-NEXT: stw [[REG1]], 0(3) 79; CHECK-NEXT: blr 80entry: 81 %conv = zext i8 %v to i32 82 %bf.load = load i32, ptr %p, align 4 83 %bf.shl = shl nuw nsw i32 %conv, 4 84 %bf.clear = and i32 %bf.load, -1048561 85 %bf.set = or i32 %bf.clear, %bf.shl 86 store i32 %bf.set, ptr %p, align 4 87 ret void 88} 89 90; equivalent C code 91; struct s64c { 92; int a:5; 93; int b:16; 94; long c:10; 95; }; 96; void bitfieldinsert64c(struct s64c *p, unsigned short v) { 97; p->b = v; 98; } 99 100%struct.s64c = type { i32, [4 x i8] } 101 102define void @bitfieldinsert64c(ptr nocapture %p, i16 zeroext %v) { 103; CHECK-LABEL: @bitfieldinsert64c 104; CHECK: lwz [[REG1:[0-9]+]], 0(3) 105; CHECK-NEXT: rlwimi [[REG1]], 4, 5, 11, 26 106; CHECK-NEXT: stw [[REG1]], 0(3) 107; CHECK-NEXT: blr 108entry: 109 %conv = zext i16 %v to i32 110 %bf.load = load i32, ptr %p, align 8 111 %bf.shl = shl nuw nsw i32 %conv, 5 112 %bf.clear = and i32 %bf.load, -2097121 113 %bf.set = or i32 %bf.clear, %bf.shl 114 store i32 %bf.set, ptr %p, align 8 115 ret void 116} 117